blob: 3cca1769c203918e06eec9071fb58ae66f101952 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley0cdebbd2015-03-30 17:15:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010034#include <auth_mod.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010035#include <bl1.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <bl_common.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010037#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010038#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010039#include <platform_def.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010040#include <smcc_helpers.h>
Dan Handleybcd60ba2014-04-17 18:53:42 +010041#include "bl1_private.h"
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010042#include <uuid.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010043
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010044/* BL1 Service UUID */
45DEFINE_SVC_UUID(bl1_svc_uid,
46 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
47 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
48
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010049
Yatharth Kochara65be2f2015-10-09 18:06:13 +010050static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010051
Sandrine Bailleux467d0572014-06-24 14:02:34 +010052/*******************************************************************************
53 * The next function has a weak definition. Platform specific code can override
54 * it if it wishes to.
55 ******************************************************************************/
56#pragma weak bl1_init_bl2_mem_layout
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010057
58/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010059 * Function that takes a memory layout into which BL2 has been loaded and
60 * populates a new memory layout for BL2 that ensures that BL1's data sections
61 * resident in secure RAM are not visible to BL2.
62 ******************************************************************************/
63void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
64 meminfo_t *bl2_mem_layout)
65{
66 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
67
68 assert(bl1_mem_layout != NULL);
69 assert(bl2_mem_layout != NULL);
70
71 /* Check that BL1's memory is lying outside of the free memory */
72 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
Yatharth Kochara65be2f2015-10-09 18:06:13 +010073 (BL1_RAM_BASE >= bl1_mem_layout->free_base +
74 bl1_mem_layout->free_size));
Sandrine Bailleux467d0572014-06-24 14:02:34 +010075
76 /* Remove BL1 RW data from the scope of memory visible to BL2 */
77 *bl2_mem_layout = *bl1_mem_layout;
78 reserve_mem(&bl2_mem_layout->total_base,
79 &bl2_mem_layout->total_size,
80 BL1_RAM_BASE,
81 bl1_size);
82
83 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
84}
85
86/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010087 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +010088 * It also queries the platform to load and run next BL image. Only called
89 * by the primary cpu after a cold boot.
90 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +010091void bl1_main(void)
92{
Yatharth Kochara65be2f2015-10-09 18:06:13 +010093 unsigned int image_id;
94
Dan Handley91b624e2014-07-29 17:14:00 +010095 /* Announce our arrival */
96 NOTICE(FIRMWARE_WELCOME_STR);
97 NOTICE("BL1: %s\n", version_string);
98 NOTICE("BL1: %s\n", build_message);
99
100 INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
101
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102
Dan Handley0cdebbd2015-03-30 17:15:16 +0100103#if DEBUG
104 unsigned long val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 /*
106 * Ensure that MMU/Caches and coherency are turned on
107 */
Dan Handley0cdebbd2015-03-30 17:15:16 +0100108 val = read_sctlr_el3();
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100109 assert(val & SCTLR_M_BIT);
110 assert(val & SCTLR_C_BIT);
111 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100112 /*
113 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
114 * provided platform value
115 */
116 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
117 /*
118 * If CWG is zero, then no CWG information is available but we can
119 * at least check the platform value is less than the architectural
120 * maximum.
121 */
122 if (val != 0)
123 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
124 else
125 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
126#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127
128 /* Perform remaining generic architectural setup from EL3 */
129 bl1_arch_setup();
130
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100131#if TRUSTED_BOARD_BOOT
132 /* Initialize authentication module */
133 auth_mod_init();
134#endif /* TRUSTED_BOARD_BOOT */
135
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 /* Perform platform setup in BL1. */
137 bl1_platform_setup();
138
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100139 /* Get the image id of next image to load and run. */
140 image_id = bl1_plat_get_next_image_id();
141
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100142 /*
143 * We currently interpret any image id other than
144 * BL2_IMAGE_ID as the start of firmware update.
145 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100146 if (image_id == BL2_IMAGE_ID)
147 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100148 else
149 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100150
151 bl1_prepare_next_image(image_id);
152}
153
154/*******************************************************************************
155 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
156 * Called by the primary cpu after a cold boot.
157 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
158 * loader etc.
159 ******************************************************************************/
160void bl1_load_bl2(void)
161{
162 image_desc_t *image_desc;
163 image_info_t *image_info;
164 entry_point_info_t *ep_info;
165 meminfo_t *bl1_tzram_layout;
166 meminfo_t *bl2_tzram_layout;
167 int err;
168
169 /* Get the image descriptor */
170 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
171 assert(image_desc);
172
173 /* Get the image info */
174 image_info = &image_desc->image_info;
175
176 /* Get the entry point info */
177 ep_info = &image_desc->ep_info;
Vikram Kanigirida567432014-04-15 18:08:08 +0100178
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100179 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000180 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100181
Juan Castillo3a66aca2015-04-13 17:36:19 +0100182 INFO("BL1: Loading BL2\n");
183
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100184 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100185 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100186 BL2_IMAGE_ID,
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100187 image_info->image_base,
188 image_info,
189 ep_info);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100190
Vikram Kanigirida567432014-04-15 18:08:08 +0100191 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100192 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100193 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100194 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000195
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196 /*
197 * Create a new layout of memory for BL2 as seen by BL1 i.e.
198 * tell it the amount of total and free memory available.
199 * This layout is created at the first free address visible
200 * to BL2. BL2 will read the memory layout before using its
201 * memory for other purposes.
202 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100203 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100204 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100206 ep_info->args.arg1 = (unsigned long)bl2_tzram_layout;
207 NOTICE("BL1: Booting BL2\n");
208 VERBOSE("BL1: BL2 memory layout address = 0x%llx\n",
209 (unsigned long long) bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210}
211
212/*******************************************************************************
Sandrine Bailleux33c95cc2015-10-27 15:52:33 +0000213 * Function called just before handing over to BL31 to inform the user about
214 * the boot progress. In debug mode, also print details about the BL31 image's
215 * execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216 ******************************************************************************/
Sandrine Bailleux33c95cc2015-10-27 15:52:33 +0000217void bl1_print_bl31_ep_info(const entry_point_info_t *bl31_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218{
Juan Castillo7d199412015-12-14 09:35:25 +0000219 NOTICE("BL1: Booting BL31\n");
Sandrine Bailleuxb2e224c2015-09-28 17:03:06 +0100220 print_entry_point_info(bl31_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000222
223#if SPIN_ON_BL1_EXIT
224void print_debug_loop_message(void)
225{
226 NOTICE("BL1: Debug loop, spinning forever\n");
227 NOTICE("BL1: Please connect the debugger to continue\n");
228}
229#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100230
231/*******************************************************************************
232 * Top level handler for servicing BL1 SMCs.
233 ******************************************************************************/
234register_t bl1_smc_handler(unsigned int smc_fid,
235 register_t x1,
236 register_t x2,
237 register_t x3,
238 register_t x4,
239 void *cookie,
240 void *handle,
241 unsigned int flags)
242{
243
244#if TRUSTED_BOARD_BOOT
245 /*
246 * Dispatch FWU calls to FWU SMC handler and return its return
247 * value
248 */
249 if (is_fwu_fid(smc_fid)) {
250 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
251 handle, flags);
252 }
253#endif
254
255 switch (smc_fid) {
256 case BL1_SMC_CALL_COUNT:
257 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
258
259 case BL1_SMC_UID:
260 SMC_UUID_RET(handle, bl1_svc_uid);
261
262 case BL1_SMC_VERSION:
263 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
264
265 default:
266 break;
267 }
268
269 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
270 SMC_RET1(handle, SMC_UNK);
271}