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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A User Guide
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010011tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +000012Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +010013possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
Joel Huttonfe027712018-03-19 11:59:57 +000041The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
Dan Handley610e7e12018-03-01 18:44:00 +000051Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010052
53::
54
Sathees Balya2d0aeb02018-07-10 14:46:51 +010055 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
Douglas Raillardd7c21b72017-06-28 15:23:03 +010056
Dan Handley610e7e12018-03-01 18:44:00 +000057TF-A has been tested with `Linaro Release 17.10`_.
David Cunadob2de0992017-06-29 12:01:33 +010058
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010060The `Linaro Release Notes`_ documents which version of the compiler to use for a
61given Linaro Release. Also, these `Linaro instructions`_ provide further
62guidance and a script, which can be used to download Linaro deliverables
63automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
Roberto Vargas0489bc02018-04-16 15:43:26 +010065Optionally, TF-A can be built using clang version 4.0 or newer or Arm
66Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010067
68In addition, the following optional packages and tools may be needed:
69
70- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
71 Tree (FDT) source files (``.dts`` files) provided with this software.
72
Dan Handley610e7e12018-03-01 18:44:00 +000073- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010074
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010075- To create and modify the diagram files included in the documentation, `Dia`_.
76 This tool can be found in most Linux distributions. Inkscape is needed to
77 generate the actual *.png files.
78
Dan Handley610e7e12018-03-01 18:44:00 +000079Getting the TF-A source code
80----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010081
Dan Handley610e7e12018-03-01 18:44:00 +000082Download the TF-A source code from Github:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010083
84::
85
86 git clone https://github.com/ARM-software/arm-trusted-firmware.git
87
Dan Handley610e7e12018-03-01 18:44:00 +000088Building TF-A
89-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010090
Dan Handley610e7e12018-03-01 18:44:00 +000091- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
92 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010093
94 For AArch64:
95
96 ::
97
98 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
99
100 For AArch32:
101
102 ::
103
104 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
105
Roberto Vargas07b1e242018-04-23 08:38:12 +0100106 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
107 ``CC`` needs to point to the clang or armclang binary, which will
108 also select the clang or armclang assembler. Be aware that the
109 GNU linker is used by default. In case of being needed the linker
110 can be overriden using the ``LD`` variable. Clang linker version 6 is
111 known to work with TF-A.
112
113 In both cases ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100114
Dan Handley610e7e12018-03-01 18:44:00 +0000115 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116 to ``CC`` matches the string 'armclang'.
117
Dan Handley610e7e12018-03-01 18:44:00 +0000118 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100119
120 ::
121
122 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
123 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
124
125 Clang will be selected when the base name of the path assigned to ``CC``
126 contains the string 'clang'. This is to allow both clang and clang-X.Y
127 to work.
128
129 For AArch64 using clang:
130
131 ::
132
133 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
134 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
135
Dan Handley610e7e12018-03-01 18:44:00 +0000136- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137
138 For AArch64:
139
140 ::
141
142 make PLAT=<platform> all
143
144 For AArch32:
145
146 ::
147
148 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
149
150 Notes:
151
152 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
153 `Summary of build options`_ for more information on available build
154 options.
155
156 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
157
158 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
159 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000160 provided by TF-A to demonstrate how PSCI Library can be integrated with
161 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
162 include other runtime services, for example Trusted OS services. A guide
163 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
164 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100165
166 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
167 image, is not compiled in by default. Refer to the
168 `Building the Test Secure Payload`_ section below.
169
170 - By default this produces a release version of the build. To produce a
171 debug version instead, refer to the "Debugging options" section below.
172
173 - The build process creates products in a ``build`` directory tree, building
174 the objects and binaries for each boot loader stage in separate
175 sub-directories. The following boot loader binary files are created
176 from the corresponding ELF files:
177
178 - ``build/<platform>/<build-type>/bl1.bin``
179 - ``build/<platform>/<build-type>/bl2.bin``
180 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
181 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
182
183 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
184 is either ``debug`` or ``release``. The actual number of images might differ
185 depending on the platform.
186
187- Build products for a specific build variant can be removed using:
188
189 ::
190
191 make DEBUG=<D> PLAT=<platform> clean
192
193 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
194
195 The build tree can be removed completely using:
196
197 ::
198
199 make realclean
200
201Summary of build options
202~~~~~~~~~~~~~~~~~~~~~~~~
203
Dan Handley610e7e12018-03-01 18:44:00 +0000204The TF-A build system supports the following build options. Unless mentioned
205otherwise, these options are expected to be specified at the build command
206line and are not to be modified in any component makefiles. Note that the
207build system doesn't track dependency for build options. Therefore, if any of
208the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100209performed.
210
211Common build options
212^^^^^^^^^^^^^^^^^^^^
213
214- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
215 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
216 directory containing the SP source, relative to the ``bl32/``; the directory
217 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
218
Dan Handley610e7e12018-03-01 18:44:00 +0000219- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
220 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
221 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100222
Dan Handley610e7e12018-03-01 18:44:00 +0000223- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
224 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
225 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
226 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100227
Dan Handley610e7e12018-03-01 18:44:00 +0000228- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
229 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
230 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100231
Dan Handley610e7e12018-03-01 18:44:00 +0000232- ``ARM_GIC_ARCH``: Choice of Arm GIC architecture version used by the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100233 Legacy GIC driver for implementing the platform GIC API. This API is used
234 by the interrupt management framework. Default is 2 (that is, version 2.0).
235 This build option is deprecated.
236
Dan Handley610e7e12018-03-01 18:44:00 +0000237- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000238 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
239 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
240 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
241 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000244 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
245 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100246
247- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000248 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100249
John Tsichritzisee10e792018-06-06 09:38:10 +0100250- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000251 BL2 at EL3 execution level.
252
John Tsichritzisee10e792018-06-06 09:38:10 +0100253- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000254 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
255 the RW sections in RAM, while leaving the RO sections in place. This option
256 enable this use-case. For now, this option is only supported when BL2_AT_EL3
257 is set to '1'.
258
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000260 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
261 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100262
263- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
264 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
265 this file name will be used to save the key.
266
267- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000268 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
269 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100270
John Tsichritzisee10e792018-06-06 09:38:10 +0100271- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100272 Trusted OS Extra1 image for the ``fip`` target.
273
John Tsichritzisee10e792018-06-06 09:38:10 +0100274- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100275 Trusted OS Extra2 image for the ``fip`` target.
276
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
278 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
279 this file name will be used to save the key.
280
281- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000282 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100283
284- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
285 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
286 this file name will be used to save the key.
287
288- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
289 compilation of each build. It must be set to a C string (including quotes
290 where applicable). Defaults to a string that contains the time and date of
291 the compilation.
292
Dan Handley610e7e12018-03-01 18:44:00 +0000293- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A
294 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100295
296- ``CFLAGS``: Extra user options appended on the compiler's command line in
297 addition to the options set by the build system.
298
299- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
300 release several CPUs out of reset. It can take either 0 (several CPUs may be
301 brought up) or 1 (only one CPU will ever be brought up during cold reset).
302 Default is 0. If the platform always brings up a single CPU, there is no
303 need to distinguish between primary and secondary CPUs and the boot path can
304 be optimised. The ``plat_is_my_cpu_primary()`` and
305 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
306 to be implemented in this case.
307
308- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
309 register state when an unexpected exception occurs during execution of
310 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
311 this is only enabled for a debug build of the firmware.
312
313- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
314 certificate generation tool to create new keys in case no valid keys are
315 present or specified. Allowed options are '0' or '1'. Default is '1'.
316
317- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
318 the AArch32 system registers to be included when saving and restoring the
319 CPU context. The option must be set to 0 for AArch64-only platforms (that
320 is on hardware that does not implement AArch32, or at least not at EL1 and
321 higher ELs). Default value is 1.
322
323- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
324 registers to be included when saving and restoring the CPU context. Default
325 is 0.
326
327- ``DEBUG``: Chooses between a debug and release build. It can take either 0
328 (release) or 1 (debug) as values. 0 is the default.
329
John Tsichritzisee10e792018-06-06 09:38:10 +0100330- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
331 Board Boot authentication at runtime. This option is meant to be enabled only
332 for development platforms. Both TRUSTED_BOARD_BOOT and LOAD_IMAGE_V2 flags
333 must be set if this flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100334
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
336 the normal boot flow. It must specify the entry point address of the EL3
337 payload. Please refer to the "Booting an EL3 payload" section for more
338 details.
339
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100340- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100341 This is an optional architectural feature available on v8.4 onwards. Some
342 v8.2 implementations also implement an AMU and this option can be used to
343 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100344
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100345- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
346 are compiled out. For debug builds, this option defaults to 1, and calls to
347 ``assert()`` are left in place. For release builds, this option defaults to 0
348 and calls to ``assert()`` function are compiled out. This option can be set
349 independently of ``DEBUG``. It can also be used to hide any auxiliary code
350 that is only required for the assertion and does not fit in the assertion
351 itself.
352
353- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
354 Measurement Framework(PMF). Default is 0.
355
356- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
357 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
358 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
359 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
360 software.
361
362- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000363 instrumentation which injects timestamp collection points into TF-A to
364 allow runtime performance to be measured. Currently, only PSCI is
365 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
366 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100367
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100368- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100369 extensions. This is an optional architectural feature for AArch64.
370 The default is 1 but is automatically disabled when the target architecture
371 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100372
David Cunadoce88eee2017-10-20 11:30:57 +0100373- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
374 (SVE) for the Non-secure world only. SVE is an optional architectural feature
375 for AArch64. Note that when SVE is enabled for the Non-secure world, access
376 to SIMD and floating-point functionality from the Secure world is disabled.
377 This is to avoid corruption of the Non-secure world data in the Z-registers
378 which are aliased by the SIMD and FP registers. The build option is not
379 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
380 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
381 1. The default is 1 but is automatically disabled when the target
382 architecture is AArch32.
383
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100384- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
385 checks in GCC. Allowed values are "all", "strong" and "0" (default).
386 "strong" is the recommended stack protection level if this feature is
387 desired. 0 disables the stack protection. For all values other than 0, the
388 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
389 The value is passed as the last component of the option
390 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
391
392- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
393 deprecated platform APIs, helper functions or drivers within Trusted
394 Firmware as error. It can take the value 1 (flag the use of deprecated
395 APIs as error) or 0. The default is 0.
396
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100397- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
398 targeted at EL3. When set ``0`` (default), no exceptions are expected or
399 handled at EL3, and a panic will result. This is supported only for AArch64
400 builds.
401
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000402- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 externsions introduced support for fault
403 injection from lower ELs, and this build option enables lower ELs to use
404 Error Records accessed via System Registers to inject faults. This is
405 applicable only to AArch64 builds.
406
407 This feature is intended for testing purposes only, and is advisable to keep
408 disabled for production images.
409
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100410- ``FIP_NAME``: This is an optional build option which specifies the FIP
411 filename for the ``fip`` target. Default is ``fip.bin``.
412
413- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
414 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
415
416- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
417 tool to create certificates as per the Chain of Trust described in
418 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
419 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
420
421 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
422 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
423 the corresponding certificates, and to include those certificates in the
424 FIP and FWU\_FIP.
425
426 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
427 images will not include support for Trusted Board Boot. The FIP will still
428 include the corresponding certificates. This FIP can be used to verify the
429 Chain of Trust on the host machine through other mechanisms.
430
431 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
432 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
433 will not include the corresponding certificates, causing a boot failure.
434
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100435- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
436 inherent support for specific EL3 type interrupts. Setting this build option
437 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
438 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
439 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
440 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
441 the Secure Payload interrupts needs to be synchronously handed over to Secure
442 EL1 for handling. The default value of this option is ``0``, which means the
443 Group 0 interrupts are assumed to be handled by Secure EL1.
444
445 .. __: `platform-interrupt-controller-API.rst`
446 .. __: `interrupt-framework-design.rst`
447
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100448- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
449 will be always trapped in EL3 i.e. in BL31 at runtime.
450
Dan Handley610e7e12018-03-01 18:44:00 +0000451- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100452 software operations are required for CPUs to enter and exit coherency.
453 However, there exists newer systems where CPUs' entry to and exit from
454 coherency is managed in hardware. Such systems require software to only
455 initiate the operations, and the rest is managed in hardware, minimizing
Dan Handley610e7e12018-03-01 18:44:00 +0000456 active software management. In such systems, this boolean option enables
457 TF-A to carry out build and run-time optimizations during boot and power
458 management operations. This option defaults to 0 and if it is enabled,
459 then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100460
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100461 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
462 translation library (xlat tables v2) must be used; version 1 of translation
463 library is not supported.
464
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100465- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
466 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
467 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
468 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
469 images.
470
Soby Mathew13b16052017-08-31 11:49:32 +0100471- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
472 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800473 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100474 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
475 retained only for compatibility. The default value of this flag is ``rsa``
476 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100477
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800478- ``HASH_ALG``: This build flag enables the user to select the secure hash
479 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
480 The default value of this flag is ``sha256``.
481
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100482- ``LDFLAGS``: Extra user options appended to the linkers' command line in
483 addition to the one set by the build system.
484
485- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
486 image loading, which provides more flexibility and scalability around what
487 images are loaded and executed during boot. Default is 0.
John Tsichritzis6dda9762018-07-23 09:18:04 +0100488
489 Note: this flag must be enabled for AArch32 builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100490
491- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
492 output compiled into the build. This should be one of the following:
493
494 ::
495
496 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100497 10 (LOG_LEVEL_ERROR)
498 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100499 30 (LOG_LEVEL_WARNING)
500 40 (LOG_LEVEL_INFO)
501 50 (LOG_LEVEL_VERBOSE)
502
503 All log output up to and including the log level is compiled into the build.
504 The default value is 40 in debug builds and 20 in release builds.
505
506- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
507 specifies the file that contains the Non-Trusted World private key in PEM
508 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
509
510- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
511 optional. It is only needed if the platform makefile specifies that it
512 is required in order to build the ``fwu_fip`` target.
513
514- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
515 contents upon world switch. It can take either 0 (don't save and restore) or
516 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
517 wants the timer registers to be saved and restored.
518
519- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
520 the underlying hardware is not a full PL011 UART but a minimally compliant
521 generic UART, which is a subset of the PL011. The driver will not access
522 any register that is not part of the SBSA generic UART specification.
523 Default value is 0 (a full PL011 compliant UART is present).
524
Dan Handley610e7e12018-03-01 18:44:00 +0000525- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
526 must be subdirectory of any depth under ``plat/``, and must contain a
527 platform makefile named ``platform.mk``. For example, to build TF-A for the
528 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100529
530- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
531 instead of the normal boot flow. When defined, it must specify the entry
532 point address for the preloaded BL33 image. This option is incompatible with
533 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
534 over ``PRELOADED_BL33_BASE``.
535
536- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
537 vector address can be programmed or is fixed on the platform. It can take
538 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
539 programmable reset address, it is expected that a CPU will start executing
540 code directly at the right address, both on a cold and warm reset. In this
541 case, there is no need to identify the entrypoint on boot and the boot path
542 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
543 does not need to be implemented in this case.
544
545- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
546 possible for the PSCI power-state parameter viz original and extended
547 State-ID formats. This flag if set to 1, configures the generic PSCI layer
548 to use the extended format. The default value of this flag is 0, which
549 means by default the original power-state format is used by the PSCI
550 implementation. This flag should be specified by the platform makefile
551 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
Dan Handley610e7e12018-03-01 18:44:00 +0000552 smc function id. When this option is enabled on Arm platforms, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100553 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
554
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100555- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
556 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
557 or later CPUs.
558
559 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
560 set to ``1``.
561
562 This option is disabled by default.
563
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100564- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
565 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
566 entrypoint) or 1 (CPU reset to BL31 entrypoint).
567 The default value is 0.
568
Dan Handley610e7e12018-03-01 18:44:00 +0000569- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided
570 in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector
571 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
572 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100573
574- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
575 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
576 file name will be used to save the key.
577
578- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
579 certificate generation tool to save the keys used to establish the Chain of
580 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
581
582- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
583 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
584 target.
585
586- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
587 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
588 this file name will be used to save the key.
589
590- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
591 optional. It is only needed if the platform makefile specifies that it
592 is required in order to build the ``fwu_fip`` target.
593
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100594- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
595 Delegated Exception Interface to BL31 image. This defaults to ``0``.
596
597 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
598 set to ``1``.
599
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100600- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
601 isolated on separate memory pages. This is a trade-off between security and
602 memory usage. See "Isolating code and read-only data on separate memory
603 pages" section in `Firmware Design`_. This flag is disabled by default and
604 affects all BL images.
605
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100606- ``SMCCC_MAJOR_VERSION``: Numeric value that indicates the major version of
607 the SMC Calling Convention that the Trusted Firmware supports. The only two
608 allowed values are 1 and 2, and it defaults to 1. The minor version is
609 determined using this value.
610
Dan Handley610e7e12018-03-01 18:44:00 +0000611- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
612 This build option is only valid if ``ARCH=aarch64``. The value should be
613 the path to the directory containing the SPD source, relative to
614 ``services/spd/``; the directory is expected to contain a makefile called
615 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100616
617- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
618 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
619 execution in BL1 just before handing over to BL31. At this point, all
620 firmware images have been loaded in memory, and the MMU and caches are
621 turned off. Refer to the "Debugging options" section for more details.
622
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100623- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200624 secure interrupts (caught through the FIQ line). Platforms can enable
625 this directive if they need to handle such interruption. When enabled,
626 the FIQ are handled in monitor mode and non secure world is not allowed
627 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
628 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
629
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100630- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
631 Boot feature. When set to '1', BL1 and BL2 images include support to load
632 and verify the certificates and images in a FIP, and BL1 includes support
633 for the Firmware Update. The default value is '0'. Generation and inclusion
634 of certificates in the FIP and FWU\_FIP depends upon the value of the
635 ``GENERATE_COT`` option.
636
637 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
638 already exist in disk, they will be overwritten without further notice.
639
640- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
641 specifies the file that contains the Trusted World private key in PEM
642 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
643
644- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
645 synchronous, (see "Initializing a BL32 Image" section in
646 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
647 synchronous method) or 1 (BL32 is initialized using asynchronous method).
648 Default is 0.
649
650- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
651 routing model which routes non-secure interrupts asynchronously from TSP
652 to EL3 causing immediate preemption of TSP. The EL3 is responsible
653 for saving and restoring the TSP context in this routing model. The
654 default routing model (when the value is 0) is to route non-secure
655 interrupts to TSP allowing it to save its context and hand over
656 synchronously to EL3 via an SMC.
657
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000658 Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
659 must also be set to ``1``.
660
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100661- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
662 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000663 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100664 (Coherent memory region is included) or 0 (Coherent memory region is
665 excluded). Default is 1.
666
667- ``V``: Verbose build. If assigned anything other than 0, the build commands
668 are printed. Default is 0.
669
Dan Handley610e7e12018-03-01 18:44:00 +0000670- ``VERSION_STRING``: String used in the log output for each TF-A image.
671 Defaults to a string formed by concatenating the version number, build type
672 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100673
674- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
675 the CPU after warm boot. This is applicable for platforms which do not
676 require interconnect programming to enable cache coherency (eg: single
677 cluster platforms). If this option is enabled, then warm boot path
678 enables D-caches immediately after enabling MMU. This option defaults to 0.
679
Dan Handley610e7e12018-03-01 18:44:00 +0000680Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100681^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
682
683- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
684 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
685 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
686 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
687 flag.
688
689- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
690 of the memory reserved for each image. This affects the maximum size of each
691 BL image as well as the number of allocated memory regions and translation
692 tables. By default this flag is 0, which means it uses the default
Dan Handley610e7e12018-03-01 18:44:00 +0000693 unoptimised values for these macros. Arm development platforms that wish to
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100694 optimise memory usage need to set this flag to 1 and must override the
695 related macros.
696
697- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
698 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
699 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
700 match the frame used by the Non-Secure image (normally the Linux kernel).
701 Default is true (access to the frame is allowed).
702
703- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000704 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100705 an error is encountered during the boot process (for example, when an image
706 could not be loaded or authenticated). The watchdog is enabled in the early
707 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
708 Trusted Watchdog may be disabled at build time for testing or development
709 purposes.
710
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100711- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
712 have specific values at boot. This boolean option allows the Trusted Firmware
713 to have a Linux kernel image as BL33 by preparing the registers to these
714 values before jumping to BL33. This option defaults to 0 (disabled). For now,
715 it only supports AArch64 kernels. ``RESET_TO_BL31`` must be 1 when using it.
716 If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set to the
717 location of a device tree blob (DTB) already loaded in memory. The Linux
718 Image address must be specified using the ``PRELOADED_BL33_BASE`` option.
719
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100720- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
721 for the construction of composite state-ID in the power-state parameter.
722 The existing PSCI clients currently do not support this encoding of
723 State-ID yet. Hence this flag is used to configure whether to use the
724 recommended State-ID encoding or not. The default value of this flag is 0,
725 in which case the platform is configured to expect NULL in the State-ID
726 field of power-state parameter.
727
728- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
729 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000730 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100731 must be specified using the ``ROT_KEY`` option when building the Trusted
732 Firmware. This private key will be used by the certificate generation tool
733 to sign the BL2 and Trusted Key certificates. Available options for
734 ``ARM_ROTPK_LOCATION`` are:
735
736 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
737 registers. The private key corresponding to this ROTPK hash is not
738 currently available.
739 - ``devel_rsa`` : return a development public key hash embedded in the BL1
740 and BL2 binaries. This hash has been obtained from the RSA public key
741 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
742 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
743 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800744 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
745 and BL2 binaries. This hash has been obtained from the ECDSA public key
746 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
747 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
748 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100749
750- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
751
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800752 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100753 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100754 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
755 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100756
Dan Handley610e7e12018-03-01 18:44:00 +0000757- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
758 of the translation tables library instead of version 2. It is set to 0 by
759 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100760
Dan Handley610e7e12018-03-01 18:44:00 +0000761- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
762 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
763 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100764 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
765
Dan Handley610e7e12018-03-01 18:44:00 +0000766For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100767map is explained in the `Firmware Design`_.
768
Dan Handley610e7e12018-03-01 18:44:00 +0000769Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100770^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
771
772- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
773 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
774 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000775 TF-A no longer supports earlier SCP versions. If this option is set to 1
776 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100777
778- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
779 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
780 during boot. Default is 1.
781
Soby Mathew1ced6b82017-06-12 12:37:10 +0100782- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
783 instead of SCPI/BOM driver for communicating with the SCP during power
784 management operations and for SCP RAM Firmware transfer. If this option
785 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100786
Dan Handley610e7e12018-03-01 18:44:00 +0000787Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100788^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
789
790- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000791 build the topology tree within TF-A. By default TF-A is configured for dual
792 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100793
794- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
795 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
796 explained in the options below:
797
798 - ``FVP_CCI`` : The CCI driver is selected. This is the default
799 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
800 - ``FVP_CCN`` : The CCN driver is selected. This is the default
801 if ``FVP_CLUSTER_COUNT`` > 2.
802
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000803- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
804 a single cluster. This option defaults to 4.
805
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000806- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
807 in the system. This option defaults to 1. Note that the build option
808 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
809
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100810- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
811
812 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
813 - ``FVP_GICV2`` : The GICv2 only driver is selected
814 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
815 - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
Dan Handley610e7e12018-03-01 18:44:00 +0000816 Note: If TF-A is compiled with this option on FVPs with GICv3 hardware,
817 then it configures the hardware to run in GICv2 emulation mode
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100818
819- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
820 for functions that wait for an arbitrary time length (udelay and mdelay).
821 The default value is 0.
822
Soby Mathewb1bf0442018-02-16 14:52:52 +0000823- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
824 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
825 details on HW_CONFIG. By default, this is initialized to a sensible DTS
826 file in ``fdts/`` folder depending on other build options. But some cases,
827 like shifted affinity format for MPIDR, cannot be detected at build time
828 and this option is needed to specify the appropriate DTS file.
829
830- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
831 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
832 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
833 HW_CONFIG blob instead of the DTS file. This option is useful to override
834 the default HW_CONFIG selected by the build system.
835
Summer Qin13b95c22018-03-02 15:51:14 +0800836ARM JUNO platform specific build options
837^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
838
839- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
840 Media Protection (TZ-MP1). Default value of this flag is 0.
841
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100842Debugging options
843~~~~~~~~~~~~~~~~~
844
845To compile a debug version and make the build more verbose use
846
847::
848
849 make PLAT=<platform> DEBUG=1 V=1 all
850
851AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
852example DS-5) might not support this and may need an older version of DWARF
853symbols to be emitted by GCC. This can be achieved by using the
854``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
855version to 2 is recommended for DS-5 versions older than 5.16.
856
857When debugging logic problems it might also be useful to disable all compiler
858optimizations by using ``-O0``.
859
860NOTE: Using ``-O0`` could cause output images to be larger and base addresses
Dan Handley610e7e12018-03-01 18:44:00 +0000861might need to be recalculated (see the **Memory layout on Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100862platforms** section in the `Firmware Design`_).
863
864Extra debug options can be passed to the build system by setting ``CFLAGS`` or
865``LDFLAGS``:
866
867.. code:: makefile
868
869 CFLAGS='-O0 -gdwarf-2' \
870 make PLAT=<platform> DEBUG=1 V=1 all
871
872Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
873ignored as the linker is called directly.
874
875It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000876post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
877``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100878section. In this case, the developer may take control of the target using a
879debugger when indicated by the console output. When using DS-5, the following
880commands can be used:
881
882::
883
884 # Stop target execution
885 interrupt
886
887 #
888 # Prepare your debugging environment, e.g. set breakpoints
889 #
890
891 # Jump over the debug loop
892 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
893
894 # Resume execution
895 continue
896
897Building the Test Secure Payload
898~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
899
900The TSP is coupled with a companion runtime service in the BL31 firmware,
901called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
902must be recompiled as well. For more information on SPs and SPDs, see the
903`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
904
Dan Handley610e7e12018-03-01 18:44:00 +0000905First clean the TF-A build directory to get rid of any previous BL31 binary.
906Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100907
908::
909
910 make PLAT=<platform> SPD=tspd all
911
912An additional boot loader binary file is created in the ``build`` directory:
913
914::
915
916 build/<platform>/<build-type>/bl32.bin
917
918Checking source code style
919~~~~~~~~~~~~~~~~~~~~~~~~~~
920
921When making changes to the source for submission to the project, the source
922must be in compliance with the Linux style guide, and to assist with this check
923the project Makefile contains two targets, which both utilise the
924``checkpatch.pl`` script that ships with the Linux source tree.
925
Joel Huttonfe027712018-03-19 11:59:57 +0000926To check the entire source tree, you must first download copies of
927``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
928in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH``
929environment variable to point to ``checkpatch.pl`` (with the other 2 files in
John Tsichritzisee10e792018-06-06 09:38:10 +0100930the same directory) and build the target checkcodebase:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100931
932::
933
934 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
935
936To just check the style on the files that differ between your local branch and
937the remote master, use:
938
939::
940
941 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
942
943If you wish to check your patch against something other than the remote master,
944set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
945is set to ``origin/master``.
946
947Building and using the FIP tool
948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
949
Dan Handley610e7e12018-03-01 18:44:00 +0000950Firmware Image Package (FIP) is a packaging format used by TF-A to package
951firmware images in a single binary. The number and type of images that should
952be packed in a FIP is platform specific and may include TF-A images and other
953firmware images required by the platform. For example, most platforms require
954a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
955U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100956
Dan Handley610e7e12018-03-01 18:44:00 +0000957The TF-A build system provides the make target ``fip`` to create a FIP file
958for the specified platform using the FIP creation tool included in the TF-A
959project. Examples below show how to build a FIP file for FVP, packaging TF-A
960and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100961
962For AArch64:
963
964::
965
966 make PLAT=fvp BL33=<path/to/bl33.bin> fip
967
968For AArch32:
969
970::
971
972 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
973
974Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
975UEFI, on FVP is not available upstream. Hence custom solutions are required to
976allow Linux boot on FVP. These instructions assume such a custom boot loader
977(BL33) is available.
978
979The resulting FIP may be found in:
980
981::
982
983 build/fvp/<build-type>/fip.bin
984
985For advanced operations on FIP files, it is also possible to independently build
986the tool and create or modify FIPs using this tool. To do this, follow these
987steps:
988
989It is recommended to remove old artifacts before building the tool:
990
991::
992
993 make -C tools/fiptool clean
994
995Build the tool:
996
997::
998
999 make [DEBUG=1] [V=1] fiptool
1000
1001The tool binary can be located in:
1002
1003::
1004
1005 ./tools/fiptool/fiptool
1006
1007Invoking the tool with ``--help`` will print a help message with all available
1008options.
1009
1010Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1011
1012::
1013
1014 ./tools/fiptool/fiptool create \
1015 --tb-fw build/<platform>/<build-type>/bl2.bin \
1016 --soc-fw build/<platform>/<build-type>/bl31.bin \
1017 fip.bin
1018
1019Example 2: view the contents of an existing Firmware package:
1020
1021::
1022
1023 ./tools/fiptool/fiptool info <path-to>/fip.bin
1024
1025Example 3: update the entries of an existing Firmware package:
1026
1027::
1028
1029 # Change the BL2 from Debug to Release version
1030 ./tools/fiptool/fiptool update \
1031 --tb-fw build/<platform>/release/bl2.bin \
1032 build/<platform>/debug/fip.bin
1033
1034Example 4: unpack all entries from an existing Firmware package:
1035
1036::
1037
1038 # Images will be unpacked to the working directory
1039 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1040
1041Example 5: remove an entry from an existing Firmware package:
1042
1043::
1044
1045 ./tools/fiptool/fiptool remove \
1046 --tb-fw build/<platform>/debug/fip.bin
1047
1048Note that if the destination FIP file exists, the create, update and
1049remove operations will automatically overwrite it.
1050
1051The unpack operation will fail if the images already exist at the
1052destination. In that case, use -f or --force to continue.
1053
1054More information about FIP can be found in the `Firmware Design`_ document.
1055
1056Migrating from fip\_create to fiptool
1057^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1058
1059The previous version of fiptool was called fip\_create. A compatibility script
1060that emulates the basic functionality of the previous fip\_create is provided.
1061However, users are strongly encouraged to migrate to fiptool.
1062
1063- To create a new FIP file, replace "fip\_create" with "fiptool create".
1064- To update a FIP file, replace "fip\_create" with "fiptool update".
1065- To dump the contents of a FIP file, replace "fip\_create --dump"
1066 with "fiptool info".
1067
1068Building FIP images with support for Trusted Board Boot
1069~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1070
1071Trusted Board Boot primarily consists of the following two features:
1072
1073- Image Authentication, described in `Trusted Board Boot`_, and
1074- Firmware Update, described in `Firmware Update`_
1075
1076The following steps should be followed to build FIP and (optionally) FWU\_FIP
1077images with support for these features:
1078
1079#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1080 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001081 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001082 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001083 information. The latest version of TF-A is tested with tag
Jeenu Viswambharanec06c3b2018-06-07 15:14:42 +01001084 ``mbedtls-2.10.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001085
1086 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1087 source files the modules depend upon.
1088 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1089 options required to build the mbed TLS sources.
1090
1091 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001092 license. Using mbed TLS source code will affect the licensing of TF-A
1093 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001094
1095#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001096 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001097
1098 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1099 - ``TRUSTED_BOARD_BOOT=1``
1100 - ``GENERATE_COT=1``
1101
Dan Handley610e7e12018-03-01 18:44:00 +00001102 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001103 specified at build time. Two locations are currently supported (see
1104 ``ARM_ROTPK_LOCATION`` build option):
1105
1106 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1107 root-key storage registers present in the platform. On Juno, this
1108 registers are read-only. On FVP Base and Cortex models, the registers
1109 are read-only, but the value can be specified using the command line
1110 option ``bp.trusted_key_storage.public_key`` when launching the model.
1111 On both Juno and FVP models, the default value corresponds to an
1112 ECDSA-SECP256R1 public key hash, whose private part is not currently
1113 available.
1114
1115 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001116 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001117 found in ``plat/arm/board/common/rotpk``.
1118
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001119 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001120 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001121 found in ``plat/arm/board/common/rotpk``.
1122
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001123 Example of command line using RSA development keys:
1124
1125 ::
1126
1127 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1128 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1129 ARM_ROTPK_LOCATION=devel_rsa \
1130 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1131 BL33=<path-to>/<bl33_image> \
1132 all fip
1133
1134 The result of this build will be the bl1.bin and the fip.bin binaries. This
1135 FIP will include the certificates corresponding to the Chain of Trust
1136 described in the TBBR-client document. These certificates can also be found
1137 in the output build directory.
1138
1139#. The optional FWU\_FIP contains any additional images to be loaded from
1140 Non-Volatile storage during the `Firmware Update`_ process. To build the
1141 FWU\_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001142 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001143
1144 - NS\_BL2U. The AP non-secure Firmware Updater image.
1145 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1146
1147 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1148 targets using RSA development:
1149
1150 ::
1151
1152 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1153 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1154 ARM_ROTPK_LOCATION=devel_rsa \
1155 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1156 BL33=<path-to>/<bl33_image> \
1157 SCP_BL2=<path-to>/<scp_bl2_image> \
1158 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1159 NS_BL2U=<path-to>/<ns_bl2u_image> \
1160 all fip fwu_fip
1161
1162 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1163 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1164 to the command line above.
1165
1166 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1167 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1168
1169 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1170 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1171 Chain of Trust described in the TBBR-client document. These certificates
1172 can also be found in the output build directory.
1173
1174Building the Certificate Generation Tool
1175~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1176
Dan Handley610e7e12018-03-01 18:44:00 +00001177The ``cert_create`` tool is built as part of the TF-A build process when the
1178``fip`` make target is specified and TBB is enabled (as described in the
1179previous section), but it can also be built separately with the following
1180command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001181
1182::
1183
1184 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1185
1186For platforms that do not require their own IDs in certificate files,
1187the generic 'cert\_create' tool can be built with the following command:
1188
1189::
1190
1191 make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
1192
1193``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1194verbose. The following command should be used to obtain help about the tool:
1195
1196::
1197
1198 ./tools/cert_create/cert_create -h
1199
1200Building a FIP for Juno and FVP
1201-------------------------------
1202
1203This section provides Juno and FVP specific instructions to build Trusted
1204Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001205a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001206
David Cunadob2de0992017-06-29 12:01:33 +01001207Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1208onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001209
Joel Huttonfe027712018-03-19 11:59:57 +00001210Note: Follow the full instructions for one platform before switching to a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001211different one. Mixing instructions for different platforms may result in
1212corrupted binaries.
1213
Joel Huttonfe027712018-03-19 11:59:57 +00001214Note: The uboot image downloaded by the Linaro workspace script does not always
1215match the uboot image packaged as BL33 in the corresponding fip file. It is
1216recommended to use the version that is packaged in the fip file using the
1217instructions below.
1218
Soby Mathewecd94ad2018-05-09 13:59:29 +01001219Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
1220by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1221section for more info on selecting the right FDT to use.
1222
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001223#. Clean the working directory
1224
1225 ::
1226
1227 make realclean
1228
1229#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1230
1231 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1232 package included in the Linaro release:
1233
1234 ::
1235
1236 # Build the fiptool
1237 make [DEBUG=1] [V=1] fiptool
1238
1239 # Unpack firmware images from Linaro FIP
1240 ./tools/fiptool/fiptool unpack \
1241 <path/to/linaro/release>/fip.bin
1242
1243 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001244 current working directory. The SCP\_BL2 image corresponds to
1245 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001246
Joel Huttonfe027712018-03-19 11:59:57 +00001247 Note: The fiptool will complain if the images to be unpacked already
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001248 exist in the current directory. If that is the case, either delete those
1249 files or use the ``--force`` option to overwrite.
1250
Joel Huttonfe027712018-03-19 11:59:57 +00001251 Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001252 Normal world boot loader that supports AArch32.
1253
Dan Handley610e7e12018-03-01 18:44:00 +00001254#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001255
1256 ::
1257
1258 # AArch64
1259 make PLAT=fvp BL33=nt-fw.bin all fip
1260
1261 # AArch32
1262 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1263
Dan Handley610e7e12018-03-01 18:44:00 +00001264#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001265
1266 For AArch64:
1267
1268 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1269 as a build parameter.
1270
1271 ::
1272
1273 make PLAT=juno all fip \
1274 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1275 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1276
1277 For AArch32:
1278
1279 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1280 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1281 separately for AArch32.
1282
1283 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1284 to the AArch32 Linaro cross compiler.
1285
1286 ::
1287
1288 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1289
1290 - Build BL32 in AArch32.
1291
1292 ::
1293
1294 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1295 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1296
1297 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1298 must point to the AArch64 Linaro cross compiler.
1299
1300 ::
1301
1302 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1303
1304 - The following parameters should be used to build BL1 and BL2 in AArch64
1305 and point to the BL32 file.
1306
1307 ::
1308
1309 make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
1310 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001311 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001312 BL32=<path-to-bl32>/bl32.bin all fip
1313
1314The resulting BL1 and FIP images may be found in:
1315
1316::
1317
1318 # Juno
1319 ./build/juno/release/bl1.bin
1320 ./build/juno/release/fip.bin
1321
1322 # FVP
1323 ./build/fvp/release/bl1.bin
1324 ./build/fvp/release/fip.bin
1325
Roberto Vargas096f3a02017-10-17 10:19:00 +01001326
1327Booting Firmware Update images
1328-------------------------------------
1329
1330When Firmware Update (FWU) is enabled there are at least 2 new images
1331that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1332FWU FIP.
1333
1334Juno
1335~~~~
1336
1337The new images must be programmed in flash memory by adding
1338an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1339on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1340Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1341programming" for more information. User should ensure these do not
1342overlap with any other entries in the file.
1343
1344::
1345
1346 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1347 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1348 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1349 NOR10LOAD: 00000000 ;Image Load Address
1350 NOR10ENTRY: 00000000 ;Image Entry Point
1351
1352 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1353 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1354 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1355 NOR11LOAD: 00000000 ;Image Load Address
1356
1357The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1358In the same way, the address ns_bl2u_base_address is the value of
1359NS_BL2U_BASE - 0x8000000.
1360
1361FVP
1362~~~
1363
1364The additional fip images must be loaded with:
1365
1366::
1367
1368 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1369 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1370
1371The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1372In the same way, the address ns_bl2u_base_address is the value of
1373NS_BL2U_BASE.
1374
1375
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001376EL3 payloads alternative boot flow
1377----------------------------------
1378
1379On a pre-production system, the ability to execute arbitrary, bare-metal code at
1380the highest exception level is required. It allows full, direct access to the
1381hardware, for example to run silicon soak tests.
1382
1383Although it is possible to implement some baremetal secure firmware from
1384scratch, this is a complex task on some platforms, depending on the level of
1385configuration required to put the system in the expected state.
1386
1387Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001388``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1389boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1390other BL images and passing control to BL31. It reduces the complexity of
1391developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001392
1393- putting the system into a known architectural state;
1394- taking care of platform secure world initialization;
1395- loading the SCP\_BL2 image if required by the platform.
1396
Dan Handley610e7e12018-03-01 18:44:00 +00001397When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001398TrustZone controller is simplified such that only region 0 is enabled and is
1399configured to permit secure access only. This gives full access to the whole
1400DRAM to the EL3 payload.
1401
1402The system is left in the same state as when entering BL31 in the default boot
1403flow. In particular:
1404
1405- Running in EL3;
1406- Current state is AArch64;
1407- Little-endian data access;
1408- All exceptions disabled;
1409- MMU disabled;
1410- Caches disabled.
1411
1412Booting an EL3 payload
1413~~~~~~~~~~~~~~~~~~~~~~
1414
1415The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001416not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001417
1418- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1419 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001420 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001421
1422- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1423 run-time.
1424
1425To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1426used. The infinite loop that it introduces in BL1 stops execution at the right
1427moment for a debugger to take control of the target and load the payload (for
1428example, over JTAG).
1429
1430It is expected that this loading method will work in most cases, as a debugger
1431connection is usually available in a pre-production system. The user is free to
1432use any other platform-specific mechanism to load the EL3 payload, though.
1433
1434Booting an EL3 payload on FVP
1435^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1436
1437The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1438the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1439is undefined on the FVP platform and the FVP platform code doesn't clear it.
1440Therefore, one must modify the way the model is normally invoked in order to
1441clear the mailbox at start-up.
1442
1443One way to do that is to create an 8-byte file containing all zero bytes using
1444the following command:
1445
1446::
1447
1448 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1449
1450and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1451using the following model parameters:
1452
1453::
1454
1455 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1456 --data=mailbox.dat@0x04000000 [Foundation FVP]
1457
1458To provide the model with the EL3 payload image, the following methods may be
1459used:
1460
1461#. If the EL3 payload is able to execute in place, it may be programmed into
1462 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1463 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1464 used for the FIP):
1465
1466 ::
1467
1468 -C bp.flashloader1.fname="/path/to/el3-payload"
1469
1470 On Foundation FVP, there is no flash loader component and the EL3 payload
1471 may be programmed anywhere in flash using method 3 below.
1472
1473#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1474 command may be used to load the EL3 payload ELF image over JTAG:
1475
1476 ::
1477
1478 load /path/to/el3-payload.elf
1479
1480#. The EL3 payload may be pre-loaded in volatile memory using the following
1481 model parameters:
1482
1483 ::
1484
1485 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1486 --data="/path/to/el3-payload"@address [Foundation FVP]
1487
1488 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001489 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001490
1491Booting an EL3 payload on Juno
1492^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1493
1494If the EL3 payload is able to execute in place, it may be programmed in flash
1495memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1496on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1497Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1498programming" for more information.
1499
1500Alternatively, the same DS-5 command mentioned in the FVP section above can
1501be used to load the EL3 payload's ELF file over JTAG on Juno.
1502
1503Preloaded BL33 alternative boot flow
1504------------------------------------
1505
1506Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001507on TF-A to load it. This may simplify packaging of the normal world code and
1508improve performance in a development environment. When secure world cold boot
1509is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001510
1511For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001512used when compiling TF-A. For example, the following command will create a FIP
1513without a BL33 and prepare to jump to a BL33 image loaded at address
15140x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001515
1516::
1517
1518 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1519
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001520Boot of a preloaded kernel image on Base FVP
1521~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001522
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001523The following example uses a simplified boot flow by directly jumping from the
1524TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1525useful if both the kernel and the device tree blob (DTB) are already present in
1526memory (like in FVP).
1527
1528For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1529address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001530
1531::
1532
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001533 CROSS_COMPILE=aarch64-linux-gnu- \
1534 make PLAT=fvp DEBUG=1 \
1535 RESET_TO_BL31=1 \
1536 ARM_LINUX_KERNEL_AS_BL33=1 \
1537 PRELOADED_BL33_BASE=0x80080000 \
1538 ARM_PRELOADED_DTB_BASE=0x82000000 \
1539 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001540
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001541Now, it is needed to modify the DTB so that the kernel knows the address of the
1542ramdisk. The following script generates a patched DTB from the provided one,
1543assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1544script assumes that the user is using a ramdisk image prepared for U-Boot, like
1545the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1546offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001547
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001548.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001549
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001550 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001551
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001552 # Path to the input DTB
1553 KERNEL_DTB=<path-to>/<fdt>
1554 # Path to the output DTB
1555 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1556 # Base address of the ramdisk
1557 INITRD_BASE=0x84000000
1558 # Path to the ramdisk
1559 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001560
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001561 # Skip uboot header (64 bytes)
1562 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1563 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1564 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1565
1566 CHOSEN_NODE=$(echo \
1567 "/ { \
1568 chosen { \
1569 linux,initrd-start = <${INITRD_START}>; \
1570 linux,initrd-end = <${INITRD_END}>; \
1571 }; \
1572 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001573
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001574 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1575 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001576
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001577And the FVP binary can be run with the following command:
1578
1579::
1580
1581 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1582 -C pctl.startup=0.0.0.0 \
1583 -C bp.secure_memory=1 \
1584 -C cluster0.NUM_CORES=4 \
1585 -C cluster1.NUM_CORES=4 \
1586 -C cache_state_modelled=1 \
1587 -C cluster0.cpu0.RVBAR=0x04020000 \
1588 -C cluster0.cpu1.RVBAR=0x04020000 \
1589 -C cluster0.cpu2.RVBAR=0x04020000 \
1590 -C cluster0.cpu3.RVBAR=0x04020000 \
1591 -C cluster1.cpu0.RVBAR=0x04020000 \
1592 -C cluster1.cpu1.RVBAR=0x04020000 \
1593 -C cluster1.cpu2.RVBAR=0x04020000 \
1594 -C cluster1.cpu3.RVBAR=0x04020000 \
1595 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1596 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1597 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1598 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1599
1600Boot of a preloaded kernel image on Juno
1601~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001602
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001603The Trusted Firmware must be compiled in a similar way as for FVP explained
1604above. The process to load binaries to memory is the one explained in
1605`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001606
1607Running the software on FVP
1608---------------------------
1609
David Cunado7c032642018-03-12 18:47:05 +00001610The latest version of the AArch64 build of TF-A has been tested on the following
1611Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1612(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001613
David Cunado82509be2017-12-19 16:33:25 +00001614NOTE: Unless otherwise stated, the model version is Version 11.2 Build 11.2.33.
David Cunado124415e2017-06-27 17:31:12 +01001615
1616- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001617- ``FVP_Base_AEMv8A-AEMv8A`` (and also Version 9.0, Build 0.8.9005)
David Cunado124415e2017-06-27 17:31:12 +01001618- ``FVP_Base_Cortex-A35x4``
1619- ``FVP_Base_Cortex-A53x4``
1620- ``FVP_Base_Cortex-A57x4-A53x4``
1621- ``FVP_Base_Cortex-A57x4``
1622- ``FVP_Base_Cortex-A72x4-A53x4``
1623- ``FVP_Base_Cortex-A72x4``
1624- ``FVP_Base_Cortex-A73x4-A53x4``
1625- ``FVP_Base_Cortex-A73x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001626
David Cunado7c032642018-03-12 18:47:05 +00001627Additionally, the AArch64 build was tested on the following Arm FVPs with
1628shifted affinities, supporting threaded CPU cores (64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001629
David Cunado7c032642018-03-12 18:47:05 +00001630- ``FVP_Base_Cortex-A55x4-A75x4`` (Version 0.0, build 0.0.4395)
1631- ``FVP_Base_Cortex-A55x4`` (Version 0.0, build 0.0.4395)
1632- ``FVP_Base_Cortex-A75x4`` (Version 0.0, build 0.0.4395)
1633- ``FVP_Base_RevC-2xAEMv8A``
1634
1635The latest version of the AArch32 build of TF-A has been tested on the following
1636Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1637(64-bit host machine only).
1638
1639- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001640- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001641
David Cunado7c032642018-03-12 18:47:05 +00001642NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1643is not compatible with legacy GIC configurations. Therefore this FVP does not
1644support these legacy GIC configurations.
1645
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001646NOTE: The build numbers quoted above are those reported by launching the FVP
1647with the ``--version`` parameter.
1648
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001649NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1650file systems that can be downloaded separately. To run an FVP with a virtio
1651file system image an additional FVP configuration option
1652``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1653used.
1654
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001655NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1656The commands below would report an ``unhandled argument`` error in this case.
1657
1658NOTE: FVPs can be launched with ``--cadi-server`` option such that a
Dan Handley610e7e12018-03-01 18:44:00 +00001659CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001660execution.
1661
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001662NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001663the internal synchronisation timings changed compared to older versions of the
1664models. The models can be launched with ``-Q 100`` option if they are required
1665to match the run time characteristics of the older versions.
1666
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001667The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001668downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001669
David Cunado124415e2017-06-27 17:31:12 +01001670The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001671`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001672
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001673Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001674parameter options. A brief description of the important ones that affect TF-A
1675and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001676
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001677Obtaining the Flattened Device Trees
1678~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1679
1680Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001681FDT files are required. FDT source files for the Foundation and Base FVPs can
1682be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1683a subset of the Base FVP components. For example, the Foundation FVP lacks
1684CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001685
1686Note: It is not recommended to use the FDTs built along the kernel because not
1687all FDTs are available from there.
1688
Soby Mathewecd94ad2018-05-09 13:59:29 +01001689The dynamic configuration capability is enabled in the firmware for FVPs.
1690This means that the firmware can authenticate and load the FDT if present in
1691FIP. A default FDT is packaged into FIP during the build based on
1692the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1693or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1694`Arm FVP platform specific build options`_ section for detail on the options).
1695
1696- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001697
David Cunado7c032642018-03-12 18:47:05 +00001698 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1699 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001700
Soby Mathewecd94ad2018-05-09 13:59:29 +01001701- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001702
David Cunado7c032642018-03-12 18:47:05 +00001703 For use with models such as the Cortex-A32 Base FVPs without shifted
1704 affinities and running Linux in AArch32 state with Base memory map
1705 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001706
Soby Mathewecd94ad2018-05-09 13:59:29 +01001707- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001708
David Cunado7c032642018-03-12 18:47:05 +00001709 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1710 affinities and with Base memory map configuration and Linux GICv3 support.
1711
Soby Mathewecd94ad2018-05-09 13:59:29 +01001712- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001713
1714 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1715 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1716
Soby Mathewecd94ad2018-05-09 13:59:29 +01001717- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001718
1719 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1720 single cluster, single threaded CPUs, Base memory map configuration and Linux
1721 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001722
Soby Mathewecd94ad2018-05-09 13:59:29 +01001723- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001724
David Cunado7c032642018-03-12 18:47:05 +00001725 For use with models such as the Cortex-A32 Base FVPs without shifted
1726 affinities and running Linux in AArch32 state with Base memory map
1727 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001728
Soby Mathewecd94ad2018-05-09 13:59:29 +01001729- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001730
1731 For use with Foundation FVP with Base memory map configuration.
1732
Soby Mathewecd94ad2018-05-09 13:59:29 +01001733- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001734
1735 (Default) For use with Foundation FVP with Base memory map configuration
1736 and Linux GICv3 support.
1737
1738Running on the Foundation FVP with reset to BL1 entrypoint
1739~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1740
1741The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000017424 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001743
1744::
1745
1746 <path-to>/Foundation_Platform \
1747 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001748 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001749 --secure-memory \
1750 --visualization \
1751 --gicv3 \
1752 --data="<path-to>/<bl1-binary>"@0x0 \
1753 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001754 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001755 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001756
1757Notes:
1758
1759- BL1 is loaded at the start of the Trusted ROM.
1760- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001761- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1762 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001763- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1764 and enable the GICv3 device in the model. Note that without this option,
1765 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001766 is not supported by TF-A.
1767- In order for TF-A to run correctly on the Foundation FVP, the architecture
1768 versions must match. The Foundation FVP defaults to the highest v8.x
1769 version it supports but the default build for TF-A is for v8.0. To avoid
1770 issues either start the Foundation FVP to use v8.0 architecture using the
1771 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1772 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001773
1774Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1776
David Cunado7c032642018-03-12 18:47:05 +00001777The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001778with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001779
1780::
1781
David Cunado7c032642018-03-12 18:47:05 +00001782 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001783 -C pctl.startup=0.0.0.0 \
1784 -C bp.secure_memory=1 \
1785 -C bp.tzc_400.diagnostics=1 \
1786 -C cluster0.NUM_CORES=4 \
1787 -C cluster1.NUM_CORES=4 \
1788 -C cache_state_modelled=1 \
1789 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1790 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001791 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001792 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001793
1794Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1795~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1796
1797The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001798with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001799
1800::
1801
1802 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1803 -C pctl.startup=0.0.0.0 \
1804 -C bp.secure_memory=1 \
1805 -C bp.tzc_400.diagnostics=1 \
1806 -C cluster0.NUM_CORES=4 \
1807 -C cluster1.NUM_CORES=4 \
1808 -C cache_state_modelled=1 \
1809 -C cluster0.cpu0.CONFIG64=0 \
1810 -C cluster0.cpu1.CONFIG64=0 \
1811 -C cluster0.cpu2.CONFIG64=0 \
1812 -C cluster0.cpu3.CONFIG64=0 \
1813 -C cluster1.cpu0.CONFIG64=0 \
1814 -C cluster1.cpu1.CONFIG64=0 \
1815 -C cluster1.cpu2.CONFIG64=0 \
1816 -C cluster1.cpu3.CONFIG64=0 \
1817 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1818 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001819 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001820 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001821
1822Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1823~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1824
1825The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001826boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001827
1828::
1829
1830 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1831 -C pctl.startup=0.0.0.0 \
1832 -C bp.secure_memory=1 \
1833 -C bp.tzc_400.diagnostics=1 \
1834 -C cache_state_modelled=1 \
1835 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1836 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001837 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001838 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001839
1840Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1841~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1842
1843The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001844boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001845
1846::
1847
1848 <path-to>/FVP_Base_Cortex-A32x4 \
1849 -C pctl.startup=0.0.0.0 \
1850 -C bp.secure_memory=1 \
1851 -C bp.tzc_400.diagnostics=1 \
1852 -C cache_state_modelled=1 \
1853 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1854 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001855 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001856 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001857
1858Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1859~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1860
David Cunado7c032642018-03-12 18:47:05 +00001861The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001862with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001863
1864::
1865
David Cunado7c032642018-03-12 18:47:05 +00001866 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001867 -C pctl.startup=0.0.0.0 \
1868 -C bp.secure_memory=1 \
1869 -C bp.tzc_400.diagnostics=1 \
1870 -C cluster0.NUM_CORES=4 \
1871 -C cluster1.NUM_CORES=4 \
1872 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001873 -C cluster0.cpu0.RVBAR=0x04020000 \
1874 -C cluster0.cpu1.RVBAR=0x04020000 \
1875 -C cluster0.cpu2.RVBAR=0x04020000 \
1876 -C cluster0.cpu3.RVBAR=0x04020000 \
1877 -C cluster1.cpu0.RVBAR=0x04020000 \
1878 -C cluster1.cpu1.RVBAR=0x04020000 \
1879 -C cluster1.cpu2.RVBAR=0x04020000 \
1880 -C cluster1.cpu3.RVBAR=0x04020000 \
1881 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001882 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1883 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001884 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001885 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001886 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001887
1888Notes:
1889
1890- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1891 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1892 parameter is needed to load the individual bootloader images in memory.
1893 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01001894 Payload. For the same reason, the FDT needs to be compiled from the DT source
1895 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
1896 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001897
1898- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1899 X and Y are the cluster and CPU numbers respectively, is used to set the
1900 reset vector for each core.
1901
1902- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1903 changing the value of
1904 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1905 ``BL32_BASE``.
1906
1907Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1908~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1909
1910The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001911with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001912
1913::
1914
1915 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1916 -C pctl.startup=0.0.0.0 \
1917 -C bp.secure_memory=1 \
1918 -C bp.tzc_400.diagnostics=1 \
1919 -C cluster0.NUM_CORES=4 \
1920 -C cluster1.NUM_CORES=4 \
1921 -C cache_state_modelled=1 \
1922 -C cluster0.cpu0.CONFIG64=0 \
1923 -C cluster0.cpu1.CONFIG64=0 \
1924 -C cluster0.cpu2.CONFIG64=0 \
1925 -C cluster0.cpu3.CONFIG64=0 \
1926 -C cluster1.cpu0.CONFIG64=0 \
1927 -C cluster1.cpu1.CONFIG64=0 \
1928 -C cluster1.cpu2.CONFIG64=0 \
1929 -C cluster1.cpu3.CONFIG64=0 \
1930 -C cluster0.cpu0.RVBAR=0x04001000 \
1931 -C cluster0.cpu1.RVBAR=0x04001000 \
1932 -C cluster0.cpu2.RVBAR=0x04001000 \
1933 -C cluster0.cpu3.RVBAR=0x04001000 \
1934 -C cluster1.cpu0.RVBAR=0x04001000 \
1935 -C cluster1.cpu1.RVBAR=0x04001000 \
1936 -C cluster1.cpu2.RVBAR=0x04001000 \
1937 -C cluster1.cpu3.RVBAR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001938 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001939 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001940 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001941 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001942 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001943
1944Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1945It should match the address programmed into the RVBAR register as well.
1946
1947Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1949
1950The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001951boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001952
1953::
1954
1955 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1956 -C pctl.startup=0.0.0.0 \
1957 -C bp.secure_memory=1 \
1958 -C bp.tzc_400.diagnostics=1 \
1959 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001960 -C cluster0.cpu0.RVBARADDR=0x04020000 \
1961 -C cluster0.cpu1.RVBARADDR=0x04020000 \
1962 -C cluster0.cpu2.RVBARADDR=0x04020000 \
1963 -C cluster0.cpu3.RVBARADDR=0x04020000 \
1964 -C cluster1.cpu0.RVBARADDR=0x04020000 \
1965 -C cluster1.cpu1.RVBARADDR=0x04020000 \
1966 -C cluster1.cpu2.RVBARADDR=0x04020000 \
1967 -C cluster1.cpu3.RVBARADDR=0x04020000 \
1968 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001969 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001970 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001971 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001972 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001973 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001974
1975Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1976~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1977
1978The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001979boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001980
1981::
1982
1983 <path-to>/FVP_Base_Cortex-A32x4 \
1984 -C pctl.startup=0.0.0.0 \
1985 -C bp.secure_memory=1 \
1986 -C bp.tzc_400.diagnostics=1 \
1987 -C cache_state_modelled=1 \
1988 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1989 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1990 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1991 -C cluster0.cpu3.RVBARADDR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001992 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001993 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001994 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001995 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001996 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001997
1998Running the software on Juno
1999----------------------------
2000
Dan Handley610e7e12018-03-01 18:44:00 +00002001This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002002
2003To execute the software stack on Juno, the version of the Juno board recovery
2004image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2005earlier version installed or are unsure which version is installed, please
2006re-install the recovery image by following the
2007`Instructions for using Linaro's deliverables on Juno`_.
2008
Dan Handley610e7e12018-03-01 18:44:00 +00002009Preparing TF-A images
2010~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002011
Dan Handley610e7e12018-03-01 18:44:00 +00002012After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2013``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002014
2015Other Juno software information
2016~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2017
Dan Handley610e7e12018-03-01 18:44:00 +00002018Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002019software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002020get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002021configure it.
2022
2023Testing SYSTEM SUSPEND on Juno
2024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2025
2026The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2027to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2028on Juno, at the linux shell prompt, issue the following command:
2029
2030::
2031
2032 echo +10 > /sys/class/rtc/rtc0/wakealarm
2033 echo -n mem > /sys/power/state
2034
2035The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2036wakeup interrupt from RTC.
2037
2038--------------
2039
Dan Handley610e7e12018-03-01 18:44:00 +00002040*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002041
David Cunadob2de0992017-06-29 12:01:33 +01002042.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002043.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00002044.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
2045.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes#1710
2046.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
2047.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002048.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002049.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Joel Huttonfe027712018-03-19 11:59:57 +00002050.. _Linux master tree: <https://github.com/torvalds/linux/tree/master/>
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002051.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002052.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002053.. _Trusted Board Boot: trusted-board-boot.rst
Soby Mathewecd94ad2018-05-09 13:59:29 +01002054.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002055.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002056.. _Firmware Update: firmware-update.rst
2057.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002058.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2059.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002060.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002061.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002062.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002063.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf