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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley2b6b5742015-03-19 19:17:53 +00002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <arch_helpers.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000032#include <arm_config.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Juan Castillo4dc4a472014-08-12 11:17:06 +010034#include <debug.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000035#include <errno.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <mmio.h>
37#include <platform.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000038#include <plat_arm.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010039#include <psci.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000040#include <v2m_def.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010041#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010042#include "fvp_def.h"
43#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
Dan Handley2b6b5742015-03-19 19:17:53 +000045
Soby Mathew7799cf72015-04-16 14:49:09 +010046#if ARM_RECOM_STATE_ID_ENC
47/*
48 * The table storing the valid idle power states. Ensure that the
49 * array entries are populated in ascending order of state-id to
50 * enable us to use binary search during power state validation.
51 * The table must be terminated by a NULL entry.
52 */
53const unsigned int arm_pm_idle_states[] = {
54 /* State-id - 0x01 */
55 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
56 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
57 /* State-id - 0x02 */
58 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
59 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
60 /* State-id - 0x22 */
61 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
62 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
63 0,
64};
65#endif
66
Achin Gupta4f6ad662013-10-25 09:08:21 +010067/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010068 * Function which implements the common FVP specific operations to power down a
69 * cpu in response to a CPU_OFF or CPU_SUSPEND request.
70 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000071static void fvp_cpu_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010072{
Achin Gupta85876392014-07-31 17:45:51 +010073 /* Prevent interrupts from spuriously waking up this cpu */
Achin Gupta1fa7eb62015-11-03 14:18:34 +000074 plat_arm_gic_cpuif_disable();
Achin Gupta85876392014-07-31 17:45:51 +010075
76 /* Program the power controller to power off this cpu. */
77 fvp_pwrc_write_ppoffr(read_mpidr_el1());
78}
79
80/*******************************************************************************
81 * Function which implements the common FVP specific operations to power down a
82 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
83 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000084static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010085{
86 uint64_t mpidr = read_mpidr_el1();
87
88 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000089 fvp_cci_disable();
Achin Gupta85876392014-07-31 17:45:51 +010090
91 /* Program the power controller to turn the cluster off */
92 fvp_pwrc_write_pcoffr(mpidr);
93}
94
Soby Mathew12012dd2015-10-26 14:01:53 +000095static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
96{
97 unsigned long mpidr;
98
99 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
100 ARM_LOCAL_STATE_OFF);
101
102 /* Get the mpidr for this cpu */
103 mpidr = read_mpidr_el1();
104
105 /* Perform the common cluster specific operations */
106 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
107 ARM_LOCAL_STATE_OFF) {
108 /*
109 * This CPU might have woken up whilst the cluster was
110 * attempting to power down. In this case the FVP power
111 * controller will have a pending cluster power off request
112 * which needs to be cleared by writing to the PPONR register.
113 * This prevents the power controller from interpreting a
114 * subsequent entry of this cpu into a simple wfi as a power
115 * down request.
116 */
117 fvp_pwrc_write_pponr(mpidr);
118
119 /* Enable coherency if this cluster was off */
120 fvp_cci_enable();
121 }
122
123 /*
124 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
125 * with a cpu power down unless the bit is set again
126 */
127 fvp_pwrc_clr_wen(mpidr);
128}
129
130
Achin Gupta85876392014-07-31 17:45:51 +0100131/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100132 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000133 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100134void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000135{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100136
137 assert(cpu_state == ARM_LOCAL_STATE_RET);
138
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100139 /*
140 * Enter standby state
141 * dsb is good practice before using wfi to enter low power states
142 */
143 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000144 wfi();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000145}
146
147/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100148 * FVP handler called when a power domain is about to be turned on. The
149 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100151int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100152{
153 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154 unsigned int psysr;
155
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156 /*
Achin Gupta4f6ad662013-10-25 09:08:21 +0100157 * Ensure that we do not cancel an inflight power off request
158 * for the target cpu. That would leave it in a zombie wfi.
159 * Wait for it to power off, program the jump address for the
160 * target cpu and then program the power controller to turn
161 * that cpu on
162 */
163 do {
164 psysr = fvp_pwrc_read_psysr(mpidr);
165 } while (psysr & PSYSR_AFF_L0);
166
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168 return rc;
169}
170
171/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100172 * FVP handler called when a power domain is about to be turned off. The
173 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100175void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100177 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
178 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179
Achin Gupta85876392014-07-31 17:45:51 +0100180 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100181 * If execution reaches this stage then this power domain will be
182 * suspended. Perform at least the cpu specific actions followed
183 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100184 */
185 fvp_cpu_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100186
Soby Mathewfec4eb72015-07-01 16:16:20 +0100187 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
188 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100189 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191}
192
193/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100194 * FVP handler called when a power domain is about to be suspended. The
195 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100197void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100199 unsigned long mpidr;
200
Soby Mathewfec4eb72015-07-01 16:16:20 +0100201 /*
202 * FVP has retention only at cpu level. Just return
203 * as nothing is to be done for retention.
204 */
205 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
206 ARM_LOCAL_STATE_RET)
Soby Mathew74e52a72014-10-02 16:56:51 +0100207 return;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208
Soby Mathewfec4eb72015-07-01 16:16:20 +0100209 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
210 ARM_LOCAL_STATE_OFF);
211
Soby Mathewffb4ab12014-09-26 15:08:52 +0100212 /* Get the mpidr for this cpu */
213 mpidr = read_mpidr_el1();
214
Achin Gupta85876392014-07-31 17:45:51 +0100215 /* Program the power controller to enable wakeup interrupts. */
216 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217
Achin Gupta85876392014-07-31 17:45:51 +0100218 /* Perform the common cpu specific operations */
219 fvp_cpu_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220
Achin Gupta85876392014-07-31 17:45:51 +0100221 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100222 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
223 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100224 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225}
226
227/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100228 * FVP handler called when a power domain has just been powered on after
229 * being turned off earlier. The target_state encodes the low power state that
230 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100231 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100232void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233{
Soby Mathew12012dd2015-10-26 14:01:53 +0000234 fvp_power_domain_on_finish_common(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235
Achin Gupta85876392014-07-31 17:45:51 +0100236 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000237 plat_arm_gic_pcpu_init();
238
239 /* Program the gic per-cpu distributor or re-distributor interface */
240 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241}
242
243/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100244 * FVP handler called when a power domain has just been powered on after
245 * having been suspended earlier. The target_state encodes the low power state
246 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247 * TODO: At the moment we reuse the on finisher and reinitialize the secure
248 * context. Need to implement a separate suspend finisher.
249 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100250void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100252 /*
253 * Nothing to be done on waking up from retention from CPU level.
254 */
255 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
256 ARM_LOCAL_STATE_RET)
257 return;
258
Soby Mathew12012dd2015-10-26 14:01:53 +0000259 fvp_power_domain_on_finish_common(target_state);
260
261 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000262 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100263}
264
Juan Castillo4dc4a472014-08-12 11:17:06 +0100265/*******************************************************************************
266 * FVP handlers to shutdown/reboot the system
267 ******************************************************************************/
268static void __dead2 fvp_system_off(void)
269{
270 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000271 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
272 V2M_CFGCTRL_START |
273 V2M_CFGCTRL_RW |
274 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100275 wfi();
276 ERROR("FVP System Off: operation not handled.\n");
277 panic();
278}
279
280static void __dead2 fvp_system_reset(void)
281{
282 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000283 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
284 V2M_CFGCTRL_START |
285 V2M_CFGCTRL_RW |
286 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100287 wfi();
288 ERROR("FVP System Reset: operation not handled.\n");
289 panic();
290}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100291
292/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100293 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
294 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100296const plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100297 .cpu_standby = fvp_cpu_standby,
298 .pwr_domain_on = fvp_pwr_domain_on,
299 .pwr_domain_off = fvp_pwr_domain_off,
300 .pwr_domain_suspend = fvp_pwr_domain_suspend,
301 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
302 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100303 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100304 .system_reset = fvp_system_reset,
Soby Mathew0d9e8522015-07-15 13:36:24 +0100305 .validate_power_state = arm_validate_power_state,
306 .validate_ns_entrypoint = arm_validate_ns_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +0100307};