Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 31 | #include <bl_common.h> |
| 32 | #include <console.h> |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 33 | #include <platform_tsp.h> |
| 34 | #include "../fvp_def.h" |
| 35 | #include "../fvp_private.h" |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 36 | |
| 37 | /******************************************************************************* |
| 38 | * Declarations of linker defined symbols which will help us find the layout |
| 39 | * of trusted SRAM |
| 40 | ******************************************************************************/ |
| 41 | extern unsigned long __RO_START__; |
| 42 | extern unsigned long __RO_END__; |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 43 | extern unsigned long __BL32_END__; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 44 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 45 | #if USE_COHERENT_MEM |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 46 | extern unsigned long __COHERENT_RAM_START__; |
| 47 | extern unsigned long __COHERENT_RAM_END__; |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 48 | #endif |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 49 | |
| 50 | /* |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 51 | * The next 3 constants identify the extents of the code & RO data region and |
| 52 | * the limit of the BL3-2 image. These addresses are used by the MMU setup code |
| 53 | * and therefore they must be page-aligned. It is the responsibility of the |
| 54 | * linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__ |
| 55 | * linker symbols refer to page-aligned addresses. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 56 | */ |
| 57 | #define BL32_RO_BASE (unsigned long)(&__RO_START__) |
| 58 | #define BL32_RO_LIMIT (unsigned long)(&__RO_END__) |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 59 | #define BL32_END (unsigned long)(&__BL32_END__) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 60 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 61 | #if USE_COHERENT_MEM |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 62 | /* |
| 63 | * The next 2 constants identify the extents of the coherent memory region. |
| 64 | * These addresses are used by the MMU setup code and therefore they must be |
| 65 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 66 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to |
| 67 | * page-aligned addresses. |
| 68 | */ |
| 69 | #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 70 | #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 71 | #endif |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 72 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 73 | /******************************************************************************* |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 74 | * Initialize the UART |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 75 | ******************************************************************************/ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 76 | void tsp_early_platform_setup(void) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 77 | { |
Vikram Kanigiri | 3684abf | 2014-03-27 14:33:15 +0000 | [diff] [blame] | 78 | /* |
| 79 | * Initialize a different console than already in use to display |
| 80 | * messages from TSP |
| 81 | */ |
Soby Mathew | f797cea | 2014-08-21 15:20:27 +0100 | [diff] [blame] | 82 | console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); |
Achin Gupta | 7671789 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 83 | |
| 84 | /* Initialize the platform config for future decision making */ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 85 | fvp_config_setup(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | /******************************************************************************* |
Vikram Kanigiri | 3684abf | 2014-03-27 14:33:15 +0000 | [diff] [blame] | 89 | * Perform platform specific setup placeholder |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 90 | ******************************************************************************/ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 91 | void tsp_platform_setup(void) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 92 | { |
Dan Handley | fb42b12 | 2014-06-20 09:43:15 +0100 | [diff] [blame] | 93 | fvp_gic_init(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | /******************************************************************************* |
| 97 | * Perform the very early platform specific architectural setup here. At the |
| 98 | * moment this is only intializes the MMU |
| 99 | ******************************************************************************/ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 100 | void tsp_plat_arch_setup(void) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 101 | { |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 102 | fvp_configure_mmu_el1(BL32_RO_BASE, |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 103 | (BL32_END - BL32_RO_BASE), |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 104 | BL32_RO_BASE, |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 105 | BL32_RO_LIMIT |
| 106 | #if USE_COHERENT_MEM |
| 107 | , BL32_COHERENT_RAM_BASE, |
| 108 | BL32_COHERENT_RAM_LIMIT |
| 109 | #endif |
| 110 | ); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 111 | } |