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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
Maheedhar Bollapalliae8e0132024-07-24 09:54:15 +05303 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05304 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/debug.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <lib/mmio.h>
Michal Simek058251a2023-04-13 13:19:11 +020010#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <plat/common/platform.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053012
Akshay Belsare589ccce2023-05-08 19:00:53 +053013#include <plat_common.h>
14#include <plat_ipi.h>
15#include <plat_private.h>
16#include <pm_api_sys.h>
17#include <versal_def.h>
18
19uint32_t platform_id, platform_version;
Maheedhar Bollapalliae8e0132024-07-24 09:54:15 +053020uint32_t cpu_clock;
Akshay Belsare589ccce2023-05-08 19:00:53 +053021
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053022/*
23 * Table of regions to map using the MMU.
24 * This doesn't include TZRAM as the 'mem_layout' argument passed to
25 * configure_mmu_elx() will give the available subset of that,
26 */
27const mmap_region_t plat_versal_mmap[] = {
28 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
29 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Michal Simek467e16e2023-04-14 08:39:49 +020031 MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW |
Tejas Patel54d13192019-02-27 18:44:55 +053032 MT_SECURE),
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053033 { 0 }
34};
35
Prasad Kummari0b377142023-10-26 16:32:26 +053036const mmap_region_t *plat_get_mmap(void)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053037{
38 return plat_versal_mmap;
39}
40
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053041void versal_config_setup(void)
42{
Tejas Patel354fe572018-12-14 00:55:37 -080043 /* Configure IPI data for versal */
44 versal_ipi_config_table_init();
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053045}
46
Akshay Belsare589ccce2023-05-08 19:00:53 +053047void board_detection(void)
48{
49 uint32_t plat_info[2];
50
51 if (pm_get_chipid(plat_info) != PM_RET_SUCCESS) {
52 /* If the call is failed we cannot proceed with further
53 * setup. TF-A to panic in this situation.
54 */
55 NOTICE("Failed to read the chip information");
56 panic();
57 }
58
59 platform_id = FIELD_GET(PLATFORM_MASK, plat_info[1]);
60 platform_version = FIELD_GET(PLATFORM_VERSION_MASK, plat_info[1]);
Akshay Belsarefc74bf12024-09-13 15:56:00 +053061
62 if (platform_id == VERSAL_COSIM) {
63 platform_id = VERSAL_QEMU;
64 }
Akshay Belsare589ccce2023-05-08 19:00:53 +053065}
Prasad Kummarie7e8f862023-10-04 10:20:30 +053066
Maheedhar Bollapalliae8e0132024-07-24 09:54:15 +053067const char *board_name_decode(void)
68{
69 const char *platform;
70
71 switch (platform_id) {
72 case VERSAL_SPP:
73 platform = "IPP";
74 break;
75 case VERSAL_EMU:
76 platform = "EMU";
77 break;
78 case VERSAL_QEMU:
79 platform = "QEMU";
80 break;
81 case VERSAL_SILICON:
82 platform = "SILICON";
83 break;
84 default:
85 platform = "unknown";
86 }
87
88 return platform;
89}
90
Prasad Kummarie7e8f862023-10-04 10:20:30 +053091uint32_t get_uart_clk(void)
92{
Maheedhar Bollapalliae8e0132024-07-24 09:54:15 +053093 uint32_t uart_clock;
94
95 switch (platform_id) {
96 case VERSAL_SPP:
97 uart_clock = 25000000;
98 break;
99 case VERSAL_EMU:
100 uart_clock = 212000;
101 break;
102 case VERSAL_QEMU:
Maheedhar Bollapalliae8e0132024-07-24 09:54:15 +0530103 case VERSAL_SILICON:
104 uart_clock = 100000000;
105 break;
106 default:
107 panic();
108 }
109
110 return uart_clock;
Prasad Kummarie7e8f862023-10-04 10:20:30 +0530111}