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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Tejas Patel69409962018-12-14 00:55:29 -08002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Tejas Patel354fe572018-12-14 00:55:37 -08007#include <plat_ipi.h>
Tejas Patel0a2f9ad2018-12-14 00:55:30 -08008#include <versal_def.h>
Tejas Patel69409962018-12-14 00:55:29 -08009#include <plat_private.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/debug.h>
11#include <drivers/generic_delay_timer.h>
12#include <lib/mmio.h>
13#include <lib/xlat_tables/xlat_tables.h>
14#include <plat/common/platform.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053015
16/*
17 * Table of regions to map using the MMU.
18 * This doesn't include TZRAM as the 'mem_layout' argument passed to
19 * configure_mmu_elx() will give the available subset of that,
20 */
21const mmap_region_t plat_versal_mmap[] = {
22 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
23 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
24 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Tejas Patel54d13192019-02-27 18:44:55 +053025 MAP_REGION_FLAT(FPD_MAINCCI_BASE, FPD_MAINCCI_SIZE, MT_DEVICE | MT_RW |
26 MT_SECURE),
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053027 { 0 }
28};
29
30const mmap_region_t *plat_versal_get_mmap(void)
31{
32 return plat_versal_mmap;
33}
34
35static void versal_print_platform_name(void)
36{
37 NOTICE("ATF running on Xilinx %s\n", PLATFORM_NAME);
38}
39
40void versal_config_setup(void)
41{
42 uint32_t val;
43
Tejas Patel354fe572018-12-14 00:55:37 -080044 /* Configure IPI data for versal */
45 versal_ipi_config_table_init();
46
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053047 versal_print_platform_name();
48
49 mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL,
50 VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT |
51 (0x20 << VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT));
52
53 /* Global timer init - Program time stamp reference clk */
54 val = mmio_read_32(VERSAL_CRL_TIMESTAMP_REF_CTRL);
55 val |= VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
56 mmio_write_32(VERSAL_CRL_TIMESTAMP_REF_CTRL, val);
57
58 /* Clear reset of timestamp reg */
59 mmio_write_32(VERSAL_CRL_RST_TIMESTAMP_OFFSET, 0x0);
60
61 /* Program freq register in System counter and enable system counter. */
62 mmio_write_32(VERSAL_IOU_SCNTRS_BASE_FREQ, VERSAL_CPU_CLOCK);
63 mmio_write_32(VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG,
64 VERSAL_IOU_SCNTRS_CONTROL_EN);
65
66 generic_delay_timer_init();
67}
68
69unsigned int plat_get_syscnt_freq2(void)
70{
71 return VERSAL_CPU_CLOCK;
72}
73
74uintptr_t plat_get_ns_image_entrypoint(void)
75{
76#ifdef PRELOADED_BL33_BASE
77 return PRELOADED_BL33_BASE;
78#else
79 return PLAT_VERSAL_NS_IMAGE_OFFSET;
80#endif
81}