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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_H__
32#define __ARCH_H__
33
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35/*******************************************************************************
36 * MIDR bit definitions
37 ******************************************************************************/
Soby Mathewc704cbc2014-08-14 11:33:56 +010038#define MIDR_IMPL_MASK 0xff
39#define MIDR_IMPL_SHIFT 0x18
Soby Mathew802f8652014-08-14 16:19:29 +010040#define MIDR_VAR_SHIFT 20
Soby Mathewc0884332014-09-22 12:11:36 +010041#define MIDR_VAR_BITS 4
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000042#define MIDR_VAR_MASK 0xf
Soby Mathew802f8652014-08-14 16:19:29 +010043#define MIDR_REV_SHIFT 0
Soby Mathewc0884332014-09-22 12:11:36 +010044#define MIDR_REV_BITS 4
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000045#define MIDR_REV_MASK 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +010046#define MIDR_PN_MASK 0xfff
47#define MIDR_PN_SHIFT 0x4
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
49/*******************************************************************************
50 * MPIDR macros
51 ******************************************************************************/
52#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
53#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
54#define MPIDR_AFFINITY_BITS 8
55#define MPIDR_AFFLVL_MASK 0xff
56#define MPIDR_AFF0_SHIFT 0
57#define MPIDR_AFF1_SHIFT 8
58#define MPIDR_AFF2_SHIFT 16
59#define MPIDR_AFF3_SHIFT 32
60#define MPIDR_AFFINITY_MASK 0xff00ffffff
61#define MPIDR_AFFLVL_SHIFT 3
62#define MPIDR_AFFLVL0 0
63#define MPIDR_AFFLVL1 1
64#define MPIDR_AFFLVL2 2
65#define MPIDR_AFFLVL3 3
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000066#define MPIDR_AFFLVL0_VAL(mpidr) \
67 ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
68#define MPIDR_AFFLVL1_VAL(mpidr) \
69 ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
70#define MPIDR_AFFLVL2_VAL(mpidr) \
71 ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
72#define MPIDR_AFFLVL3_VAL(mpidr) \
73 ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000074/*
75 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
76 * add one while using this macro to define array sizes.
77 * TODO: Support only the first 3 affinity levels for now.
78 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010079#define MPIDR_MAX_AFFLVL 2
80
81/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
82#define FIRST_MPIDR 0
83
84/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010085 * Definitions for CPU system register interface to GICv3
86 ******************************************************************************/
87#define ICC_SRE_EL1 S3_0_C12_C12_5
88#define ICC_SRE_EL2 S3_4_C12_C9_5
89#define ICC_SRE_EL3 S3_6_C12_C12_5
90#define ICC_CTLR_EL1 S3_0_C12_C12_4
91#define ICC_CTLR_EL3 S3_6_C12_C12_4
92#define ICC_PMR_EL1 S3_0_C4_C6_0
Achin Gupta92712a52015-09-03 14:18:02 +010093#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
94#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
95#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
96#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
97#define ICC_IAR0_EL1 S3_0_c12_c8_0
98#define ICC_IAR1_EL1 S3_0_c12_c12_0
99#define ICC_EOIR0_EL1 S3_0_c12_c8_1
100#define ICC_EOIR1_EL1 S3_0_c12_c12_1
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100101
102/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000103 * Generic timer memory mapped registers & offsets
104 ******************************************************************************/
105#define CNTCR_OFF 0x000
106#define CNTFID_OFF 0x020
107
108#define CNTCR_EN (1 << 0)
109#define CNTCR_HDBG (1 << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100110#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000111
112/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113 * System register bit definitions
114 ******************************************************************************/
115/* CLIDR definitions */
116#define LOUIS_SHIFT 21
117#define LOC_SHIFT 24
118#define CLIDR_FIELD_WIDTH 3
119
120/* CSSELR definitions */
121#define LEVEL_SHIFT 1
122
123/* D$ set/way op type defines */
124#define DCISW 0x0
125#define DCCISW 0x1
126#define DCCSW 0x2
127
128/* ID_AA64PFR0_EL1 definitions */
129#define ID_AA64PFR0_EL0_SHIFT 0
130#define ID_AA64PFR0_EL1_SHIFT 4
131#define ID_AA64PFR0_EL2_SHIFT 8
132#define ID_AA64PFR0_EL3_SHIFT 12
133#define ID_AA64PFR0_ELX_MASK 0xf
134
Achin Gupta92712a52015-09-03 14:18:02 +0100135#define ID_AA64PFR0_GIC_SHIFT 24
136#define ID_AA64PFR0_GIC_WIDTH 4
137#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1)
138
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000139/* ID_AA64MMFR0_EL1 definitions */
140#define ID_AA64MMFR0_EL1_PARANGE_MASK 0xf
141
142#define PARANGE_0000 32
143#define PARANGE_0001 36
144#define PARANGE_0010 40
145#define PARANGE_0011 42
146#define PARANGE_0100 44
147#define PARANGE_0101 48
148
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149/* ID_PFR1_EL1 definitions */
150#define ID_PFR1_VIRTEXT_SHIFT 12
151#define ID_PFR1_VIRTEXT_MASK 0xf
152#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
153 & ID_PFR1_VIRTEXT_MASK)
154
155/* SCTLR definitions */
156#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
157 (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \
158 (1 << 4))
159
160#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
Vikram Kanigiri94efd1f2015-07-22 11:53:52 +0100161 (1 << 20) | (1 << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200162#define SCTLR_AARCH32_EL1_RES1 \
163 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
164 (1 << 3))
165
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166#define SCTLR_M_BIT (1 << 0)
167#define SCTLR_A_BIT (1 << 1)
168#define SCTLR_C_BIT (1 << 2)
169#define SCTLR_SA_BIT (1 << 3)
Soby Mathewa993c422016-09-29 14:15:57 +0100170#define SCTLR_CP15BEN_BIT (1 << 5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171#define SCTLR_I_BIT (1 << 12)
Soby Mathewa993c422016-09-29 14:15:57 +0100172#define SCTLR_NTWI_BIT (1 << 16)
173#define SCTLR_NTWE_BIT (1 << 18)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174#define SCTLR_WXN_BIT (1 << 19)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175#define SCTLR_EE_BIT (1 << 25)
176
Achin Gupta4f6ad662013-10-25 09:08:21 +0100177/* CPACR_El1 definitions */
178#define CPACR_EL1_FPEN(x) (x << 20)
179#define CPACR_EL1_FP_TRAP_EL0 0x1
180#define CPACR_EL1_FP_TRAP_ALL 0x2
181#define CPACR_EL1_FP_TRAP_NONE 0x3
182
183/* SCR definitions */
184#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
185#define SCR_TWE_BIT (1 << 13)
186#define SCR_TWI_BIT (1 << 12)
187#define SCR_ST_BIT (1 << 11)
188#define SCR_RW_BIT (1 << 10)
189#define SCR_SIF_BIT (1 << 9)
190#define SCR_HCE_BIT (1 << 8)
191#define SCR_SMD_BIT (1 << 7)
192#define SCR_EA_BIT (1 << 3)
193#define SCR_FIQ_BIT (1 << 2)
194#define SCR_IRQ_BIT (1 << 1)
195#define SCR_NS_BIT (1 << 0)
Achin Gupta27b895e2014-05-04 18:38:28 +0100196#define SCR_VALID_BIT_MASK 0x2f8f
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197
198/* HCR definitions */
199#define HCR_RW_BIT (1ull << 31)
200#define HCR_AMO_BIT (1 << 5)
201#define HCR_IMO_BIT (1 << 4)
202#define HCR_FMO_BIT (1 << 3)
203
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100204/* ISR definitions */
205#define ISR_A_SHIFT 8
206#define ISR_I_SHIFT 7
207#define ISR_F_SHIFT 6
208
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209/* CNTHCTL_EL2 definitions */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100210#define EVNTEN_BIT (1 << 2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211#define EL1PCEN_BIT (1 << 1)
212#define EL1PCTEN_BIT (1 << 0)
213
214/* CNTKCTL_EL1 definitions */
215#define EL0PTEN_BIT (1 << 9)
216#define EL0VTEN_BIT (1 << 8)
217#define EL0PCTEN_BIT (1 << 0)
218#define EL0VCTEN_BIT (1 << 1)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100219#define EVNTEN_BIT (1 << 2)
220#define EVNTDIR_BIT (1 << 3)
221#define EVNTI_SHIFT 4
222#define EVNTI_MASK 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100223
224/* CPTR_EL3 definitions */
Harry Liebel4f603682014-01-14 18:11:48 +0000225#define TCPAC_BIT (1 << 31)
226#define TTA_BIT (1 << 20)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100227#define TFP_BIT (1 << 10)
228
229/* CPSR/SPSR definitions */
230#define DAIF_FIQ_BIT (1 << 0)
231#define DAIF_IRQ_BIT (1 << 1)
232#define DAIF_ABT_BIT (1 << 2)
233#define DAIF_DBG_BIT (1 << 3)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100234#define SPSR_DAIF_SHIFT 6
235#define SPSR_DAIF_MASK 0xf
236
237#define SPSR_AIF_SHIFT 6
238#define SPSR_AIF_MASK 0x7
239
240#define SPSR_E_SHIFT 9
241#define SPSR_E_MASK 0x1
242#define SPSR_E_LITTLE 0x0
243#define SPSR_E_BIG 0x1
244
245#define SPSR_T_SHIFT 5
246#define SPSR_T_MASK 0x1
247#define SPSR_T_ARM 0x0
248#define SPSR_T_THUMB 0x1
249
250#define DISABLE_ALL_EXCEPTIONS \
251 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
252
Achin Gupta4f6ad662013-10-25 09:08:21 +0100253
254/*
255 * TCR defintions
256 */
257#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
Lin Ma741a3822014-06-27 16:56:30 -0700258#define TCR_EL1_IPS_SHIFT 32
259#define TCR_EL3_PS_SHIFT 16
260
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100261#define TCR_TxSZ_MIN 16
262#define TCR_TxSZ_MAX 39
263
Lin Ma741a3822014-06-27 16:56:30 -0700264/* (internal) physical address size bits in EL3/EL1 */
265#define TCR_PS_BITS_4GB (0x0)
266#define TCR_PS_BITS_64GB (0x1)
267#define TCR_PS_BITS_1TB (0x2)
268#define TCR_PS_BITS_4TB (0x3)
269#define TCR_PS_BITS_16TB (0x4)
270#define TCR_PS_BITS_256TB (0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100271
Lin Ma741a3822014-06-27 16:56:30 -0700272#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL
273#define ADDR_MASK_44_TO_47 0x0000F00000000000UL
274#define ADDR_MASK_42_TO_43 0x00000C0000000000UL
275#define ADDR_MASK_40_TO_41 0x0000030000000000UL
276#define ADDR_MASK_36_TO_39 0x000000F000000000UL
277#define ADDR_MASK_32_TO_35 0x0000000F00000000UL
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278
279#define TCR_RGN_INNER_NC (0x0 << 8)
280#define TCR_RGN_INNER_WBA (0x1 << 8)
281#define TCR_RGN_INNER_WT (0x2 << 8)
282#define TCR_RGN_INNER_WBNA (0x3 << 8)
283
284#define TCR_RGN_OUTER_NC (0x0 << 10)
285#define TCR_RGN_OUTER_WBA (0x1 << 10)
286#define TCR_RGN_OUTER_WT (0x2 << 10)
287#define TCR_RGN_OUTER_WBNA (0x3 << 10)
288
289#define TCR_SH_NON_SHAREABLE (0x0 << 12)
290#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)
291#define TCR_SH_INNER_SHAREABLE (0x3 << 12)
292
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100293#define MODE_SP_SHIFT 0x0
294#define MODE_SP_MASK 0x1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295#define MODE_SP_EL0 0x0
296#define MODE_SP_ELX 0x1
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100297
298#define MODE_RW_SHIFT 0x4
299#define MODE_RW_MASK 0x1
300#define MODE_RW_64 0x0
301#define MODE_RW_32 0x1
302
303#define MODE_EL_SHIFT 0x2
304#define MODE_EL_MASK 0x3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100305#define MODE_EL3 0x3
306#define MODE_EL2 0x2
307#define MODE_EL1 0x1
308#define MODE_EL0 0x0
309
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100310#define MODE32_SHIFT 0
311#define MODE32_MASK 0xf
312#define MODE32_usr 0x0
313#define MODE32_fiq 0x1
314#define MODE32_irq 0x2
315#define MODE32_svc 0x3
316#define MODE32_mon 0x6
317#define MODE32_abt 0x7
318#define MODE32_hyp 0xa
319#define MODE32_und 0xb
320#define MODE32_sys 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100321
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100322#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
323#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
324#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
325#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100326
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100327#define SPSR_64(el, sp, daif) \
328 (MODE_RW_64 << MODE_RW_SHIFT | \
329 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
330 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
331 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
332
333#define SPSR_MODE32(mode, isa, endian, aif) \
334 (MODE_RW_32 << MODE_RW_SHIFT | \
335 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
336 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
337 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
338 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100339
Dan Handley0cdebbd2015-03-30 17:15:16 +0100340/*
341 * CTR_EL0 definitions
342 */
343#define CTR_CWG_SHIFT 24
344#define CTR_CWG_MASK 0xf
345#define CTR_ERG_SHIFT 20
346#define CTR_ERG_MASK 0xf
347#define CTR_DMINLINE_SHIFT 16
348#define CTR_DMINLINE_MASK 0xf
349#define CTR_L1IP_SHIFT 14
350#define CTR_L1IP_MASK 0x3
351#define CTR_IMINLINE_SHIFT 0
352#define CTR_IMINLINE_MASK 0xf
353
354#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100355
Achin Gupta405406d2014-05-09 12:00:17 +0100356/* Physical timer control register bit fields shifts and masks */
357#define CNTP_CTL_ENABLE_SHIFT 0
358#define CNTP_CTL_IMASK_SHIFT 1
359#define CNTP_CTL_ISTATUS_SHIFT 2
360
361#define CNTP_CTL_ENABLE_MASK 1
362#define CNTP_CTL_IMASK_MASK 1
363#define CNTP_CTL_ISTATUS_MASK 1
364
365#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \
366 CNTP_CTL_ENABLE_MASK)
367#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \
368 CNTP_CTL_IMASK_MASK)
369#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \
370 CNTP_CTL_ISTATUS_MASK)
371
372#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT)
373#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT)
374
375#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
376#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
377
Achin Gupta4f6ad662013-10-25 09:08:21 +0100378/* Exception Syndrome register bits and bobs */
379#define ESR_EC_SHIFT 26
380#define ESR_EC_MASK 0x3f
381#define ESR_EC_LENGTH 6
382#define EC_UNKNOWN 0x0
383#define EC_WFE_WFI 0x1
384#define EC_AARCH32_CP15_MRC_MCR 0x3
385#define EC_AARCH32_CP15_MRRC_MCRR 0x4
386#define EC_AARCH32_CP14_MRC_MCR 0x5
387#define EC_AARCH32_CP14_LDC_STC 0x6
388#define EC_FP_SIMD 0x7
389#define EC_AARCH32_CP10_MRC 0x8
390#define EC_AARCH32_CP14_MRRC_MCRR 0xc
391#define EC_ILLEGAL 0xe
392#define EC_AARCH32_SVC 0x11
393#define EC_AARCH32_HVC 0x12
394#define EC_AARCH32_SMC 0x13
395#define EC_AARCH64_SVC 0x15
396#define EC_AARCH64_HVC 0x16
397#define EC_AARCH64_SMC 0x17
398#define EC_AARCH64_SYS 0x18
399#define EC_IABORT_LOWER_EL 0x20
400#define EC_IABORT_CUR_EL 0x21
401#define EC_PC_ALIGN 0x22
402#define EC_DABORT_LOWER_EL 0x24
403#define EC_DABORT_CUR_EL 0x25
404#define EC_SP_ALIGN 0x26
405#define EC_AARCH32_FP 0x28
406#define EC_AARCH64_FP 0x2c
407#define EC_SERROR 0x2f
408
409#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
410
Dan Handleyed6ff952014-05-14 17:44:19 +0100411/*******************************************************************************
412 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
413 * system level implementation of the Generic Timer.
414 ******************************************************************************/
415#define CNTNSAR 0x4
416#define CNTNSAR_NS_SHIFT(x) x
417
418#define CNTACR_BASE(x) (0x40 + (x << 2))
419#define CNTACR_RPCT_SHIFT 0x0
420#define CNTACR_RVCT_SHIFT 0x1
421#define CNTACR_RFRQ_SHIFT 0x2
422#define CNTACR_RVOFF_SHIFT 0x3
423#define CNTACR_RWVT_SHIFT 0x4
424#define CNTACR_RWPT_SHIFT 0x5
425
David Cunado5f55e282016-10-31 17:37:34 +0000426/* PMCR_EL0 definitions */
427#define PMCR_EL0_N_SHIFT 11
428#define PMCR_EL0_N_MASK 0x1f
429#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
430
Achin Gupta4f6ad662013-10-25 09:08:21 +0100431#endif /* __ARCH_H__ */