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Loh Tien Hock59400a42019-02-04 16:17:24 +08001/*
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +08002 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Loh Tien Hock59400a42019-02-04 16:17:24 +08004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <arch.h>
9#include <arch_helpers.h>
Siew Chin Lim380924d2021-06-12 13:25:05 +080010#include <assert.h>
Loh Tien Hock59400a42019-02-04 16:17:24 +080011#include <common/bl_common.h>
12#include <common/debug.h>
13#include <common/desc_image_load.h>
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080014#include <drivers/generic_delay_timer.h>
Loh Tien Hock59400a42019-02-04 16:17:24 +080015#include <drivers/synopsys/dw_mmc.h>
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080016#include <drivers/ti/uart/uart_16550.h>
Loh Tien Hock59400a42019-02-04 16:17:24 +080017#include <lib/xlat_tables/xlat_tables.h>
18
Hadi Asyrafic461add2019-06-12 11:24:12 +080019#include "qspi/cadence_qspi.h"
Tien Hock, Loh8d9e8912019-10-02 13:49:25 +080020#include "socfpga_emac.h"
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +080021#include "socfpga_f2sdram_manager.h"
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +080022#include "socfpga_handoff.h"
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080023#include "socfpga_mailbox.h"
Hadi Asyrafif0fa8072019-10-23 17:02:55 +080024#include "socfpga_private.h"
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +080025#include "socfpga_reset_manager.h"
Hadi Asyrafi8ebd2372019-12-23 17:58:04 +080026#include "socfpga_system_manager.h"
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080027#include "s10_clock_manager.h"
28#include "s10_memory_controller.h"
Sieu Mun Tange026eea2022-05-05 23:42:55 +080029#include "s10_mmc.h"
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080030#include "s10_pinmux.h"
Hadi Asyrafic461add2019-06-12 11:24:12 +080031#include "wdt/watchdog.h"
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +080032
Yann Gautiercf931582021-03-22 14:21:54 +010033static struct mmc_device_info mmc_info;
Loh Tien Hock59400a42019-02-04 16:17:24 +080034
35const mmap_region_t plat_stratix10_mmap[] = {
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080036 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
37 MT_MEMORY | MT_RW | MT_NS),
38 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
39 MT_DEVICE | MT_RW | MT_NS),
40 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
41 MT_DEVICE | MT_RW | MT_SECURE),
Loh Tien Hock59400a42019-02-04 16:17:24 +080042 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
43 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
44 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
45 MT_DEVICE | MT_RW | MT_SECURE),
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080046 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
47 MT_DEVICE | MT_RW | MT_NS),
48 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
49 MT_DEVICE | MT_RW | MT_NS),
Loh Tien Hock59400a42019-02-04 16:17:24 +080050 {0},
51};
52
Hadi Asyrafi786db4d2019-12-30 16:00:30 +080053boot_source_type boot_source = BOOT_SOURCE;
Loh Tien Hock59400a42019-02-04 16:17:24 +080054
55void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
56 u_register_t x2, u_register_t x4)
57{
Andre Przywara98b5a112020-01-25 00:58:35 +000058 static console_t console;
Loh Tien Hock59400a42019-02-04 16:17:24 +080059 handoff reverse_handoff_ptr;
60
61 generic_delay_timer_init();
62
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +080063 if (socfpga_get_handoff(&reverse_handoff_ptr))
Loh Tien Hock59400a42019-02-04 16:17:24 +080064 return;
65 config_pinmux(&reverse_handoff_ptr);
Loh Tien Hock59400a42019-02-04 16:17:24 +080066
67 config_clkmgr_handoff(&reverse_handoff_ptr);
68 enable_nonsecure_access();
69 deassert_peripheral_reset();
70 config_hps_hs_before_warm_reset();
71
Hadi Asyrafi78fee352019-07-30 22:18:17 +080072 watchdog_init(get_wdt_clk());
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +080073
Boon Khai Ngb19ac612021-08-06 01:16:46 +080074 console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(),
75 PLAT_BAUDRATE, &console);
Loh Tien Hock59400a42019-02-04 16:17:24 +080076
Tien Hock, Loh8d9e8912019-10-02 13:49:25 +080077 socfpga_emac_init();
Hadi Asyrafi309ac012019-08-01 14:48:39 +080078 socfpga_delay_timer_init();
Loh Tien Hock59400a42019-02-04 16:17:24 +080079 init_hard_memory_controller();
Hadi Asyrafie73c5112019-10-21 16:35:08 +080080 mailbox_init();
Sieu Mun Tange026eea2022-05-05 23:42:55 +080081 s10_mmc_init();
Hadi Asyrafi6aeb55d2019-12-24 14:43:22 +080082
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +080083 if (!intel_mailbox_is_fpga_not_ready()) {
84 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
Sieu Mun Tang044ed482022-05-11 10:45:19 +080085 FPGA2SOC_MASK | F2SDRAM0_MASK | F2SDRAM1_MASK |
86 F2SDRAM2_MASK);
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +080087 }
Loh Tien Hock59400a42019-02-04 16:17:24 +080088}
89
90
91void bl2_el3_plat_arch_setup(void)
92{
93
Loh Tien Hock59400a42019-02-04 16:17:24 +080094 const mmap_region_t bl_regions[] = {
95 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
96 MT_MEMORY | MT_RW | MT_SECURE),
97 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
98 MT_CODE | MT_SECURE),
99 MAP_REGION_FLAT(BL_RO_DATA_BASE,
100 BL_RO_DATA_END - BL_RO_DATA_BASE,
101 MT_RO_DATA | MT_SECURE),
102#if USE_COHERENT_MEM_BAR
103 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
104 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
105 MT_DEVICE | MT_RW | MT_SECURE),
106#endif
107 {0},
108 };
109
110 setup_page_tables(bl_regions, plat_stratix10_mmap);
111
112 enable_mmu_el3(0);
113
Hadi Asyrafi78fee352019-07-30 22:18:17 +0800114 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
Loh Tien Hock59400a42019-02-04 16:17:24 +0800115
Yann Gautiercf931582021-03-22 14:21:54 +0100116 mmc_info.mmc_dev_type = MMC_IS_SD;
117 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
Loh Tien Hock59400a42019-02-04 16:17:24 +0800118
Abdul Halim, Muhammad Hadi Asyrafiae4cd3a2020-10-06 20:09:53 +0800119 /* Request ownership and direct access to QSPI */
120 mailbox_hps_qspi_enable();
121
Loh Tien Hock59400a42019-02-04 16:17:24 +0800122 switch (boot_source) {
123 case BOOT_SOURCE_SDMMC:
Yann Gautiercf931582021-03-22 14:21:54 +0100124 dw_mmc_init(&params, &mmc_info);
Hadi Asyrafif0fa8072019-10-23 17:02:55 +0800125 socfpga_io_setup(boot_source);
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800126 break;
127
128 case BOOT_SOURCE_QSPI:
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800129 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
130 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
131 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
Hadi Asyrafif0fa8072019-10-23 17:02:55 +0800132 socfpga_io_setup(boot_source);
Loh Tien Hock59400a42019-02-04 16:17:24 +0800133 break;
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800134
Loh Tien Hock59400a42019-02-04 16:17:24 +0800135 default:
136 ERROR("Unsupported boot source\n");
137 panic();
138 break;
139 }
140}
141
142uint32_t get_spsr_for_bl33_entry(void)
143{
144 unsigned long el_status;
145 unsigned int mode;
146 uint32_t spsr;
147
148 /* Figure out what mode we enter the non-secure world in */
149 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
150 el_status &= ID_AA64PFR0_ELX_MASK;
151
152 mode = (el_status) ? MODE_EL2 : MODE_EL1;
153
154 /*
155 * TODO: Consider the possibility of specifying the SPSR in
156 * the FIP ToC and allowing the platform to have a say as
157 * well.
158 */
159 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
160 return spsr;
161}
162
163
164int bl2_plat_handle_post_image_load(unsigned int image_id)
165{
166 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
167
Siew Chin Lim380924d2021-06-12 13:25:05 +0800168 assert(bl_mem_params);
169
Loh Tien Hock59400a42019-02-04 16:17:24 +0800170 switch (image_id) {
171 case BL33_IMAGE_ID:
172 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
173 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
174 break;
175 default:
176 break;
177 }
178
179 return 0;
180}
181
182/*******************************************************************************
183 * Perform any BL3-1 platform setup code
184 ******************************************************************************/
185void bl2_platform_setup(void)
186{
187}
188