intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 8e8b582..f24bbde 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -73,9 +73,9 @@
deassert_peripheral_reset();
config_hps_hs_before_warm_reset();
- watchdog_init(get_wdt_clk(&reverse_handoff_ptr));
+ watchdog_init(get_wdt_clk());
- console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
+ console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
&console);
socfpga_delay_timer_init();
@@ -107,7 +107,7 @@
enable_mmu_el3(0);
- dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
+ dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
info.mmc_dev_type = MMC_IS_SD;
info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;