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Loh Tien Hock59400a42019-02-04 16:17:24 +08001/*
Yann Gautiercf931582021-03-22 14:21:54 +01002 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
Loh Tien Hock59400a42019-02-04 16:17:24 +08004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <arch.h>
9#include <arch_helpers.h>
Siew Chin Lim380924d2021-06-12 13:25:05 +080010#include <assert.h>
Loh Tien Hock59400a42019-02-04 16:17:24 +080011#include <common/bl_common.h>
12#include <common/debug.h>
13#include <common/desc_image_load.h>
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080014#include <drivers/generic_delay_timer.h>
Loh Tien Hock59400a42019-02-04 16:17:24 +080015#include <drivers/synopsys/dw_mmc.h>
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080016#include <drivers/ti/uart/uart_16550.h>
Loh Tien Hock59400a42019-02-04 16:17:24 +080017#include <lib/xlat_tables/xlat_tables.h>
18
Hadi Asyrafic461add2019-06-12 11:24:12 +080019#include "qspi/cadence_qspi.h"
Tien Hock, Loh8d9e8912019-10-02 13:49:25 +080020#include "socfpga_emac.h"
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +080021#include "socfpga_handoff.h"
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080022#include "socfpga_mailbox.h"
Hadi Asyrafif0fa8072019-10-23 17:02:55 +080023#include "socfpga_private.h"
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +080024#include "socfpga_reset_manager.h"
Hadi Asyrafi8ebd2372019-12-23 17:58:04 +080025#include "socfpga_system_manager.h"
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080026#include "s10_clock_manager.h"
27#include "s10_memory_controller.h"
28#include "s10_pinmux.h"
Hadi Asyrafic461add2019-06-12 11:24:12 +080029#include "wdt/watchdog.h"
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +080030
Yann Gautiercf931582021-03-22 14:21:54 +010031static struct mmc_device_info mmc_info;
Loh Tien Hock59400a42019-02-04 16:17:24 +080032
33const mmap_region_t plat_stratix10_mmap[] = {
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080034 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
35 MT_MEMORY | MT_RW | MT_NS),
36 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
37 MT_DEVICE | MT_RW | MT_NS),
38 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
39 MT_DEVICE | MT_RW | MT_SECURE),
Loh Tien Hock59400a42019-02-04 16:17:24 +080040 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
41 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
42 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
43 MT_DEVICE | MT_RW | MT_SECURE),
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080044 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
45 MT_DEVICE | MT_RW | MT_NS),
46 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
47 MT_DEVICE | MT_RW | MT_NS),
Loh Tien Hock59400a42019-02-04 16:17:24 +080048 {0},
49};
50
Hadi Asyrafi786db4d2019-12-30 16:00:30 +080051boot_source_type boot_source = BOOT_SOURCE;
Loh Tien Hock59400a42019-02-04 16:17:24 +080052
53void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
54 u_register_t x2, u_register_t x4)
55{
Andre Przywara98b5a112020-01-25 00:58:35 +000056 static console_t console;
Loh Tien Hock59400a42019-02-04 16:17:24 +080057 handoff reverse_handoff_ptr;
58
59 generic_delay_timer_init();
60
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +080061 if (socfpga_get_handoff(&reverse_handoff_ptr))
Loh Tien Hock59400a42019-02-04 16:17:24 +080062 return;
63 config_pinmux(&reverse_handoff_ptr);
Loh Tien Hock59400a42019-02-04 16:17:24 +080064
65 config_clkmgr_handoff(&reverse_handoff_ptr);
66 enable_nonsecure_access();
67 deassert_peripheral_reset();
68 config_hps_hs_before_warm_reset();
69
Hadi Asyrafi78fee352019-07-30 22:18:17 +080070 watchdog_init(get_wdt_clk());
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +080071
Boon Khai Ngb19ac612021-08-06 01:16:46 +080072 console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(),
73 PLAT_BAUDRATE, &console);
Loh Tien Hock59400a42019-02-04 16:17:24 +080074
Tien Hock, Loh8d9e8912019-10-02 13:49:25 +080075 socfpga_emac_init();
Hadi Asyrafi309ac012019-08-01 14:48:39 +080076 socfpga_delay_timer_init();
Loh Tien Hock59400a42019-02-04 16:17:24 +080077 init_hard_memory_controller();
Hadi Asyrafie73c5112019-10-21 16:35:08 +080078 mailbox_init();
Hadi Asyrafi6aeb55d2019-12-24 14:43:22 +080079
80 if (!intel_mailbox_is_fpga_not_ready())
81 socfpga_bridges_enable();
Loh Tien Hock59400a42019-02-04 16:17:24 +080082}
83
84
85void bl2_el3_plat_arch_setup(void)
86{
87
Loh Tien Hock59400a42019-02-04 16:17:24 +080088 const mmap_region_t bl_regions[] = {
89 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
90 MT_MEMORY | MT_RW | MT_SECURE),
91 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
92 MT_CODE | MT_SECURE),
93 MAP_REGION_FLAT(BL_RO_DATA_BASE,
94 BL_RO_DATA_END - BL_RO_DATA_BASE,
95 MT_RO_DATA | MT_SECURE),
96#if USE_COHERENT_MEM_BAR
97 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
98 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
99 MT_DEVICE | MT_RW | MT_SECURE),
100#endif
101 {0},
102 };
103
104 setup_page_tables(bl_regions, plat_stratix10_mmap);
105
106 enable_mmu_el3(0);
107
Hadi Asyrafi78fee352019-07-30 22:18:17 +0800108 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
Loh Tien Hock59400a42019-02-04 16:17:24 +0800109
Yann Gautiercf931582021-03-22 14:21:54 +0100110 mmc_info.mmc_dev_type = MMC_IS_SD;
111 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
Loh Tien Hock59400a42019-02-04 16:17:24 +0800112
Abdul Halim, Muhammad Hadi Asyrafiae4cd3a2020-10-06 20:09:53 +0800113 /* Request ownership and direct access to QSPI */
114 mailbox_hps_qspi_enable();
115
Loh Tien Hock59400a42019-02-04 16:17:24 +0800116 switch (boot_source) {
117 case BOOT_SOURCE_SDMMC:
Yann Gautiercf931582021-03-22 14:21:54 +0100118 dw_mmc_init(&params, &mmc_info);
Hadi Asyrafif0fa8072019-10-23 17:02:55 +0800119 socfpga_io_setup(boot_source);
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800120 break;
121
122 case BOOT_SOURCE_QSPI:
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800123 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
124 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
125 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
Hadi Asyrafif0fa8072019-10-23 17:02:55 +0800126 socfpga_io_setup(boot_source);
Loh Tien Hock59400a42019-02-04 16:17:24 +0800127 break;
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800128
Loh Tien Hock59400a42019-02-04 16:17:24 +0800129 default:
130 ERROR("Unsupported boot source\n");
131 panic();
132 break;
133 }
134}
135
136uint32_t get_spsr_for_bl33_entry(void)
137{
138 unsigned long el_status;
139 unsigned int mode;
140 uint32_t spsr;
141
142 /* Figure out what mode we enter the non-secure world in */
143 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
144 el_status &= ID_AA64PFR0_ELX_MASK;
145
146 mode = (el_status) ? MODE_EL2 : MODE_EL1;
147
148 /*
149 * TODO: Consider the possibility of specifying the SPSR in
150 * the FIP ToC and allowing the platform to have a say as
151 * well.
152 */
153 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
154 return spsr;
155}
156
157
158int bl2_plat_handle_post_image_load(unsigned int image_id)
159{
160 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
161
Siew Chin Lim380924d2021-06-12 13:25:05 +0800162 assert(bl_mem_params);
163
Loh Tien Hock59400a42019-02-04 16:17:24 +0800164 switch (image_id) {
165 case BL33_IMAGE_ID:
166 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
167 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
168 break;
169 default:
170 break;
171 }
172
173 return 0;
174}
175
176/*******************************************************************************
177 * Perform any BL3-1 platform setup code
178 ******************************************************************************/
179void bl2_platform_setup(void)
180{
181}
182