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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekarb8776152016-03-03 13:52:52 -08002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05303 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Varun Wadekarcad7b082015-12-28 18:12:59 -080031#include <arch_helpers.h>
32#include <assert.h>
Varun Wadekar94701ff2016-05-23 11:47:34 -070033#include <bl31.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080034#include <bl_common.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053035#include <console.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080036#include <context.h>
37#include <context_mgmt.h>
Varun Wadekar4debe052016-05-18 13:39:16 -070038#include <cortex_a57.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080039#include <debug.h>
40#include <denver.h>
41#include <interrupt_mgmt.h>
Varun Wadekar47ddd002016-03-28 16:00:02 -070042#include <mce.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080043#include <platform.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053044#include <tegra_def.h>
Varun Wadekar5887c102016-07-19 11:29:40 -070045#include <tegra_platform.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080046#include <tegra_private.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053047#include <xlat_tables.h>
48
Varun Wadekar4debe052016-05-18 13:39:16 -070049DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
50extern uint64_t tegra_enable_l2_ecc_parity_prot;
51
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080052/*******************************************************************************
Varun Wadekar43dad672017-01-31 14:53:37 -080053 * Tegra186 CPU numbers in cluster #0
54 *******************************************************************************
55 */
56#define TEGRA186_CLUSTER0_CORE2 2
57#define TEGRA186_CLUSTER0_CORE3 3
58
59/*******************************************************************************
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080060 * The Tegra power domain tree has a single system level power domain i.e. a
61 * single root node. The first entry in the power domain descriptor specifies
62 * the number of power domains at the highest power level.
63 *******************************************************************************
64 */
65const unsigned char tegra_power_domain_tree_desc[] = {
66 /* No of root nodes */
67 1,
68 /* No of clusters */
69 PLATFORM_CLUSTER_COUNT,
70 /* No of CPU cores - cluster0 */
71 PLATFORM_MAX_CPUS_PER_CLUSTER,
72 /* No of CPU cores - cluster1 */
73 PLATFORM_MAX_CPUS_PER_CLUSTER
74};
75
Varun Wadekar921b9062015-08-25 17:03:14 +053076/*
77 * Table of regions to map using the MMU.
78 */
79static const mmap_region_t tegra_mmap[] = {
80 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
81 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekara0f26972016-03-11 17:18:51 -080082 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
83 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053084 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
85 MT_DEVICE | MT_RW | MT_SECURE),
86 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
87 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar9db0ad12016-07-12 10:04:28 -070088 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
89 MT_DEVICE | MT_RW | MT_SECURE),
90 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
91 MT_DEVICE | MT_RW | MT_SECURE),
92 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
Varun Wadekar921b9062015-08-25 17:03:14 +053093 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar4debe052016-05-18 13:39:16 -070094 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
95 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053096 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
97 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -080098 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
99 MT_DEVICE | MT_RW | MT_SECURE),
100 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
101 MT_DEVICE | MT_RW | MT_SECURE),
102 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
103 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekare60f1bf2016-02-17 10:10:50 -0800104 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
105 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +0530106 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
107 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -0800108 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
109 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +0530110 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
111 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekard64db962016-09-23 14:28:16 -0700112 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
113 MT_DEVICE | MT_RW | MT_SECURE),
Pritesh Raithatha0de6e532017-01-24 13:49:46 +0530114 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530115 MT_DEVICE | MT_RW | MT_SECURE),
116 {0}
117};
118
119/*******************************************************************************
120 * Set up the pagetables as per the platform memory map & initialize the MMU
121 ******************************************************************************/
122const mmap_region_t *plat_get_mmio_map(void)
123{
124 /* MMIO space */
125 return tegra_mmap;
126}
127
128/*******************************************************************************
129 * Handler to get the System Counter Frequency
130 ******************************************************************************/
Varun Wadekaref8a4fe2016-06-02 14:26:13 -0700131unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar921b9062015-08-25 17:03:14 +0530132{
Varun Wadekar20c94292016-01-04 10:57:45 -0800133 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530134}
135
136/*******************************************************************************
137 * Maximum supported UART controllers
138 ******************************************************************************/
139#define TEGRA186_MAX_UART_PORTS 7
140
141/*******************************************************************************
142 * This variable holds the UART port base addresses
143 ******************************************************************************/
144static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
145 0, /* undefined - treated as an error case */
146 TEGRA_UARTA_BASE,
147 TEGRA_UARTB_BASE,
148 TEGRA_UARTC_BASE,
149 TEGRA_UARTD_BASE,
150 TEGRA_UARTE_BASE,
151 TEGRA_UARTF_BASE,
152 TEGRA_UARTG_BASE,
153};
154
155/*******************************************************************************
156 * Retrieve the UART controller base to be used as the console
157 ******************************************************************************/
158uint32_t plat_get_console_from_id(int id)
159{
160 if (id > TEGRA186_MAX_UART_PORTS)
161 return 0;
162
163 return tegra186_uart_addresses[id];
164}
Varun Wadekarcad7b082015-12-28 18:12:59 -0800165
Varun Wadekar4debe052016-05-18 13:39:16 -0700166/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
167#define TEGRA186_VER_A02P 0x1201
168
169/*******************************************************************************
170 * Handler for early platform setup
171 ******************************************************************************/
172void plat_early_platform_setup(void)
173{
174 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
Varun Wadekar5887c102016-07-19 11:29:40 -0700175 uint32_t chip_subrev, val;
Varun Wadekar4debe052016-05-18 13:39:16 -0700176
177 /* sanity check MCE firmware compatibility */
178 mce_verify_firmware_version();
179
180 /*
181 * Enable ECC and Parity Protection for Cortex-A57 CPUs
182 * for Tegra A02p SKUs
183 */
184 if (impl != DENVER_IMPL) {
185
186 /* get the major, minor and sub-version values */
Varun Wadekar4debe052016-05-18 13:39:16 -0700187 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
188 SUBREVISION_MASK;
189
190 /* prepare chip version number */
Varun Wadekar5887c102016-07-19 11:29:40 -0700191 val = (tegra_get_chipid_major() << 12) |
192 (tegra_get_chipid_minor() << 8) |
193 chip_subrev;
Varun Wadekar4debe052016-05-18 13:39:16 -0700194
195 /* enable L2 ECC for Tegra186 A02P and beyond */
196 if (val >= TEGRA186_VER_A02P) {
197
198 val = read_l2ctlr_el1();
199 val |= L2_ECC_PARITY_PROTECTION_BIT;
200 write_l2ctlr_el1(val);
201
202 /*
203 * Set the flag to enable ECC/Parity Protection
204 * when we exit System Suspend or Cluster Powerdn
205 */
206 tegra_enable_l2_ecc_parity_prot = 1;
207 }
208 }
209}
210
Varun Wadekarcad7b082015-12-28 18:12:59 -0800211/* Secure IRQs for Tegra186 */
212static const irq_sec_cfg_t tegra186_sec_irqs[] = {
213 {
214 TEGRA186_TOP_WDT_IRQ,
215 TEGRA186_SEC_IRQ_TARGET_MASK,
216 INTR_TYPE_EL3,
217 },
218 {
219 TEGRA186_AON_WDT_IRQ,
220 TEGRA186_SEC_IRQ_TARGET_MASK,
221 INTR_TYPE_EL3,
222 },
223};
224
225/*******************************************************************************
226 * Initialize the GIC and SGIs
227 ******************************************************************************/
228void plat_gic_setup(void)
229{
230 tegra_gic_setup(tegra186_sec_irqs,
231 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
232
233 /*
234 * Initialize the FIQ handler only if the platform supports any
235 * FIQ interrupt sources.
236 */
237 if (sizeof(tegra186_sec_irqs) > 0)
238 tegra_fiq_handler_setup();
239}
Varun Wadekar94701ff2016-05-23 11:47:34 -0700240
241/*******************************************************************************
242 * Return pointer to the BL31 params from previous bootloader
243 ******************************************************************************/
244bl31_params_t *plat_get_bl31_params(void)
245{
246 uint32_t val;
247
248 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
249
250 return (bl31_params_t *)(uintptr_t)val;
251}
252
253/*******************************************************************************
254 * Return pointer to the BL31 platform params from previous bootloader
255 ******************************************************************************/
256plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
257{
258 uint32_t val;
259
260 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
261
262 return (plat_params_from_bl2_t *)(uintptr_t)val;
263}
Varun Wadekar43dad672017-01-31 14:53:37 -0800264
265/*******************************************************************************
266 * This function implements a part of the critical interface between the psci
267 * generic layer and the platform that allows the former to query the platform
268 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
269 * in case the MPIDR is invalid.
270 ******************************************************************************/
271int plat_core_pos_by_mpidr(u_register_t mpidr)
272{
273 unsigned int cluster_id, cpu_id, pos;
274
275 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
276 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
277
278 /*
279 * Validate cluster_id by checking whether it represents
280 * one of the two clusters present on the platform.
281 */
282 if (cluster_id >= PLATFORM_CLUSTER_COUNT)
283 return PSCI_E_NOT_PRESENT;
284
285 /*
286 * Validate cpu_id by checking whether it represents a CPU in
287 * one of the two clusters present on the platform.
288 */
289 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
290 return PSCI_E_NOT_PRESENT;
291
292 /* calculate the core position */
293 pos = cpu_id + (cluster_id << 2);
294
295 /* check for non-existent CPUs */
296 if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
297 return PSCI_E_NOT_PRESENT;
298
299 return pos;
300}