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Paul Beesleyf3653a62019-05-22 11:22:44 +01001STMicroelectronics STM32MP1
2===========================
Yann Gautier75115392018-07-16 14:49:34 +02003
4STM32MP1 is a microprocessor designed by STMicroelectronics
Sebastien Pasdeloup94389ef2020-12-18 11:50:40 +01005based on Arm Cortex-A7.
Yann Gautier75115392018-07-16 14:49:34 +02006It is an Armv7-A platform, using dedicated code from TF-A.
Yann Gautier969be342019-02-20 17:34:16 +01007More information can be found on `STM32MP1 Series`_ page.
Yann Gautier75115392018-07-16 14:49:34 +02008
9
Yann Gautier26c10672020-10-13 11:27:05 +020010STM32MP1 Versions
11-----------------
Sebastien Pasdeloup94389ef2020-12-18 11:50:40 +010012
13There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
14
15STM32MP13 Versions
16~~~~~~~~~~~~~~~~~~
17The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
18
19- STM32MP131: Single Cortex-A7 core
20- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
21- STM32MP135: STM32MP133 + DCMIPP, LTDC
22
23Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
24
25- A Cortex-A7 @ 650 MHz
26- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
27- D Cortex-A7 @ 900 MHz
28- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
29
30STM32MP15 Versions
31~~~~~~~~~~~~~~~~~~
32The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
Yann Gautier26c10672020-10-13 11:27:05 +020033
34- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
35- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
36- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
37
38Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
39
40- A Basic + Cortex-A7 @ 650 MHz
41- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
42- D Basic + Cortex-A7 @ 800 MHz
43- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
44
45The `STM32MP1 part number codification`_ page gives more information about part numbers.
46
Yann Gautier75115392018-07-16 14:49:34 +020047Design
48------
49The STM32MP1 resets in the ROM code of the Cortex-A7.
50The primary boot core (core 0) executes the boot sequence while
51secondary boot core (core 1) is kept in a holding pen loop.
52The ROM code boot sequence loads the TF-A binary image from boot device
53to embedded SRAM.
54
55The TF-A image must be properly formatted with a STM32 header structure
56for ROM code is able to load this image.
57Tool stm32image can be used to prepend this header to the generated TF-A binary.
58
Yann Gautier9730da02021-02-12 18:04:23 +010059Boot with FIP
60~~~~~~~~~~~~~
61The use of FIP is now the recommended way to boot STM32MP1 platform.
62Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
63inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective
64device tree blobs.
65
66STM32IMAGE bootchain
67~~~~~~~~~~~~~~~~~~~~
68Although still supported, this way of booting is not recommended.
69Pease use FIP instead.
Yann Gautier75115392018-07-16 14:49:34 +020070At compilation step, BL2, BL32 and DTB file are linked together in a single
71binary. The stm32image tool is also generated and the header is added to TF-A
72binary. This binary file with header is named tf-a-stm32mp157c-ev1.stm32.
73It can then be copied in the first partition of the boot device.
74
75
76Memory mapping
77~~~~~~~~~~~~~~
78
79::
80
81 0x00000000 +-----------------+
82 | | ROM
83 0x00020000 +-----------------+
84 | |
85 | ... |
86 | |
87 0x2FFC0000 +-----------------+ \
Yann Gautier9730da02021-02-12 18:04:23 +010088 | BL32 DTB | |
89 0x2FFC5000 +-----------------+ |
90 | BL32 | |
91 0x2FFDF000 +-----------------+ |
Yann Gautier75115392018-07-16 14:49:34 +020092 | ... | |
Yann Gautier9730da02021-02-12 18:04:23 +010093 0x2FFE3000 +-----------------+ |
94 | BL2 DTB | | Embedded SRAM
95 0x2FFEA000 +-----------------+ |
Yann Gautier75115392018-07-16 14:49:34 +020096 | BL2 | |
Yann Gautier9730da02021-02-12 18:04:23 +010097 0x2FFFF000 +-----------------+ |
98 | SCMI mailbox | |
Yann Gautier75115392018-07-16 14:49:34 +020099 0x30000000 +-----------------+ /
100 | |
101 | ... |
102 | |
103 0x40000000 +-----------------+
104 | |
105 | | Devices
106 | |
107 0xC0000000 +-----------------+ \
108 | | |
109 0xC0100000 +-----------------+ |
110 | BL33 | | Non-secure RAM (DDR)
111 | ... | |
112 | | |
113 0xFFFFFFFF +-----------------+ /
114
115
116Boot sequence
117~~~~~~~~~~~~~
118
119ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot)
120
Yann Gautierb3386f72019-04-19 09:41:01 +0200121or if Op-TEE is used:
122
123ROM code -> BL2 (compiled with BL2_AT_EL3) -> OP-TEE -> BL33 (U-Boot)
124
Yann Gautier75115392018-07-16 14:49:34 +0200125
126Build Instructions
127------------------
Lionel Debieve4066c902019-10-17 15:12:13 +0200128Boot media(s) supported by BL2 must be specified in the build command.
129Available storage medias are:
Yann Gautier23929132021-02-15 17:13:23 +0100130
Lionel Debieve4066c902019-10-17 15:12:13 +0200131- ``STM32MP_SDMMC``
132- ``STM32MP_EMMC``
133- ``STM32MP_RAW_NAND``
134- ``STM32MP_SPI_NAND``
135- ``STM32MP_SPI_NOR``
Yann Gautier75115392018-07-16 14:49:34 +0200136
Yann Gautier377fc852022-03-03 18:22:46 +0100137Serial boot devices:
138
139- ``STM32MP_UART_PROGRAMMER``
140- ``STM32MP_USB_PROGRAMMER``
141
142
143Other configuration flags:
144
145- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
146 | Default: stm32mp157c-ev1.dtb
Patrick Delaunay4c66e0a2022-03-15 11:20:56 +0100147- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
148 | default location (end of the first 128MB) is used when absent
Yann Gautier377fc852022-03-03 18:22:46 +0100149- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
150 | Default: 0 (disabled)
Yann Gautier312dde02022-09-13 13:53:41 +0200151- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
152 | Default: 0 (disabled)
Yann Gautierb02dd492022-03-02 14:31:55 +0100153- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
154 | Default: 115200
Yann Gautier377fc852022-03-03 18:22:46 +0100155- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
156 | Default: 0
Sebastien Pasdeloup94389ef2020-12-18 11:50:40 +0100157- | ``STM32MP13``: to select STM32MP13 variant configuration.
158 | Default: 0
159- | ``STM32MP15``: to select STM32MP15 variant configuration.
160 | Default: 1
Yann Gautier377fc852022-03-03 18:22:46 +0100161
162
Yann Gautier9730da02021-02-12 18:04:23 +0100163Boot with FIP
164~~~~~~~~~~~~~
165You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.
166
167U-Boot
168______
Yann Gautier75115392018-07-16 14:49:34 +0200169
170.. code:: bash
171
Yann Gautierb4ddd302018-10-24 10:50:12 +0200172 cd <u-boot_directory>
Yann Gautierb7168ee2019-05-20 11:50:18 +0200173 make stm32mp15_trusted_defconfig
Yann Gautier969be342019-02-20 17:34:16 +0100174 make DEVICE_TREE=stm32mp157c-ev1 all
Yann Gautier75115392018-07-16 14:49:34 +0200175
Yann Gautier9730da02021-02-12 18:04:23 +0100176OP-TEE (optional)
177_________________
Yann Gautier23929132021-02-15 17:13:23 +0100178
Yann Gautierb3386f72019-04-19 09:41:01 +0200179.. code:: bash
180
Lionel Debieve4066c902019-10-17 15:12:13 +0200181 cd <optee_directory>
Yann Gautier9730da02021-02-12 18:04:23 +0100182 make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
183 CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
184
185
186TF-A BL32 (SP_min)
187__________________
188If you choose not to use OP-TEE, you can use TF-A SP_min.
189To build TF-A BL32, and its device tree file:
190
191.. code:: bash
192
193 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
194 AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs
195
196TF-A BL2
197________
198To build TF-A BL2 with its STM32 header for SD-card boot:
199
200.. code:: bash
201
202 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
203 DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
204
205For other boot devices, you have to replace STM32MP_SDMMC in the previous command
206with the desired device flag.
207
208This BL2 is independent of the BL32 used (SP_min or OP-TEE)
209
210
211FIP
212___
213With BL32 SP_min:
214
215.. code:: bash
216
217 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
218 AARCH32_SP=sp_min \
219 DTB_FILE_NAME=stm32mp157c-ev1.dtb \
220 BL33=<u-boot_directory>/u-boot-nodtb.bin \
221 BL33_CFG=<u-boot_directory>/u-boot.dtb \
222 fip
223
224With OP-TEE:
225
226.. code:: bash
227
228 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
Yann Gautier39b82192021-10-21 14:57:52 +0200229 AARCH32_SP=optee \
Yann Gautier9730da02021-02-12 18:04:23 +0100230 DTB_FILE_NAME=stm32mp157c-ev1.dtb \
231 BL33=<u-boot_directory>/u-boot-nodtb.bin \
232 BL33_CFG=<u-boot_directory>/u-boot.dtb \
233 BL32=<optee_directory>/tee-header_v2.bin \
234 BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
235 BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin
236 fip
237
Lionel Debieve045e7f72022-10-06 09:00:14 +0200238Trusted Boot Board
239__________________
240
241.. code:: shell
242
243 tools/cert_create/cert_create -n --rot-key "build/stm32mp1/debug/rot_key.pem" \
244 --tfw-nvctr 0 \
245 --ntfw-nvctr 0 \
246 --key-alg ecdsa --hash-alg sha256 \
247 --trusted-key-cert build/stm32mp1/cert_images/trusted-key-cert.key-crt \
248 --tos-fw <optee_directory>/tee-header_v2.bin \
249 --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
250 --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
251 --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
252 --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
253 --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
254 --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
255 --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
256 --hw-config <u-boot_directory>/u-boot.dtb \
257 --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
258 --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt
259
260 tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
261 --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
262 --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
263 --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
264 --hw-config <u-boot_directory>/u-boot.dtb \
265 --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
266 --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
267 --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
268 --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
269 --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
270 --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip
271
Yann Gautier9730da02021-02-12 18:04:23 +0100272
273STM32IMAGE bootchain
274~~~~~~~~~~~~~~~~~~~~
275You need to add the following flag to the make command:
276``STM32MP_USE_STM32IMAGE=1``
277
278To build with SP_min and support for SD-card boot:
279
280.. code:: bash
281
282 make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
283 AARCH32_SP=sp_min STM32MP_SDMMC=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb \
284 STM32MP_USE_STM32IMAGE=1
285
286 cd <u-boot_directory>
287 make stm32mp15_trusted_defconfig
288 make DEVICE_TREE=stm32mp157c-ev1 all
289
290To build TF-A with OP-TEE support for SD-card boot:
291
292.. code:: bash
293
294 make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
295 AARCH32_SP=optee STM32MP_SDMMC=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb \
296 STM32MP_USE_STM32IMAGE=1
297
298 cd <optee_directory>
299 make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
300 CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
301
Lionel Debieve4066c902019-10-17 15:12:13 +0200302 cd <u-boot_directory>
Jan Kiszka30576a42020-10-02 10:07:00 +0200303 make stm32mp15_trusted_defconfig
Lionel Debieve4066c902019-10-17 15:12:13 +0200304 make DEVICE_TREE=stm32mp157c-ev1 all
305
Yann Gautierb3386f72019-04-19 09:41:01 +0200306
Yann Gautier75115392018-07-16 14:49:34 +0200307The following build options are supported:
308
309- ``ENABLE_STACK_PROTECTOR``: To enable the stack protection.
Yann Gautierb4ddd302018-10-24 10:50:12 +0200310
311
312Populate SD-card
313----------------
314
Yann Gautier9730da02021-02-12 18:04:23 +0100315Boot with FIP
316~~~~~~~~~~~~~
317The SD-card has to be formatted with GPT.
318It should contain at least those partitions:
319
320- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2)
321- fip: which contains the FIP binary
322
323Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
324
325STM32IMAGE bootchain
326~~~~~~~~~~~~~~~~~~~~
327The SD-card has to be formatted with GPT.
Yann Gautierb4ddd302018-10-24 10:50:12 +0200328It should contain at least those partitions:
329
330- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary
331- ssbl: to copy the u-boot.stm32 binary
332
333Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
Yann Gautier969be342019-02-20 17:34:16 +0100334
Jan Kiszka30576a42020-10-02 10:07:00 +0200335OP-TEE artifacts go into separate partitions as follows:
336
337- teeh: tee-header_v2.stm32
338- teed: tee-pageable_v2.stm32
339- teex: tee-pager_v2.stm32
340
Yann Gautier969be342019-02-20 17:34:16 +0100341
342.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
Yann Gautier26c10672020-10-13 11:27:05 +0200343.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification