feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index 7ae98b1..be86ae4 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -144,6 +144,8 @@
- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
| Default: stm32mp157c-ev1.dtb
+- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
+ | default location (end of the first 128MB) is used when absent
- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
| Default: 0 (disabled)
- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.