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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Firmware Design
2===============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
5Requirements (TBBR) Platform Design Document (PDD) [1]_ for Arm reference
Douglas Raillardd7c21b72017-06-28 15:23:03 +01006platforms. The TBB sequence starts when the platform is powered on and runs up
7to the stage where it hands-off control to firmware running in the normal
8world in DRAM. This is the cold boot path.
9
Dan Handley610e7e12018-03-01 18:44:00 +000010TF-A also implements the Power State Coordination Interface PDD [2]_ as a
11runtime service. PSCI is the interface from normal world software to firmware
12implementing power management use-cases (for example, secondary CPU boot,
13hotplug and idle). Normal world software can access TF-A runtime services via
14the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be
15used as mandated by the SMC Calling Convention [3]_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010016
Dan Handley610e7e12018-03-01 18:44:00 +000017TF-A implements a framework for configuring and managing interrupts generated
18in either security state. The details of the interrupt management framework
19and its design can be found in TF-A Interrupt Management Design guide [4]_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010020
Dan Handley610e7e12018-03-01 18:44:00 +000021TF-A also implements a library for setting up and managing the translation
John Tsichritzis2fd3d922019-05-28 13:13:39 +010022tables. The details of this library can be found in `Translation tables design`_.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010023
Dan Handley610e7e12018-03-01 18:44:00 +000024TF-A can be built to support either AArch64 or AArch32 execution state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010025
26Cold boot
27---------
28
29The cold boot path starts when the platform is physically turned on. If
30``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
31primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
32CPU is chosen through platform-specific means. The cold boot path is mainly
33executed by the primary CPU, other than essential CPU initialization executed by
34all CPUs. The secondary CPUs are kept in a safe platform-specific state until
35the primary CPU has performed enough initialization to boot them.
36
37Refer to the `Reset Design`_ for more information on the effect of the
38``COLD_BOOT_SINGLE_CPU`` platform build option.
39
Dan Handley610e7e12018-03-01 18:44:00 +000040The cold boot path in this implementation of TF-A depends on the execution
41state. For AArch64, it is divided into five steps (in order of execution):
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042
43- Boot Loader stage 1 (BL1) *AP Trusted ROM*
44- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
45- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
46- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
47- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
48
49For AArch32, it is divided into four steps (in order of execution):
50
51- Boot Loader stage 1 (BL1) *AP Trusted ROM*
52- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
53- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
54- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
55
Dan Handley610e7e12018-03-01 18:44:00 +000056Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010057combination of the following types of memory regions. Each bootloader stage uses
58one or more of these memory regions.
59
60- Regions accessible from both non-secure and secure states. For example,
61 non-trusted SRAM, ROM and DRAM.
62- Regions accessible from only the secure state. For example, trusted SRAM and
63 ROM. The FVPs also implement the trusted DRAM which is statically
64 configured. Additionally, the Base FVPs and Juno development platform
65 configure the TrustZone Controller (TZC) to create a region in the DRAM
66 which is accessible only from the secure state.
67
68The sections below provide the following details:
69
Soby Mathewb1bf0442018-02-16 14:52:52 +000070- dynamic configuration of Boot Loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +010071- initialization and execution of the first three stages during cold boot
72- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
73 AArch32) entrypoint requirements for use by alternative Trusted Boot
74 Firmware in place of the provided BL1 and BL2
75
Soby Mathewb1bf0442018-02-16 14:52:52 +000076Dynamic Configuration during cold boot
77~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
78
79Each of the Boot Loader stages may be dynamically configured if required by the
80platform. The Boot Loader stage may optionally specify a firmware
81configuration file and/or hardware configuration file as listed below:
82
83- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
84 stages and also by the Normal World Rich OS.
85- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
86 and BL2.
87- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
88- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
89 (BL32).
90- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
91 firmware (BL33).
92
93The Arm development platforms use the Flattened Device Tree format for the
94dynamic configuration files.
95
96Each Boot Loader stage can pass up to 4 arguments via registers to the next
97stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
98Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
99arguments are platform defined. The Arm development platforms use the following
100convention:
101
102- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
103 structure contains the memory layout available to BL2.
104- When dynamic configuration files are present, the firmware configuration for
105 the next Boot Loader stage is populated in the first available argument and
106 the generic hardware configuration is passed the next available argument.
107 For example,
108
109 - If TB_FW_CONFIG is loaded by BL1, then its address is passed in ``arg0``
110 to BL2.
111 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
112 BL2. Note, ``arg1`` is already used for meminfo_t.
113 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
114 to BL31. Note, ``arg0`` is used to pass the list of executable images.
115 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
116 passed in ``arg2`` to BL31.
117 - For other BL3x images, if the firmware configuration file is loaded by
118 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
119 then its address is passed in ``arg1``.
120
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100121BL1
122~~~
123
124This stage begins execution from the platform's reset vector at EL3. The reset
125address is platform dependent but it is usually located in a Trusted ROM area.
126The BL1 data section is copied to trusted SRAM at runtime.
127
Dan Handley610e7e12018-03-01 18:44:00 +0000128On the Arm development platforms, BL1 code starts execution from the reset
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100129vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
130to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
131
132The functionality implemented by this stage is as follows.
133
134Determination of boot path
135^^^^^^^^^^^^^^^^^^^^^^^^^^
136
137Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
138boot and a cold boot. This is done using platform-specific mechanisms (see the
139``plat_get_my_entrypoint()`` function in the `Porting Guide`_). In the case of a
140warm boot, a CPU is expected to continue execution from a separate
141entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
142platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
143the `Porting Guide`_) while the primary CPU executes the remaining cold boot path
144as described in the following sections.
145
146This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
147`Reset Design`_ for more information on the effect of the
148``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
149
150Architectural initialization
151^^^^^^^^^^^^^^^^^^^^^^^^^^^^
152
153BL1 performs minimal architectural initialization as follows.
154
155- Exception vectors
156
157 BL1 sets up simple exception vectors for both synchronous and asynchronous
158 exceptions. The default behavior upon receiving an exception is to populate
159 a status code in the general purpose register ``X0/R0`` and call the
160 ``plat_report_exception()`` function (see the `Porting Guide`_). The status
161 code is one of:
162
163 For AArch64:
164
165 ::
166
167 0x0 : Synchronous exception from Current EL with SP_EL0
168 0x1 : IRQ exception from Current EL with SP_EL0
169 0x2 : FIQ exception from Current EL with SP_EL0
170 0x3 : System Error exception from Current EL with SP_EL0
171 0x4 : Synchronous exception from Current EL with SP_ELx
172 0x5 : IRQ exception from Current EL with SP_ELx
173 0x6 : FIQ exception from Current EL with SP_ELx
174 0x7 : System Error exception from Current EL with SP_ELx
175 0x8 : Synchronous exception from Lower EL using aarch64
176 0x9 : IRQ exception from Lower EL using aarch64
177 0xa : FIQ exception from Lower EL using aarch64
178 0xb : System Error exception from Lower EL using aarch64
179 0xc : Synchronous exception from Lower EL using aarch32
180 0xd : IRQ exception from Lower EL using aarch32
181 0xe : FIQ exception from Lower EL using aarch32
182 0xf : System Error exception from Lower EL using aarch32
183
184 For AArch32:
185
186 ::
187
188 0x10 : User mode
189 0x11 : FIQ mode
190 0x12 : IRQ mode
191 0x13 : SVC mode
192 0x16 : Monitor mode
193 0x17 : Abort mode
194 0x1a : Hypervisor mode
195 0x1b : Undefined mode
196 0x1f : System mode
197
Dan Handley610e7e12018-03-01 18:44:00 +0000198 The ``plat_report_exception()`` implementation on the Arm FVP port programs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100199 the Versatile Express System LED register in the following format to
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000200 indicate the occurrence of an unexpected exception:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100201
202 ::
203
204 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
205 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
206 For AArch32 it is always 0x0
207 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
208 of the status code
209
210 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
211 CLCD window of the FVP.
212
213 BL1 does not expect to receive any exceptions other than the SMC exception.
214 For the latter, BL1 installs a simple stub. The stub expects to receive a
215 limited set of SMC types (determined by their function IDs in the general
216 purpose register ``X0/R0``):
217
218 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
219 to EL3 Runtime Software.
220 - All SMCs listed in section "BL1 SMC Interface" in the `Firmware Update`_
221 Design Guide are supported for AArch64 only. These SMCs are currently
222 not supported when BL1 is built for AArch32.
223
224 Any other SMC leads to an assertion failure.
225
226- CPU initialization
227
228 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
229 specific reset handler function (see the section: "CPU specific operations
230 framework").
231
232- Control register setup (for AArch64)
233
234 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
235 bit. Alignment and stack alignment checking is enabled by setting the
236 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
237 little-endian by clearing the ``SCTLR_EL3.EE`` bit.
238
239 - ``SCR_EL3``. The register width of the next lower exception level is set
240 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
241 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
242 also set to disable instruction fetches from Non-secure memory when in
243 secure state.
244
245 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
246 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
247 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
248 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
249 Instructions that access the registers associated with Floating Point
250 and Advanced SIMD execution are configured to not trap to EL3 by
251 clearing the ``CPTR_EL3.TFP`` bit.
252
253 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
254 mask bit.
255
256 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
257 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
258 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
259 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
260 disable AArch32 Secure self-hosted privileged debug from S-EL1.
261
262- Control register setup (for AArch32)
263
264 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
265 Alignment checking is enabled by setting the ``SCTLR.A`` bit.
266 Exception endianness is set to little-endian by clearing the
267 ``SCTLR.EE`` bit.
268
269 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
270 Non-secure memory when in secure state.
271
272 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
273 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
274 is configured not to trap to undefined mode by clearing the
275 ``CPACR.TRCDIS`` bit.
276
277 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
278 system register access to implemented trace registers.
279
280 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
281 functionality from all Exception levels.
282
283 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
284 the Asynchronous data abort interrupt mask bit.
285
286 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
287 self-hosted privileged debug.
288
289Platform initialization
290^^^^^^^^^^^^^^^^^^^^^^^
291
Dan Handley610e7e12018-03-01 18:44:00 +0000292On Arm platforms, BL1 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100293
294- Enable the Trusted Watchdog.
295- Initialize the console.
296- Configure the Interconnect to enable hardware coherency.
297- Enable the MMU and map the memory it needs to access.
298- Configure any required platform storage to load the next bootloader image
299 (BL2).
Soby Mathewb1bf0442018-02-16 14:52:52 +0000300- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
301 load it to the platform defined address and make it available to BL2 via
302 ``arg0``.
Soby Mathewd969a7e2018-06-11 16:40:36 +0100303- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U
304 and NS-BL2U firmware update images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100305
306Firmware Update detection and execution
307^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
308
309After performing platform setup, BL1 common code calls
310``bl1_plat_get_next_image_id()`` to determine if `Firmware Update`_ is required or
311to proceed with the normal boot process. If the platform code returns
312``BL2_IMAGE_ID`` then the normal boot sequence is executed as described in the
313next section, else BL1 assumes that `Firmware Update`_ is required and execution
314passes to the first image in the `Firmware Update`_ process. In either case, BL1
315retrieves a descriptor of the next image by calling ``bl1_plat_get_image_desc()``.
316The image descriptor contains an ``entry_point_info_t`` structure, which BL1
317uses to initialize the execution state of the next image.
318
319BL2 image load and execution
320^^^^^^^^^^^^^^^^^^^^^^^^^^^^
321
322In the normal boot flow, BL1 execution continues as follows:
323
324#. BL1 prints the following string from the primary CPU to indicate successful
325 execution of the BL1 stage:
326
327 ::
328
329 "Booting Trusted Firmware"
330
Soby Mathewb1bf0442018-02-16 14:52:52 +0000331#. BL1 loads a BL2 raw binary image from platform storage, at a
332 platform-specific base address. Prior to the load, BL1 invokes
333 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
334 use the image information. If the BL2 image file is not present or if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335 there is not enough free trusted SRAM the following error message is
336 printed:
337
338 ::
339
340 "Failed to load BL2 firmware."
341
Soby Mathewb1bf0442018-02-16 14:52:52 +0000342#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
343 for platforms to take further action after image load. This function must
344 populate the necessary arguments for BL2, which may also include the memory
345 layout. Further description of the memory layout can be found later
346 in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100347
348#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
349 Secure SVC mode (for AArch32), starting from its load address.
350
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351BL2
352~~~
353
354BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
355SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
356base address (more information can be found later in this document).
357The functionality implemented by BL2 is as follows.
358
359Architectural initialization
360^^^^^^^^^^^^^^^^^^^^^^^^^^^^
361
362For AArch64, BL2 performs the minimal architectural initialization required
Dan Handley610e7e12018-03-01 18:44:00 +0000363for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
364access to Floating Point and Advanced SIMD registers by clearing the
365``CPACR.FPEN`` bits.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100366
367For AArch32, the minimal architectural initialization required for subsequent
Dan Handley610e7e12018-03-01 18:44:00 +0000368stages of TF-A and normal world software is taken care of in BL1 as both BL1
369and BL2 execute at PL1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100370
371Platform initialization
372^^^^^^^^^^^^^^^^^^^^^^^
373
Dan Handley610e7e12018-03-01 18:44:00 +0000374On Arm platforms, BL2 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100375
376- Initialize the console.
377- Configure any required platform storage to allow loading further bootloader
378 images.
379- Enable the MMU and map the memory it needs to access.
380- Perform platform security setup to allow access to controlled components.
381- Reserve some memory for passing information to the next bootloader image
382 EL3 Runtime Software and populate it.
383- Define the extents of memory available for loading each subsequent
384 bootloader image.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000385- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
386 then parse it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387
388Image loading in BL2
389^^^^^^^^^^^^^^^^^^^^
390
Roberto Vargas025946a2018-09-24 17:20:48 +0100391BL2 generic code loads the images based on the list of loadable images
392provided by the platform. BL2 passes the list of executable images
393provided by the platform to the next handover BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394
Soby Mathewb1bf0442018-02-16 14:52:52 +0000395The list of loadable images provided by the platform may also contain
396dynamic configuration files. The files are loaded and can be parsed as
397needed in the ``bl2_plat_handle_post_image_load()`` function. These
398configuration files can be passed to next Boot Loader stages as arguments
399by updating the corresponding entrypoint information in this function.
400
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100401SCP_BL2 (System Control Processor Firmware) image load
402^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100403
404Some systems have a separate System Control Processor (SCP) for power, clock,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100405reset and system control. BL2 loads the optional SCP_BL2 image from platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100406storage into a platform-specific region of secure memory. The subsequent
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100407handling of SCP_BL2 is platform specific. For example, on the Juno Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100408development platform port the image is transferred into SCP's internal memory
409using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100410memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100411for BL2 execution to continue.
412
413EL3 Runtime Software image load
414^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
415
416BL2 loads the EL3 Runtime Software image from platform storage into a platform-
417specific address in trusted SRAM. If there is not enough memory to load the
Roberto Vargas025946a2018-09-24 17:20:48 +0100418image or image is missing it leads to an assertion failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100419
420AArch64 BL32 (Secure-EL1 Payload) image load
421^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
422
423BL2 loads the optional BL32 image from platform storage into a platform-
424specific region of secure memory. The image executes in the secure world. BL2
425relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
426populates a platform-specific area of memory with the entrypoint/load-address
427of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
428for entry into BL32 is not determined by BL2, it is initialized by the
429Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
430managing interaction with BL32. This information is passed to BL31.
431
432BL33 (Non-trusted Firmware) image load
433^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
434
435BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
436platform storage into non-secure memory as defined by the platform.
437
438BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
439initialization is complete. Hence, BL2 populates a platform-specific area of
440memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
441normal world software image. The entrypoint is the load address of the BL33
442image. The ``SPSR`` is determined as specified in Section 5.13 of the
443`PSCI PDD`_. This information is passed to the EL3 Runtime Software.
444
445AArch64 BL31 (EL3 Runtime Software) execution
446^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
447
448BL2 execution continues as follows:
449
450#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
451 BL31 entrypoint. The exception is handled by the SMC exception handler
452 installed by BL1.
453
454#. BL1 turns off the MMU and flushes the caches. It clears the
455 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
456 and invalidates the TLBs.
457
458#. BL1 passes control to BL31 at the specified entrypoint at EL3.
459
Roberto Vargasb1584272017-11-20 13:36:10 +0000460Running BL2 at EL3 execution level
461~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
462
Dan Handley610e7e12018-03-01 18:44:00 +0000463Some platforms have a non-TF-A Boot ROM that expects the next boot stage
464to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
465as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
Roberto Vargasb1584272017-11-20 13:36:10 +0000466this waste, a special mode enables BL2 to execute at EL3, which allows
Dan Handley610e7e12018-03-01 18:44:00 +0000467a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
Roberto Vargasb1584272017-11-20 13:36:10 +0000468when the build flag BL2_AT_EL3 is enabled. The main differences in this
469mode are:
470
471#. BL2 includes the reset code and the mailbox mechanism to differentiate
472 cold boot and warm boot. It runs at EL3 doing the arch
473 initialization required for EL3.
474
475#. BL2 does not receive the meminfo information from BL1 anymore. This
476 information can be passed by the Boot ROM or be internal to the
477 BL2 image.
478
479#. Since BL2 executes at EL3, BL2 jumps directly to the next image,
480 instead of invoking the RUN_IMAGE SMC call.
481
482
483We assume 3 different types of BootROM support on the platform:
484
485#. The Boot ROM always jumps to the same address, for both cold
486 and warm boot. In this case, we will need to keep a resident part
487 of BL2 whose memory cannot be reclaimed by any other image. The
488 linker script defines the symbols __TEXT_RESIDENT_START__ and
489 __TEXT_RESIDENT_END__ that allows the platform to configure
490 correctly the memory map.
491#. The platform has some mechanism to indicate the jump address to the
492 Boot ROM. Platform code can then program the jump address with
493 psci_warmboot_entrypoint during cold boot.
494#. The platform has some mechanism to program the reset address using
495 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then
496 program the reset address with psci_warmboot_entrypoint during
497 cold boot, bypassing the boot ROM for warm boot.
498
499In the last 2 cases, no part of BL2 needs to remain resident at
500runtime. In the first 2 cases, we expect the Boot ROM to be able to
501differentiate between warm and cold boot, to avoid loading BL2 again
502during warm boot.
503
504This functionality can be tested with FVP loading the image directly
505in memory and changing the address where the system jumps at reset.
506For example:
507
Dimitris Papastamos25836492018-06-11 11:07:58 +0100508 -C cluster0.cpu0.RVBAR=0x4022000
509 --data cluster0.cpu0=bl2.bin@0x4022000
Roberto Vargasb1584272017-11-20 13:36:10 +0000510
511With this configuration, FVP is like a platform of the first case,
512where the Boot ROM jumps always to the same address. For simplification,
513BL32 is loaded in DRAM in this case, to avoid other images reclaiming
514BL2 memory.
515
516
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100517AArch64 BL31
518~~~~~~~~~~~~
519
520The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
521EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
522loaded at a platform-specific base address (more information can be found later
523in this document). The functionality implemented by BL31 is as follows.
524
525Architectural initialization
526^^^^^^^^^^^^^^^^^^^^^^^^^^^^
527
528Currently, BL31 performs a similar architectural initialization to BL1 as
529far as system register settings are concerned. Since BL1 code resides in ROM,
530architectural initialization in BL31 allows override of any previous
531initialization done by BL1.
532
533BL31 initializes the per-CPU data framework, which provides a cache of
534frequently accessed per-CPU data optimised for fast, concurrent manipulation
535on different CPUs. This buffer includes pointers to per-CPU contexts, crash
536buffer, CPU reset and power down operations, PSCI data, platform data and so on.
537
538It then replaces the exception vectors populated by BL1 with its own. BL31
539exception vectors implement more elaborate support for handling SMCs since this
540is the only mechanism to access the runtime services implemented by BL31 (PSCI
541for example). BL31 checks each SMC for validity as specified by the
542`SMC calling convention PDD`_ before passing control to the required SMC
543handler routine.
544
545BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
546counter, which is provided by the platform.
547
548Platform initialization
549^^^^^^^^^^^^^^^^^^^^^^^
550
551BL31 performs detailed platform initialization, which enables normal world
552software to function correctly.
553
Dan Handley610e7e12018-03-01 18:44:00 +0000554On Arm platforms, this consists of the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100555
556- Initialize the console.
557- Configure the Interconnect to enable hardware coherency.
558- Enable the MMU and map the memory it needs to access.
559- Initialize the generic interrupt controller.
560- Initialize the power controller device.
561- Detect the system topology.
562
563Runtime services initialization
564^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
565
566BL31 is responsible for initializing the runtime services. One of them is PSCI.
567
568As part of the PSCI initializations, BL31 detects the system topology. It also
569initializes the data structures that implement the state machine used to track
570the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
571``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
572that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
573initializes the locks that protect them. BL31 accesses the state of a CPU or
574cluster immediately after reset and before the data cache is enabled in the
575warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
576therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
577
578The runtime service framework and its initialization is described in more
579detail in the "EL3 runtime services framework" section below.
580
581Details about the status of the PSCI implementation are provided in the
582"Power State Coordination Interface" section below.
583
584AArch64 BL32 (Secure-EL1 Payload) image initialization
585^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
586
587If a BL32 image is present then there must be a matching Secure-EL1 Payload
588Dispatcher (SPD) service (see later for details). During initialization
589that service must register a function to carry out initialization of BL32
590once the runtime services are fully initialized. BL31 invokes such a
591registered function to initialize BL32 before running BL33. This initialization
592is not necessary for AArch32 SPs.
593
594Details on BL32 initialization and the SPD's role are described in the
595"Secure-EL1 Payloads and Dispatchers" section below.
596
597BL33 (Non-trusted Firmware) execution
598^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
599
600EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
601world cold boot, ensuring that no secure state information finds its way into
602the non-secure execution state. EL3 Runtime Software uses the entrypoint
603information provided by BL2 to jump to the Non-trusted firmware image (BL33)
604at the highest available Exception Level (EL2 if available, otherwise EL1).
605
606Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
607~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
608
609Some platforms have existing implementations of Trusted Boot Firmware that
Dan Handley610e7e12018-03-01 18:44:00 +0000610would like to use TF-A BL31 for the EL3 Runtime Software. To enable this
611firmware architecture it is important to provide a fully documented and stable
612interface between the Trusted Boot Firmware and BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100613
614Future changes to the BL31 interface will be done in a backwards compatible
615way, and this enables these firmware components to be independently enhanced/
616updated to develop and exploit new functionality.
617
618Required CPU state when calling ``bl31_entrypoint()`` during cold boot
619^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
620
621This function must only be called by the primary CPU.
622
623On entry to this function the calling primary CPU must be executing in AArch64
624EL3, little-endian data access, and all interrupt sources masked:
625
626::
627
628 PSTATE.EL = 3
629 PSTATE.RW = 1
630 PSTATE.DAIF = 0xf
631 SCTLR_EL3.EE = 0
632
633X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
634platform code in BL31:
635
636::
637
Dan Handley610e7e12018-03-01 18:44:00 +0000638 X0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100639 X1 : Platform specific information
640
641BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
642these will be zero filled prior to invoking platform setup code.
643
644Use of the X0 and X1 parameters
645'''''''''''''''''''''''''''''''
646
647The parameters are platform specific and passed from ``bl31_entrypoint()`` to
648``bl31_early_platform_setup()``. The value of these parameters is never directly
649used by the common BL31 code.
650
651The convention is that ``X0`` conveys information regarding the BL31, BL32 and
652BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
Dan Handley610e7e12018-03-01 18:44:00 +0000653platform specific purpose. This convention allows platforms which use TF-A's
654BL1 and BL2 images to transfer additional platform specific information from
655Secure Boot without conflicting with future evolution of TF-A using ``X0`` to
656pass a ``bl31_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100657
658BL31 common and SPD initialization code depends on image and entrypoint
659information about BL33 and BL32, which is provided via BL31 platform APIs.
660This information is required until the start of execution of BL33. This
661information can be provided in a platform defined manner, e.g. compiled into
662the platform code in BL31, or provided in a platform defined memory location
663by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
664Cold boot Initialization parameters. This data may need to be cleaned out of
665the CPU caches if it is provided by an earlier boot stage and then accessed by
666BL31 platform code before the caches are enabled.
667
Dan Handley610e7e12018-03-01 18:44:00 +0000668TF-A's BL2 implementation passes a ``bl31_params`` structure in
669``X0`` and the Arm development platforms interpret this in the BL31 platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100670code.
671
672MMU, Data caches & Coherency
673''''''''''''''''''''''''''''
674
675BL31 does not depend on the enabled state of the MMU, data caches or
676interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
677on entry, these should be enabled during ``bl31_plat_arch_setup()``.
678
679Data structures used in the BL31 cold boot interface
680''''''''''''''''''''''''''''''''''''''''''''''''''''
681
682These structures are designed to support compatibility and independent
683evolution of the structures and the firmware images. For example, a version of
684BL31 that can interpret the BL3x image information from different versions of
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100685BL2, a platform that uses an extended entry_point_info structure to convey
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100686additional register information to BL31, or a ELF image loader that can convey
687more details about the firmware images.
688
689To support these scenarios the structures are versioned and sized, which enables
690BL31 to detect which information is present and respond appropriately. The
691``param_header`` is defined to capture this information:
692
693.. code:: c
694
695 typedef struct param_header {
696 uint8_t type; /* type of the structure */
697 uint8_t version; /* version of this structure */
698 uint16_t size; /* size of this structure in bytes */
699 uint32_t attr; /* attributes: unused bits SBZ */
700 } param_header_t;
701
702The structures using this format are ``entry_point_info``, ``image_info`` and
703``bl31_params``. The code that allocates and populates these structures must set
704the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
705to simplify this action.
706
707Required CPU state for BL31 Warm boot initialization
708^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
709
Dan Handley610e7e12018-03-01 18:44:00 +0000710When requesting a CPU power-on, or suspending a running CPU, TF-A provides
711the platform power management code with a Warm boot initialization
712entry-point, to be invoked by the CPU immediately after the reset handler.
713On entry to the Warm boot initialization function the calling CPU must be in
714AArch64 EL3, little-endian data access and all interrupt sources masked:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100715
716::
717
718 PSTATE.EL = 3
719 PSTATE.RW = 1
720 PSTATE.DAIF = 0xf
721 SCTLR_EL3.EE = 0
722
723The PSCI implementation will initialize the processor state and ensure that the
724platform power management code is then invoked as required to initialize all
725necessary system, cluster and CPU resources.
726
727AArch32 EL3 Runtime Software entrypoint interface
728~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
729
730To enable this firmware architecture it is important to provide a fully
731documented and stable interface between the Trusted Boot Firmware and the
732AArch32 EL3 Runtime Software.
733
734Future changes to the entrypoint interface will be done in a backwards
735compatible way, and this enables these firmware components to be independently
736enhanced/updated to develop and exploit new functionality.
737
738Required CPU state when entering during cold boot
739^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
740
741This function must only be called by the primary CPU.
742
743On entry to this function the calling primary CPU must be executing in AArch32
744EL3, little-endian data access, and all interrupt sources masked:
745
746::
747
748 PSTATE.AIF = 0x7
749 SCTLR.EE = 0
750
751R0 and R1 are used to pass information from the Trusted Boot Firmware to the
752platform code in AArch32 EL3 Runtime Software:
753
754::
755
Dan Handley610e7e12018-03-01 18:44:00 +0000756 R0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100757 R1 : Platform specific information
758
759Use of the R0 and R1 parameters
760'''''''''''''''''''''''''''''''
761
762The parameters are platform specific and the convention is that ``R0`` conveys
763information regarding the BL3x images from the Trusted Boot firmware and ``R1``
764can be used for other platform specific purpose. This convention allows
Dan Handley610e7e12018-03-01 18:44:00 +0000765platforms which use TF-A's BL1 and BL2 images to transfer additional platform
766specific information from Secure Boot without conflicting with future
767evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100768
769The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
770information can be obtained in a platform defined manner, e.g. compiled into
771the AArch32 EL3 Runtime Software, or provided in a platform defined memory
772location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
773via the Cold boot Initialization parameters. This data may need to be cleaned
774out of the CPU caches if it is provided by an earlier boot stage and then
775accessed by AArch32 EL3 Runtime Software before the caches are enabled.
776
Dan Handley610e7e12018-03-01 18:44:00 +0000777When using AArch32 EL3 Runtime Software, the Arm development platforms pass a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100778``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
779Software platform code.
780
781MMU, Data caches & Coherency
782''''''''''''''''''''''''''''
783
784AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
785data caches or interconnect coherency in its entrypoint. They must be explicitly
786enabled if required.
787
788Data structures used in cold boot interface
789'''''''''''''''''''''''''''''''''''''''''''
790
791The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
792of ``bl31_params``. The ``bl_params`` structure is based on the convention
793described in AArch64 BL31 cold boot interface section.
794
795Required CPU state for warm boot initialization
796^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
797
798When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
799Runtime Software must ensure execution of a warm boot initialization entrypoint.
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100800If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false,
Dan Handley610e7e12018-03-01 18:44:00 +0000801then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
802boot entrypoint by arranging for the BL1 platform function,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100803plat_get_my_entrypoint(), to return a non-zero value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100804
805In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
806data access and all interrupt sources masked:
807
808::
809
810 PSTATE.AIF = 0x7
811 SCTLR.EE = 0
812
Dan Handley610e7e12018-03-01 18:44:00 +0000813The warm boot entrypoint may be implemented by using TF-A
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100814``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
815the pre-requisites mentioned in the `PSCI Library integration guide`_.
816
817EL3 runtime services framework
818------------------------------
819
820Software executing in the non-secure state and in the secure state at exception
821levels lower than EL3 will request runtime services using the Secure Monitor
822Call (SMC) instruction. These requests will follow the convention described in
823the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
824identifiers to each SMC request and describes how arguments are passed and
825returned.
826
827The EL3 runtime services framework enables the development of services by
828different providers that can be easily integrated into final product firmware.
829The following sections describe the framework which facilitates the
830registration, initialization and use of runtime services in EL3 Runtime
831Software (BL31).
832
833The design of the runtime services depends heavily on the concepts and
834definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
835Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
836conventions. Please refer to that document for more detailed explanation of
837these terms.
838
839The following runtime services are expected to be implemented first. They have
840not all been instantiated in the current implementation.
841
842#. Standard service calls
843
844 This service is for management of the entire system. The Power State
845 Coordination Interface (`PSCI`_) is the first set of standard service calls
Dan Handley610e7e12018-03-01 18:44:00 +0000846 defined by Arm (see PSCI section later).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100847
848#. Secure-EL1 Payload Dispatcher service
849
850 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
851 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
852 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
853 The Secure Monitor will make these world switches in response to SMCs. The
854 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
855 Application Call OEN ranges.
856
857 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
858 not defined by the `SMCCC`_ or any other standard. As a result, each
859 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000860 service - within TF-A this service is referred to as the Secure-EL1 Payload
861 Dispatcher (SPD).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100862
Dan Handley610e7e12018-03-01 18:44:00 +0000863 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
864 (TSPD). Details of SPD design and TSP/TSPD operation are described in the
865 "Secure-EL1 Payloads and Dispatchers" section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100866
867#. CPU implementation service
868
869 This service will provide an interface to CPU implementation specific
870 services for a given platform e.g. access to processor errata workarounds.
871 This service is currently unimplemented.
872
Dan Handley610e7e12018-03-01 18:44:00 +0000873Additional services for Arm Architecture, SiP and OEM calls can be implemented.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100874Each implemented service handles a range of SMC function identifiers as
875described in the `SMCCC`_.
876
877Registration
878~~~~~~~~~~~~
879
880A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
881the name of the service, the range of OENs covered, the type of service and
882initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
883This structure is allocated in a special ELF section ``rt_svc_descs``, enabling
884the framework to find all service descriptors included into BL31.
885
886The specific service for a SMC Function is selected based on the OEN and call
887type of the Function ID, and the framework uses that information in the service
888descriptor to identify the handler for the SMC Call.
889
890The service descriptors do not include information to identify the precise set
891of SMC function identifiers supported by this service implementation, the
892security state from which such calls are valid nor the capability to support
89364-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
894to these aspects of a SMC call is the responsibility of the service
895implementation, the framework is focused on integration of services from
896different providers and minimizing the time taken by the framework before the
897service handler is invoked.
898
899Details of the parameters, requirements and behavior of the initialization and
900call handling functions are provided in the following sections.
901
902Initialization
903~~~~~~~~~~~~~~
904
905``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
906framework running on the primary CPU during cold boot as part of the BL31
907initialization. This happens prior to initializing a Trusted OS and running
908Normal world boot firmware that might in turn use these services.
909Initialization involves validating each of the declared runtime service
910descriptors, calling the service initialization function and populating the
911index used for runtime lookup of the service.
912
913The BL31 linker script collects all of the declared service descriptors into a
914single array and defines symbols that allow the framework to locate and traverse
915the array, and determine its size.
916
917The framework does basic validation of each descriptor to halt firmware
918initialization if service declaration errors are detected. The framework does
919not check descriptors for the following error conditions, and may behave in an
920unpredictable manner under such scenarios:
921
922#. Overlapping OEN ranges
923#. Multiple descriptors for the same range of OENs and ``call_type``
924#. Incorrect range of owning entity numbers for a given ``call_type``
925
926Once validated, the service ``init()`` callback is invoked. This function carries
927out any essential EL3 initialization before servicing requests. The ``init()``
928function is only invoked on the primary CPU during cold boot. If the service
929uses per-CPU data this must either be initialized for all CPUs during this call,
930or be done lazily when a CPU first issues an SMC call to that service. If
931``init()`` returns anything other than ``0``, this is treated as an initialization
932error and the service is ignored: this does not cause the firmware to halt.
933
934The OEN and call type fields present in the SMC Function ID cover a total of
935128 distinct services, but in practice a single descriptor can cover a range of
936OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
937service handler, the framework uses an array of 128 indices that map every
938distinct OEN/call-type combination either to one of the declared services or to
939indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
940populated for all of the OENs covered by a service after the service ``init()``
941function has reported success. So a service that fails to initialize will never
942have it's ``handle()`` function invoked.
943
944The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
945Function ID call type and OEN onto a specific service handler in the
946``rt_svc_descs[]`` array.
947
948|Image 1|
949
950Handling an SMC
951~~~~~~~~~~~~~~~
952
953When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
954Function ID is passed in W0 from the lower exception level (as per the
955`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
956SMC Function which indicates the SMC64 calling convention: such calls are
957ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
958in R0/X0.
959
960Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
961Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
962resulting value might indicate a service that has no handler, in this case the
963framework will also report an Unknown SMC Function ID. Otherwise, the value is
964used as a further index into the ``rt_svc_descs[]`` array to locate the required
965service and handler.
966
967The service's ``handle()`` callback is provided with five of the SMC parameters
968directly, the others are saved into memory for retrieval (if needed) by the
969handler. The handler is also provided with an opaque ``handle`` for use with the
970supporting library for parameter retrieval, setting return values and context
971manipulation; and with ``flags`` indicating the security state of the caller. The
972framework finally sets up the execution stack for the handler, and invokes the
973services ``handle()`` function.
974
975On return from the handler the result registers are populated in X0-X3 before
976restoring the stack and CPU state and returning from the original SMC.
977
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +0100978Exception Handling Framework
979----------------------------
980
981Please refer to the `Exception Handling Framework`_ document.
982
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100983Power State Coordination Interface
984----------------------------------
985
986TODO: Provide design walkthrough of PSCI implementation.
987
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100988The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
989mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100990`Power State Coordination Interface PDD`_ are implemented. The table lists
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100991the PSCI v1.1 APIs and their support in generic code.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100992
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100993An API implementation might have a dependency on platform code e.g. CPU_SUSPEND
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100994requires the platform to export a part of the implementation. Hence the level
995of support of the mandatory APIs depends upon the support exported by the
996platform port as well. The Juno and FVP (all variants) platforms export all the
997required support.
998
999+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001000| PSCI v1.1 API | Supported | Comments |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001001+=============================+=============+===============================+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001002| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001003+-----------------------------+-------------+-------------------------------+
1004| ``CPU_SUSPEND`` | Yes\* | |
1005+-----------------------------+-------------+-------------------------------+
1006| ``CPU_OFF`` | Yes\* | |
1007+-----------------------------+-------------+-------------------------------+
1008| ``CPU_ON`` | Yes\* | |
1009+-----------------------------+-------------+-------------------------------+
1010| ``AFFINITY_INFO`` | Yes | |
1011+-----------------------------+-------------+-------------------------------+
1012| ``MIGRATE`` | Yes\*\* | |
1013+-----------------------------+-------------+-------------------------------+
1014| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
1015+-----------------------------+-------------+-------------------------------+
1016| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
1017+-----------------------------+-------------+-------------------------------+
1018| ``SYSTEM_OFF`` | Yes\* | |
1019+-----------------------------+-------------+-------------------------------+
1020| ``SYSTEM_RESET`` | Yes\* | |
1021+-----------------------------+-------------+-------------------------------+
1022| ``PSCI_FEATURES`` | Yes | |
1023+-----------------------------+-------------+-------------------------------+
1024| ``CPU_FREEZE`` | No | |
1025+-----------------------------+-------------+-------------------------------+
1026| ``CPU_DEFAULT_SUSPEND`` | No | |
1027+-----------------------------+-------------+-------------------------------+
1028| ``NODE_HW_STATE`` | Yes\* | |
1029+-----------------------------+-------------+-------------------------------+
1030| ``SYSTEM_SUSPEND`` | Yes\* | |
1031+-----------------------------+-------------+-------------------------------+
1032| ``PSCI_SET_SUSPEND_MODE`` | No | |
1033+-----------------------------+-------------+-------------------------------+
1034| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
1035+-----------------------------+-------------+-------------------------------+
1036| ``PSCI_STAT_COUNT`` | Yes\* | |
1037+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001038| ``SYSTEM_RESET2`` | Yes\* | |
1039+-----------------------------+-------------+-------------------------------+
1040| ``MEM_PROTECT`` | Yes\* | |
1041+-----------------------------+-------------+-------------------------------+
1042| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
1043+-----------------------------+-------------+-------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001044
1045\*Note : These PSCI APIs require platform power management hooks to be
1046registered with the generic PSCI code to be supported.
1047
1048\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
1049hooks to be registered with the generic PSCI code to be supported.
1050
Dan Handley610e7e12018-03-01 18:44:00 +00001051The PSCI implementation in TF-A is a library which can be integrated with
1052AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to
1053integrating PSCI library with AArch32 EL3 Runtime Software can be found
1054`here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001055
1056Secure-EL1 Payloads and Dispatchers
1057-----------------------------------
1058
1059On a production system that includes a Trusted OS running in Secure-EL1/EL0,
1060the Trusted OS is coupled with a companion runtime service in the BL31
1061firmware. This service is responsible for the initialisation of the Trusted
1062OS and all communications with it. The Trusted OS is the BL32 stage of the
Dan Handley610e7e12018-03-01 18:44:00 +00001063boot flow in TF-A. The firmware will attempt to locate, load and execute a
1064BL32 image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001065
Dan Handley610e7e12018-03-01 18:44:00 +00001066TF-A uses a more general term for the BL32 software that runs at Secure-EL1 -
1067the *Secure-EL1 Payload* - as it is not always a Trusted OS.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001068
Dan Handley610e7e12018-03-01 18:44:00 +00001069TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
1070Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a
1071production system using the Runtime Services Framework. On such a system, the
1072Test BL32 image and service are replaced by the Trusted OS and its dispatcher
1073service. The TF-A build system expects that the dispatcher will define the
1074build flag ``NEED_BL32`` to enable it to include the BL32 in the build either
1075as a binary or to compile from source depending on whether the ``BL32`` build
1076option is specified or not.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001077
1078The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
1079communication with the normal-world software running in EL1/EL2. Communication
1080is initiated by the normal-world software
1081
1082- either directly through a Fast SMC (as defined in the `SMCCC`_)
1083
1084- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
1085 informs the TSPD about the requested power management operation. This allows
1086 the TSP to prepare for or respond to the power state change
1087
1088The TSPD service is responsible for.
1089
1090- Initializing the TSP
1091
1092- Routing requests and responses between the secure and the non-secure
1093 states during the two types of communications just described
1094
1095Initializing a BL32 Image
1096~~~~~~~~~~~~~~~~~~~~~~~~~
1097
1098The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1099the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1100so. This is provided by:
1101
1102.. code:: c
1103
1104 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1105
1106which returns a reference to the ``entry_point_info`` structure corresponding to
1107the image which will be run in the specified security state. The SPD uses this
1108API to get entry point information for the SECURE image, BL32.
1109
1110In the absence of a BL32 image, BL31 passes control to the normal world
1111bootloader image (BL33). When the BL32 image is present, it is typical
1112that the SPD wants control to be passed to BL32 first and then later to BL33.
1113
1114To do this the SPD has to register a BL32 initialization function during
1115initialization of the SPD service. The BL32 initialization function has this
1116prototype:
1117
1118.. code:: c
1119
1120 int32_t init(void);
1121
1122and is registered using the ``bl31_register_bl32_init()`` function.
1123
Dan Handley610e7e12018-03-01 18:44:00 +00001124TF-A supports two approaches for the SPD to pass control to BL32 before
1125returning through EL3 and running the non-trusted firmware (BL33):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001126
1127#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1128 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1129 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1130 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1131
1132 When the BL32 has completed initialization at Secure-EL1, it returns to
1133 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1134 receipt of this SMC, the SPD service handler should switch the CPU context
1135 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1136 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1137 the normal world firmware BL33. On return from the handler the framework
1138 will exit to EL2 and run BL33.
1139
1140#. The BL32 setup function registers an initialization function using
1141 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1142 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1143 entrypoint.
Paul Beesleyba3ed402019-03-13 16:20:44 +00001144
1145 .. note::
1146 The Test SPD service included with TF-A provides one implementation
1147 of such a mechanism.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001148
1149 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1150 SPD service handler invokes the synchronous call return mechanism to return
1151 to the BL32 initialization function. On return from this function,
1152 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1153 continue the boot process in the normal world.
1154
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01001155Crash Reporting in BL31
1156-----------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001157
1158BL31 implements a scheme for reporting the processor state when an unhandled
1159exception is encountered. The reporting mechanism attempts to preserve all the
1160register contents and report it via a dedicated UART (PL011 console). BL31
1161reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1162
1163A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1164the per-CPU pointer cache. The implementation attempts to minimise the memory
1165required for this feature. The file ``crash_reporting.S`` contains the
1166implementation for crash reporting.
1167
1168The sample crash output is shown below.
1169
1170::
1171
1172 x0 :0x000000004F00007C
1173 x1 :0x0000000007FFFFFF
1174 x2 :0x0000000004014D50
1175 x3 :0x0000000000000000
1176 x4 :0x0000000088007998
1177 x5 :0x00000000001343AC
1178 x6 :0x0000000000000016
1179 x7 :0x00000000000B8A38
1180 x8 :0x00000000001343AC
1181 x9 :0x00000000000101A8
1182 x10 :0x0000000000000002
1183 x11 :0x000000000000011C
1184 x12 :0x00000000FEFDC644
1185 x13 :0x00000000FED93FFC
1186 x14 :0x0000000000247950
1187 x15 :0x00000000000007A2
1188 x16 :0x00000000000007A4
1189 x17 :0x0000000000247950
1190 x18 :0x0000000000000000
1191 x19 :0x00000000FFFFFFFF
1192 x20 :0x0000000004014D50
1193 x21 :0x000000000400A38C
1194 x22 :0x0000000000247950
1195 x23 :0x0000000000000010
1196 x24 :0x0000000000000024
1197 x25 :0x00000000FEFDC868
1198 x26 :0x00000000FEFDC86A
1199 x27 :0x00000000019EDEDC
1200 x28 :0x000000000A7CFDAA
1201 x29 :0x0000000004010780
1202 x30 :0x000000000400F004
1203 scr_el3 :0x0000000000000D3D
1204 sctlr_el3 :0x0000000000C8181F
1205 cptr_el3 :0x0000000000000000
1206 tcr_el3 :0x0000000080803520
1207 daif :0x00000000000003C0
1208 mair_el3 :0x00000000000004FF
1209 spsr_el3 :0x00000000800003CC
1210 elr_el3 :0x000000000400C0CC
1211 ttbr0_el3 :0x00000000040172A0
1212 esr_el3 :0x0000000096000210
1213 sp_el3 :0x0000000004014D50
1214 far_el3 :0x000000004F00007C
1215 spsr_el1 :0x0000000000000000
1216 elr_el1 :0x0000000000000000
1217 spsr_abt :0x0000000000000000
1218 spsr_und :0x0000000000000000
1219 spsr_irq :0x0000000000000000
1220 spsr_fiq :0x0000000000000000
1221 sctlr_el1 :0x0000000030C81807
1222 actlr_el1 :0x0000000000000000
1223 cpacr_el1 :0x0000000000300000
1224 csselr_el1 :0x0000000000000002
1225 sp_el1 :0x0000000004028800
1226 esr_el1 :0x0000000000000000
1227 ttbr0_el1 :0x000000000402C200
1228 ttbr1_el1 :0x0000000000000000
1229 mair_el1 :0x00000000000004FF
1230 amair_el1 :0x0000000000000000
1231 tcr_el1 :0x0000000000003520
1232 tpidr_el1 :0x0000000000000000
1233 tpidr_el0 :0x0000000000000000
1234 tpidrro_el0 :0x0000000000000000
1235 dacr32_el2 :0x0000000000000000
1236 ifsr32_el2 :0x0000000000000000
1237 par_el1 :0x0000000000000000
1238 far_el1 :0x0000000000000000
1239 afsr0_el1 :0x0000000000000000
1240 afsr1_el1 :0x0000000000000000
1241 contextidr_el1 :0x0000000000000000
1242 vbar_el1 :0x0000000004027000
1243 cntp_ctl_el0 :0x0000000000000000
1244 cntp_cval_el0 :0x0000000000000000
1245 cntv_ctl_el0 :0x0000000000000000
1246 cntv_cval_el0 :0x0000000000000000
1247 cntkctl_el1 :0x0000000000000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001248 sp_el0 :0x0000000004010780
1249
1250Guidelines for Reset Handlers
1251-----------------------------
1252
Dan Handley610e7e12018-03-01 18:44:00 +00001253TF-A implements a framework that allows CPU and platform ports to perform
1254actions very early after a CPU is released from reset in both the cold and warm
1255boot paths. This is done by calling the ``reset_handler()`` function in both
1256the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
1257handling functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001258
1259Details for implementing a CPU specific reset handler can be found in
1260Section 8. Details for implementing a platform specific reset handler can be
1261found in the `Porting Guide`_ (see the ``plat_reset_handler()`` function).
1262
1263When adding functionality to a reset handler, keep in mind that if a different
1264reset handling behavior is required between the first and the subsequent
1265invocations of the reset handling code, this should be detected at runtime.
1266In other words, the reset handler should be able to detect whether an action has
1267already been performed and act as appropriate. Possible courses of actions are,
1268e.g. skip the action the second time, or undo/redo it.
1269
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001270Configuring secure interrupts
1271-----------------------------
1272
1273The GIC driver is responsible for performing initial configuration of secure
1274interrupts on the platform. To this end, the platform is expected to provide the
1275GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1276interrupt configuration during the driver initialisation.
1277
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001278Secure interrupt configuration are specified in an array of secure interrupt
1279properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
1280``interrupt_props`` member points to an array of interrupt properties. Each
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001281element of the array specifies the interrupt number and its attributes
1282(priority, group, configuration). Each element of the array shall be populated
1283by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001284
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001285- 10-bit interrupt number,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001286
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001287- 8-bit interrupt priority,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001288
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001289- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1290 ``INTR_TYPE_NS``),
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001291
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001292- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1293 ``GIC_INTR_CFG_EDGE``).
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001294
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001295CPU specific operations framework
1296---------------------------------
1297
Dan Handley610e7e12018-03-01 18:44:00 +00001298Certain aspects of the Armv8-A architecture are implementation defined,
1299that is, certain behaviours are not architecturally defined, but must be
1300defined and documented by individual processor implementations. TF-A
1301implements a framework which categorises the common implementation defined
1302behaviours and allows a processor to export its implementation of that
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001303behaviour. The categories are:
1304
1305#. Processor specific reset sequence.
1306
1307#. Processor specific power down sequences.
1308
1309#. Processor specific register dumping as a part of crash reporting.
1310
1311#. Errata status reporting.
1312
1313Each of the above categories fulfils a different requirement.
1314
1315#. allows any processor specific initialization before the caches and MMU
1316 are turned on, like implementation of errata workarounds, entry into
1317 the intra-cluster coherency domain etc.
1318
1319#. allows each processor to implement the power down sequence mandated in
1320 its Technical Reference Manual (TRM).
1321
1322#. allows a processor to provide additional information to the developer
1323 in the event of a crash, for example Cortex-A53 has registers which
1324 can expose the data cache contents.
1325
1326#. allows a processor to define a function that inspects and reports the status
1327 of all errata workarounds on that processor.
1328
1329Please note that only 2. is mandated by the TRM.
1330
1331The CPU specific operations framework scales to accommodate a large number of
1332different CPUs during power down and reset handling. The platform can specify
1333any CPU optimization it wants to enable for each CPU. It can also specify
1334the CPU errata workarounds to be applied for each CPU type during reset
1335handling by defining CPU errata compile time macros. Details on these macros
John Tsichritzis2fd3d922019-05-28 13:13:39 +01001336can be found in `CPU specific build macros`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001337
1338The CPU specific operations framework depends on the ``cpu_ops`` structure which
1339needs to be exported for each type of CPU in the platform. It is defined in
1340``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1341``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1342``cpu_reg_dump()``.
1343
1344The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1345suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1346exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1347configuration, these CPU specific files must be included in the build by
1348the platform makefile. The generic CPU specific operations framework code exists
1349in ``lib/cpus/aarch64/cpu_helpers.S``.
1350
1351CPU specific Reset Handling
1352~~~~~~~~~~~~~~~~~~~~~~~~~~~
1353
1354After a reset, the state of the CPU when it calls generic reset handler is:
1355MMU turned off, both instruction and data caches turned off and not part
1356of any coherency domain.
1357
1358The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1359the platform to perform any system initialization required and any system
1360errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1361the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1362array and returns it. Note that only the part number and implementer fields
1363in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1364the returned ``cpu_ops`` is then invoked which executes the required reset
1365handling for that CPU and also any errata workarounds enabled by the platform.
1366This function must preserve the values of general purpose registers x20 to x29.
1367
1368Refer to Section "Guidelines for Reset Handlers" for general guidelines
1369regarding placement of code in a reset handler.
1370
1371CPU specific power down sequence
1372~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1373
1374During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1375entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1376retrieved during power down sequences.
1377
1378Various CPU drivers register handlers to perform power down at certain power
1379levels for that specific CPU. The PSCI service, upon receiving a power down
1380request, determines the highest power level at which to execute power down
1381sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1382pick the right power down handler for the requested level. The function
1383retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1384retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1385requested power level is higher than what a CPU driver supports, the handler
1386registered for highest level is invoked.
1387
1388At runtime the platform hooks for power down are invoked by the PSCI service to
1389perform platform specific operations during a power down sequence, for example
1390turning off CCI coherency during a cluster power down.
1391
1392CPU specific register reporting during crash
1393~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1394
1395If the crash reporting is enabled in BL31, when a crash occurs, the crash
1396reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1397``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1398``cpu_ops`` is invoked, which then returns the CPU specific register values to
1399be reported and a pointer to the ASCII list of register names in a format
1400expected by the crash reporting framework.
1401
1402CPU errata status reporting
1403~~~~~~~~~~~~~~~~~~~~~~~~~~~
1404
Dan Handley610e7e12018-03-01 18:44:00 +00001405Errata workarounds for CPUs supported in TF-A are applied during both cold and
1406warm boots, shortly after reset. Individual Errata workarounds are enabled as
1407build options. Some errata workarounds have potential run-time implications;
1408therefore some are enabled by default, others not. Platform ports shall
1409override build options to enable or disable errata as appropriate. The CPU
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001410drivers take care of applying errata workarounds that are enabled and applicable
1411to a given CPU. Refer to the section titled *CPU Errata Workarounds* in `CPUBM`_
1412for more information.
1413
1414Functions in CPU drivers that apply errata workaround must follow the
1415conventions listed below.
1416
1417The errata workaround must be authored as two separate functions:
1418
1419- One that checks for errata. This function must determine whether that errata
1420 applies to the current CPU. Typically this involves matching the current
1421 CPUs revision and variant against a value that's known to be affected by the
1422 errata. If the function determines that the errata applies to this CPU, it
1423 must return ``ERRATA_APPLIES``; otherwise, it must return
1424 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and
1425 ``cpu_rev_var_ls`` functions may come in handy for this purpose.
1426
1427For an errata identified as ``E``, the check function must be named
1428``check_errata_E``.
1429
1430This function will be invoked at different times, both from assembly and from
1431C run time. Therefore it must follow AAPCS, and must not use stack.
1432
1433- Another one that applies the errata workaround. This function would call the
1434 check function described above, and applies errata workaround if required.
1435
1436CPU drivers that apply errata workaround can optionally implement an assembly
1437function that report the status of errata workarounds pertaining to that CPU.
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001438For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001439macro, the errata reporting function, if it exists, must be named
1440``cpux_errata_report``. This function will always be called with MMU enabled; it
1441must follow AAPCS and may use stack.
1442
Dan Handley610e7e12018-03-01 18:44:00 +00001443In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the
1444runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata
1445status reporting function, if one exists, for that type of CPU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001446
1447To report the status of each errata workaround, the function shall use the
1448assembler macro ``report_errata``, passing it:
1449
1450- The build option that enables the errata;
1451
1452- The name of the CPU: this must be the same identifier that CPU driver
1453 registered itself with, using ``declare_cpu_ops``;
1454
1455- And the errata identifier: the identifier must match what's used in the
1456 errata's check function described above.
1457
1458The errata status reporting function will be called once per CPU type/errata
1459combination during the software's active life time.
1460
Dan Handley610e7e12018-03-01 18:44:00 +00001461It's expected that whenever an errata workaround is submitted to TF-A, the
1462errata reporting function is appropriately extended to report its status as
1463well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001464
1465Reporting the status of errata workaround is for informational purpose only; it
1466has no functional significance.
1467
1468Memory layout of BL images
1469--------------------------
1470
1471Each bootloader image can be divided in 2 parts:
1472
1473- the static contents of the image. These are data actually stored in the
1474 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1475 sections;
1476
1477- the run-time contents of the image. These are data that don't occupy any
1478 space in the binary on the disk. The ELF binary just contains some
1479 metadata indicating where these data will be stored at run-time and the
1480 corresponding sections need to be allocated and initialized at run-time.
1481 In the ELF terminology, they are called ``NOBITS`` sections.
1482
1483All PROGBITS sections are grouped together at the beginning of the image,
Dan Handley610e7e12018-03-01 18:44:00 +00001484followed by all NOBITS sections. This is true for all TF-A images and it is
1485governed by the linker scripts. This ensures that the raw binary images are
1486as small as possible. If a NOBITS section was inserted in between PROGBITS
1487sections then the resulting binary file would contain zero bytes in place of
1488this NOBITS section, making the image unnecessarily bigger. Smaller images
1489allow faster loading from the FIP to the main memory.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001490
1491Linker scripts and symbols
1492~~~~~~~~~~~~~~~~~~~~~~~~~~
1493
1494Each bootloader stage image layout is described by its own linker script. The
1495linker scripts export some symbols into the program symbol table. Their values
Dan Handley610e7e12018-03-01 18:44:00 +00001496correspond to particular addresses. TF-A code can refer to these symbols to
1497figure out the image memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001498
Dan Handley610e7e12018-03-01 18:44:00 +00001499Linker symbols follow the following naming convention in TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001500
1501- ``__<SECTION>_START__``
1502
1503 Start address of a given section named ``<SECTION>``.
1504
1505- ``__<SECTION>_END__``
1506
1507 End address of a given section named ``<SECTION>``. If there is an alignment
1508 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1509 to the end address of the section's actual contents, rounded up to the right
1510 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1511 actual end address of the section's contents.
1512
1513- ``__<SECTION>_UNALIGNED_END__``
1514
1515 End address of a given section named ``<SECTION>`` without any padding or
1516 rounding up due to some alignment constraint.
1517
1518- ``__<SECTION>_SIZE__``
1519
1520 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1521 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1522 corresponds to the size of the section's actual contents, rounded up to the
1523 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1524 to know the actual size of the section's contents.
1525
1526- ``__<SECTION>_UNALIGNED_SIZE__``
1527
1528 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1529 rounding up due to some alignment constraint. In other words,
1530 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``.
1531
Dan Handley610e7e12018-03-01 18:44:00 +00001532Some of the linker symbols are mandatory as TF-A code relies on them to be
1533defined. They are listed in the following subsections. Some of them must be
1534provided for each bootloader stage and some are specific to a given bootloader
1535stage.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001536
1537The linker scripts define some extra, optional symbols. They are not actually
1538used by any code but they help in understanding the bootloader images' memory
1539layout as they are easy to spot in the link map files.
1540
1541Common linker symbols
1542^^^^^^^^^^^^^^^^^^^^^
1543
1544All BL images share the following requirements:
1545
1546- The BSS section must be zero-initialised before executing any C code.
1547- The coherent memory section (if enabled) must be zero-initialised as well.
1548- The MMU setup code needs to know the extents of the coherent and read-only
1549 memory regions to set the right memory attributes. When
1550 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1551 read-only memory region is divided between code and data.
1552
1553The following linker symbols are defined for this purpose:
1554
1555- ``__BSS_START__``
1556- ``__BSS_SIZE__``
1557- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1558- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1559- ``__COHERENT_RAM_UNALIGNED_SIZE__``
1560- ``__RO_START__``
1561- ``__RO_END__``
1562- ``__TEXT_START__``
1563- ``__TEXT_END__``
1564- ``__RODATA_START__``
1565- ``__RODATA_END__``
1566
1567BL1's linker symbols
1568^^^^^^^^^^^^^^^^^^^^
1569
1570BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1571it is entirely executed in place but it needs some read-write memory for its
1572mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1573relocated from ROM to RAM before executing any C code.
1574
1575The following additional linker symbols are defined for BL1:
1576
1577- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1578 and ``.data`` section in ROM.
1579- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1580 aligned on a 16-byte boundary.
1581- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1582 copied over. Must be aligned on a 16-byte boundary.
1583- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1584- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1585- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1586
1587How to choose the right base addresses for each bootloader stage image
1588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1589
Dan Handley610e7e12018-03-01 18:44:00 +00001590There is currently no support for dynamic image loading in TF-A. This means
1591that all bootloader images need to be linked against their ultimate runtime
1592locations and the base addresses of each image must be chosen carefully such
1593that images don't overlap each other in an undesired way. As the code grows,
1594the base addresses might need adjustments to cope with the new memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001595
1596The memory layout is completely specific to the platform and so there is no
1597general recipe for choosing the right base addresses for each bootloader image.
1598However, there are tools to aid in understanding the memory layout. These are
1599the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1600being the stage bootloader. They provide a detailed view of the memory usage of
1601each image. Among other useful information, they provide the end address of
1602each image.
1603
1604- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address.
1605- ``bl2.map`` link map file provides ``__BL2_END__`` address.
1606- ``bl31.map`` link map file provides ``__BL31_END__`` address.
1607- ``bl32.map`` link map file provides ``__BL32_END__`` address.
1608
1609For each bootloader image, the platform code must provide its start address
1610as well as a limit address that it must not overstep. The latter is used in the
1611linker scripts to check that the image doesn't grow past that address. If that
1612happens, the linker will issue a message similar to the following:
1613
1614::
1615
1616 aarch64-none-elf-ld: BLx has exceeded its limit.
1617
1618Additionally, if the platform memory layout implies some image overlaying like
1619on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1620sections must not overstep. The platform code must provide those.
1621
Soby Mathew97b1bff2018-09-27 16:46:41 +01001622TF-A does not provide any mechanism to verify at boot time that the memory
1623to load a new image is free to prevent overwriting a previously loaded image.
1624The platform must specify the memory available in the system for all the
1625relevant BL images to be loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001626
1627For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1628return the region defined by the platform where BL1 intends to load BL2. The
1629``load_image()`` function performs bounds check for the image size based on the
1630base and maximum image size provided by the platforms. Platforms must take
1631this behaviour into account when defining the base/size for each of the images.
1632
Dan Handley610e7e12018-03-01 18:44:00 +00001633Memory layout on Arm development platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001634^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1635
Dan Handley610e7e12018-03-01 18:44:00 +00001636The following list describes the memory layout on the Arm development platforms:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001637
1638- A 4KB page of shared memory is used for communication between Trusted
1639 Firmware and the platform's power controller. This is located at the base of
1640 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1641 images is reduced by the size of the shared memory.
1642
1643 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1644 this is also used for the MHU payload when passing messages to and from the
1645 SCP.
1646
Soby Mathew492e2452018-06-06 16:03:10 +01001647- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
1648 and also the dynamic firmware configurations.
1649
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001650- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1651 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1652 data are relocated to the top of Trusted SRAM at runtime.
1653
Soby Mathew492e2452018-06-06 16:03:10 +01001654- BL2 is loaded below BL1 RW
1655
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001656- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN),
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001657 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
Soby Mathew492e2452018-06-06 16:03:10 +01001658 overwrite BL1 R/W data and BL2. This implies that BL1 global variables
1659 remain valid only until execution reaches the EL3 Runtime Software entry
1660 point during a cold boot.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001661
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001662- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001663 region and transfered to the SCP before being overwritten by EL3 Runtime
1664 Software.
1665
1666- BL32 (for AArch64) can be loaded in one of the following locations:
1667
1668 - Trusted SRAM
1669 - Trusted DRAM (FVP only)
1670 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1671 controller)
1672
Soby Mathew492e2452018-06-06 16:03:10 +01001673 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
1674 BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001675
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001676The location of the BL32 image will result in different memory maps. This is
1677illustrated for both FVP and Juno in the following diagrams, using the TSP as
1678an example.
1679
Paul Beesleyba3ed402019-03-13 16:20:44 +00001680.. note::
1681 Loading the BL32 image in TZC secured DRAM doesn't change the memory
1682 layout of the other images in Trusted SRAM.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001683
Sathees Balya90950092018-11-15 14:22:30 +00001684CONFIG section in memory layouts shown below contains:
1685
1686::
1687
1688 +--------------------+
1689 |bl2_mem_params_descs|
1690 |--------------------|
1691 | fw_configs |
1692 +--------------------+
1693
1694``bl2_mem_params_descs`` contains parameters passed from BL2 to next the
1695BL image during boot.
1696
1697``fw_configs`` includes soc_fw_config, tos_fw_config and tb_fw_config.
1698
Soby Mathew492e2452018-06-06 16:03:10 +01001699**FVP with TSP in Trusted SRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001700(These diagrams only cover the AArch64 case)
1701
1702::
1703
Soby Mathew492e2452018-06-06 16:03:10 +01001704 DRAM
1705 0xffffffff +----------+
1706 : :
1707 |----------|
1708 |HW_CONFIG |
1709 0x83000000 |----------| (non-secure)
1710 | |
1711 0x80000000 +----------+
1712
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001713 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001714 0x04040000 +----------+ loaded by BL2 +----------------+
1715 | BL1 (rw) | <<<<<<<<<<<<< | |
1716 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1717 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001718 |----------| <<<<<<<<<<<<< |----------------|
1719 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001720 | | <<<<<<<<<<<<< |----------------|
1721 | | <<<<<<<<<<<<< | BL32 |
1722 0x04002000 +----------+ +----------------+
Sathees Balya90950092018-11-15 14:22:30 +00001723 | CONFIG |
Soby Mathew492e2452018-06-06 16:03:10 +01001724 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001725 | Shared |
1726 0x04000000 +----------+
1727
1728 Trusted ROM
1729 0x04000000 +----------+
1730 | BL1 (ro) |
1731 0x00000000 +----------+
1732
Soby Mathew492e2452018-06-06 16:03:10 +01001733**FVP with TSP in Trusted DRAM with firmware configs (default option):**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001734
1735::
1736
Soby Mathewb1bf0442018-02-16 14:52:52 +00001737 DRAM
1738 0xffffffff +--------------+
1739 : :
1740 |--------------|
1741 | HW_CONFIG |
1742 0x83000000 |--------------| (non-secure)
1743 | |
1744 0x80000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001745
Soby Mathewb1bf0442018-02-16 14:52:52 +00001746 Trusted DRAM
1747 0x08000000 +--------------+
1748 | BL32 |
1749 0x06000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001750
Soby Mathewb1bf0442018-02-16 14:52:52 +00001751 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001752 0x04040000 +--------------+ loaded by BL2 +----------------+
1753 | BL1 (rw) | <<<<<<<<<<<<< | |
1754 |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
1755 | BL2 | <<<<<<<<<<<<< | |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001756 |--------------| <<<<<<<<<<<<< |----------------|
1757 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001758 | | +----------------+
1759 +--------------+
Sathees Balya90950092018-11-15 14:22:30 +00001760 | CONFIG |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001761 0x04001000 +--------------+
1762 | Shared |
1763 0x04000000 +--------------+
1764
1765 Trusted ROM
1766 0x04000000 +--------------+
1767 | BL1 (ro) |
1768 0x00000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001769
Soby Mathew492e2452018-06-06 16:03:10 +01001770**FVP with TSP in TZC-Secured DRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771
1772::
1773
1774 DRAM
1775 0xffffffff +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001776 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001777 0xff000000 +----------+
1778 | |
Soby Mathew492e2452018-06-06 16:03:10 +01001779 |----------|
1780 |HW_CONFIG |
1781 0x83000000 |----------| (non-secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001782 | |
1783 0x80000000 +----------+
1784
1785 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001786 0x04040000 +----------+ loaded by BL2 +----------------+
1787 | BL1 (rw) | <<<<<<<<<<<<< | |
1788 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1789 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001790 |----------| <<<<<<<<<<<<< |----------------|
1791 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001792 | | +----------------+
1793 0x04002000 +----------+
Sathees Balya90950092018-11-15 14:22:30 +00001794 | CONFIG |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001795 0x04001000 +----------+
1796 | Shared |
1797 0x04000000 +----------+
1798
1799 Trusted ROM
1800 0x04000000 +----------+
1801 | BL1 (ro) |
1802 0x00000000 +----------+
1803
Soby Mathew492e2452018-06-06 16:03:10 +01001804**Juno with BL32 in Trusted SRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001805
1806::
1807
1808 Flash0
1809 0x0C000000 +----------+
1810 : :
1811 0x0BED0000 |----------|
1812 | BL1 (ro) |
1813 0x0BEC0000 |----------|
1814 : :
1815 0x08000000 +----------+ BL31 is loaded
1816 after SCP_BL2 has
1817 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001818 0x04040000 +----------+ loaded by BL2 +----------------+
1819 | BL1 (rw) | <<<<<<<<<<<<< | |
1820 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1821 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001822 |----------| <<<<<<<<<<<<< |----------------|
1823 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001824 |----------| <<<<<<<<<<<<< |----------------|
Soby Mathew492e2452018-06-06 16:03:10 +01001825 | | <<<<<<<<<<<<< | BL32 |
1826 | | +----------------+
1827 | |
1828 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001829 | MHU |
1830 0x04000000 +----------+
1831
Soby Mathew492e2452018-06-06 16:03:10 +01001832**Juno with BL32 in TZC-secured DRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001833
1834::
1835
1836 DRAM
1837 0xFFE00000 +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001838 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001839 0xFF000000 |----------|
1840 | |
1841 : : (non-secure)
1842 | |
1843 0x80000000 +----------+
1844
1845 Flash0
1846 0x0C000000 +----------+
1847 : :
1848 0x0BED0000 |----------|
1849 | BL1 (ro) |
1850 0x0BEC0000 |----------|
1851 : :
1852 0x08000000 +----------+ BL31 is loaded
1853 after SCP_BL2 has
1854 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001855 0x04040000 +----------+ loaded by BL2 +----------------+
1856 | BL1 (rw) | <<<<<<<<<<<<< | |
1857 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1858 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001859 |----------| <<<<<<<<<<<<< |----------------|
1860 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001861 |----------| +----------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001862 0x04001000 +----------+
1863 | MHU |
1864 0x04000000 +----------+
1865
Sathees Balya17d8eed2019-01-30 15:56:44 +00001866Library at ROM
1867---------------
1868
1869Please refer to the `ROMLIB Design`_ document.
1870
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001871Firmware Image Package (FIP)
1872----------------------------
1873
1874Using a Firmware Image Package (FIP) allows for packing bootloader images (and
Dan Handley610e7e12018-03-01 18:44:00 +00001875potentially other payloads) into a single archive that can be loaded by TF-A
1876from non-volatile platform storage. A driver to load images from a FIP has
1877been added to the storage layer and allows a package to be read from supported
1878platform storage. A tool to create Firmware Image Packages is also provided
1879and described below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001880
1881Firmware Image Package layout
1882~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1883
1884The FIP layout consists of a table of contents (ToC) followed by payload data.
1885The ToC itself has a header followed by one or more table entries. The ToC is
Jett Zhou75566102017-11-24 16:03:58 +08001886terminated by an end marker entry, and since the size of the ToC is 0 bytes,
1887the offset equals the total size of the FIP file. All ToC entries describe some
1888payload data that has been appended to the end of the binary package. With the
1889information provided in the ToC entry the corresponding payload data can be
1890retrieved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001891
1892::
1893
1894 ------------------
1895 | ToC Header |
1896 |----------------|
1897 | ToC Entry 0 |
1898 |----------------|
1899 | ToC Entry 1 |
1900 |----------------|
1901 | ToC End Marker |
1902 |----------------|
1903 | |
1904 | Data 0 |
1905 | |
1906 |----------------|
1907 | |
1908 | Data 1 |
1909 | |
1910 ------------------
1911
1912The ToC header and entry formats are described in the header file
1913``include/tools_share/firmware_image_package.h``. This file is used by both the
Dan Handley610e7e12018-03-01 18:44:00 +00001914tool and TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001915
1916The ToC header has the following fields:
1917
1918::
1919
1920 `name`: The name of the ToC. This is currently used to validate the header.
1921 `serial_number`: A non-zero number provided by the creation tool
1922 `flags`: Flags associated with this data.
1923 Bits 0-31: Reserved
1924 Bits 32-47: Platform defined
1925 Bits 48-63: Reserved
1926
1927A ToC entry has the following fields:
1928
1929::
1930
1931 `uuid`: All files are referred to by a pre-defined Universally Unique
1932 IDentifier [UUID] . The UUIDs are defined in
1933 `include/tools_share/firmware_image_package.h`. The platform translates
1934 the requested image name into the corresponding UUID when accessing the
1935 package.
1936 `offset_address`: The offset address at which the corresponding payload data
1937 can be found. The offset is calculated from the ToC base address.
1938 `size`: The size of the corresponding payload data in bytes.
Etienne Carriere7421bf12017-08-23 15:43:33 +02001939 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001940
1941Firmware Image Package creation tool
1942~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1943
Dan Handley610e7e12018-03-01 18:44:00 +00001944The FIP creation tool can be used to pack specified images into a binary
1945package that can be loaded by TF-A from platform storage. The tool currently
1946only supports packing bootloader images. Additional image definitions can be
1947added to the tool as required.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001948
1949The tool can be found in ``tools/fiptool``.
1950
1951Loading from a Firmware Image Package (FIP)
1952~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1953
1954The Firmware Image Package (FIP) driver can load images from a binary package on
Dan Handley610e7e12018-03-01 18:44:00 +00001955non-volatile platform storage. For the Arm development platforms, this is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001956currently NOR FLASH.
1957
1958Bootloader images are loaded according to the platform policy as specified by
Dan Handley610e7e12018-03-01 18:44:00 +00001959the function ``plat_get_image_source()``. For the Arm development platforms, this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001960means the platform will attempt to load images from a Firmware Image Package
1961located at the start of NOR FLASH0.
1962
Dan Handley610e7e12018-03-01 18:44:00 +00001963The Arm development platforms' policy is to only allow loading of a known set of
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001964images. The platform policy can be modified to allow additional images.
1965
Dan Handley610e7e12018-03-01 18:44:00 +00001966Use of coherent memory in TF-A
1967------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001968
1969There might be loss of coherency when physical memory with mismatched
1970shareability, cacheability and memory attributes is accessed by multiple CPUs
Dan Handley610e7e12018-03-01 18:44:00 +00001971(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs
1972in TF-A during power up/down sequences when coherency, MMU and caches are
1973turned on/off incrementally.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001974
Dan Handley610e7e12018-03-01 18:44:00 +00001975TF-A defines coherent memory as a region of memory with Device nGnRE attributes
1976in the translation tables. The translation granule size in TF-A is 4KB. This
1977is the smallest possible size of the coherent memory region.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001978
1979By default, all data structures which are susceptible to accesses with
1980mismatched attributes from various CPUs are allocated in a coherent memory
1981region (refer to section 2.1 of `Porting Guide`_). The coherent memory region
1982accesses are Outer Shareable, non-cacheable and they can be accessed
1983with the Device nGnRE attributes when the MMU is turned on. Hence, at the
Dan Handley610e7e12018-03-01 18:44:00 +00001984expense of at least an extra page of memory, TF-A is able to work around
1985coherency issues due to mismatched memory attributes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001986
1987The alternative to the above approach is to allocate the susceptible data
1988structures in Normal WriteBack WriteAllocate Inner shareable memory. This
1989approach requires the data structures to be designed so that it is possible to
1990work around the issue of mismatched memory attributes by performing software
1991cache maintenance on them.
1992
Dan Handley610e7e12018-03-01 18:44:00 +00001993Disabling the use of coherent memory in TF-A
1994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001995
1996It might be desirable to avoid the cost of allocating coherent memory on
Dan Handley610e7e12018-03-01 18:44:00 +00001997platforms which are memory constrained. TF-A enables inclusion of coherent
1998memory in firmware images through the build flag ``USE_COHERENT_MEM``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001999This flag is enabled by default. It can be disabled to choose the second
2000approach described above.
2001
2002The below sections analyze the data structures allocated in the coherent memory
2003region and the changes required to allocate them in normal memory.
2004
2005Coherent memory usage in PSCI implementation
2006~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2007
2008The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2009tree information for state management of power domains. By default, this data
Dan Handley610e7e12018-03-01 18:44:00 +00002010structure is allocated in the coherent memory region in TF-A because it can be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002011accessed by multiple CPUs, either with caches enabled or disabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002012
2013.. code:: c
2014
2015 typedef struct non_cpu_pwr_domain_node {
2016 /*
2017 * Index of the first CPU power domain node level 0 which has this node
2018 * as its parent.
2019 */
2020 unsigned int cpu_start_idx;
2021
2022 /*
2023 * Number of CPU power domains which are siblings of the domain indexed
2024 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2025 * -> cpu_start_idx + ncpus' have this node as their parent.
2026 */
2027 unsigned int ncpus;
2028
2029 /*
2030 * Index of the parent power domain node.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002031 */
2032 unsigned int parent_node;
2033
2034 plat_local_state_t local_state;
2035
2036 unsigned char level;
2037
2038 /* For indexing the psci_lock array*/
2039 unsigned char lock_index;
2040 } non_cpu_pd_node_t;
2041
2042In order to move this data structure to normal memory, the use of each of its
2043fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2044``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2045them from coherent memory involves only doing a clean and invalidate of the
2046cache lines after these fields are written.
2047
2048The field ``local_state`` can be concurrently accessed by multiple CPUs in
2049different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002050mutual exclusion to this field and a clean and invalidate is needed after it
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002051is written.
2052
2053Bakery lock data
2054~~~~~~~~~~~~~~~~
2055
2056The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2057and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2058defined as follows:
2059
2060.. code:: c
2061
2062 typedef struct bakery_lock {
2063 /*
2064 * The lock_data is a bit-field of 2 members:
2065 * Bit[0] : choosing. This field is set when the CPU is
2066 * choosing its bakery number.
2067 * Bits[1 - 15] : number. This is the bakery number allocated.
2068 */
2069 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2070 } bakery_lock_t;
2071
2072It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2073fields can be read by all CPUs but only written to by the owning CPU.
2074
2075Depending upon the data cache line size, the per-CPU fields of the
2076``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2077These per-CPU fields can be read and written during lock contention by multiple
2078CPUs with mismatched memory attributes. Since these fields are a part of the
2079lock implementation, they do not have access to any other locking primitive to
2080safeguard against the resulting coherency issues. As a result, simple software
2081cache maintenance is not enough to allocate them in coherent memory. Consider
2082the following example.
2083
2084CPU0 updates its per-CPU field with data cache enabled. This write updates a
2085local cache line which contains a copy of the fields for other CPUs as well. Now
2086CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2087disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2088its field in any other cache line in the system. This operation will invalidate
2089the update made by CPU0 as well.
2090
2091To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2092has been redesigned. The changes utilise the characteristic of Lamport's Bakery
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002093algorithm mentioned earlier. The bakery_lock structure only allocates the memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002094for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2095needed for a CPU into a section ``bakery_lock``. The linker allocates the memory
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002096for other cores by using the total size allocated for the bakery_lock section
2097and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002098perform software cache maintenance on the lock data structure without running
2099into coherency issues associated with mismatched attributes.
2100
2101The bakery lock data structure ``bakery_info_t`` is defined for use when
2102``USE_COHERENT_MEM`` is disabled as follows:
2103
2104.. code:: c
2105
2106 typedef struct bakery_info {
2107 /*
2108 * The lock_data is a bit-field of 2 members:
2109 * Bit[0] : choosing. This field is set when the CPU is
2110 * choosing its bakery number.
2111 * Bits[1 - 15] : number. This is the bakery number allocated.
2112 */
2113 volatile uint16_t lock_data;
2114 } bakery_info_t;
2115
2116The ``bakery_info_t`` represents a single per-CPU field of one lock and
2117the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2118system represents the complete bakery lock. The view in memory for a system
2119with n bakery locks are:
2120
2121::
2122
2123 bakery_lock section start
2124 |----------------|
2125 | `bakery_info_t`| <-- Lock_0 per-CPU field
2126 | Lock_0 | for CPU0
2127 |----------------|
2128 | `bakery_info_t`| <-- Lock_1 per-CPU field
2129 | Lock_1 | for CPU0
2130 |----------------|
2131 | .... |
2132 |----------------|
2133 | `bakery_info_t`| <-- Lock_N per-CPU field
2134 | Lock_N | for CPU0
2135 ------------------
2136 | XXXXX |
2137 | Padding to |
2138 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2139 | Granule | continuous memory for remaining CPUs.
2140 ------------------
2141 | `bakery_info_t`| <-- Lock_0 per-CPU field
2142 | Lock_0 | for CPU1
2143 |----------------|
2144 | `bakery_info_t`| <-- Lock_1 per-CPU field
2145 | Lock_1 | for CPU1
2146 |----------------|
2147 | .... |
2148 |----------------|
2149 | `bakery_info_t`| <-- Lock_N per-CPU field
2150 | Lock_N | for CPU1
2151 ------------------
2152 | XXXXX |
2153 | Padding to |
2154 | next Cache WB |
2155 | Granule |
2156 ------------------
2157
2158Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002159operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002160``bakery_lock`` section need to be fetched and appropriate cache operations need
2161to be performed for each access.
2162
Dan Handley610e7e12018-03-01 18:44:00 +00002163On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002164driver (``arm_lock``).
2165
2166Non Functional Impact of removing coherent memory
2167~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2168
2169Removal of the coherent memory region leads to the additional software overhead
2170of performing cache maintenance for the affected data structures. However, since
2171the memory where the data structures are allocated is cacheable, the overhead is
2172mostly mitigated by an increase in performance.
2173
2174There is however a performance impact for bakery locks, due to:
2175
2176- Additional cache maintenance operations, and
2177- Multiple cache line reads for each lock operation, since the bakery locks
2178 for each CPU are distributed across different cache lines.
2179
2180The implementation has been optimized to minimize this additional overhead.
2181Measurements indicate that when bakery locks are allocated in Normal memory, the
2182minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2183in Device memory the same is 2 micro seconds. The measurements were done on the
Dan Handley610e7e12018-03-01 18:44:00 +00002184Juno Arm development platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002185
2186As mentioned earlier, almost a page of memory can be saved by disabling
2187``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2188whether coherent memory should be used. If a platform disables
2189``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2190optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
2191`Porting Guide`_). Refer to the reference platform code for examples.
2192
2193Isolating code and read-only data on separate memory pages
2194----------------------------------------------------------
2195
Dan Handley610e7e12018-03-01 18:44:00 +00002196In the Armv8-A VMSA, translation table entries include fields that define the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002197properties of the target memory region, such as its access permissions. The
2198smallest unit of memory that can be addressed by a translation table entry is
2199a memory page. Therefore, if software needs to set different permissions on two
2200memory regions then it needs to map them using different memory pages.
2201
2202The default memory layout for each BL image is as follows:
2203
2204::
2205
2206 | ... |
2207 +-------------------+
2208 | Read-write data |
2209 +-------------------+ Page boundary
2210 | <Padding> |
2211 +-------------------+
2212 | Exception vectors |
2213 +-------------------+ 2 KB boundary
2214 | <Padding> |
2215 +-------------------+
2216 | Read-only data |
2217 +-------------------+
2218 | Code |
2219 +-------------------+ BLx_BASE
2220
Paul Beesleyba3ed402019-03-13 16:20:44 +00002221.. note::
2222 The 2KB alignment for the exception vectors is an architectural
2223 requirement.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002224
2225The read-write data start on a new memory page so that they can be mapped with
2226read-write permissions, whereas the code and read-only data below are configured
2227as read-only.
2228
2229However, the read-only data are not aligned on a page boundary. They are
2230contiguous to the code. Therefore, the end of the code section and the beginning
2231of the read-only data one might share a memory page. This forces both to be
2232mapped with the same memory attributes. As the code needs to be executable, this
2233means that the read-only data stored on the same memory page as the code are
2234executable as well. This could potentially be exploited as part of a security
2235attack.
2236
2237TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2238read-only data on separate memory pages. This in turn allows independent control
2239of the access permissions for the code and read-only data. In this case,
2240platform code gets a finer-grained view of the image layout and can
2241appropriately map the code region as executable and the read-only data as
2242execute-never.
2243
2244This has an impact on memory footprint, as padding bytes need to be introduced
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002245between the code and read-only data to ensure the segregation of the two. To
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002246limit the memory cost, this flag also changes the memory layout such that the
2247code and exception vectors are now contiguous, like so:
2248
2249::
2250
2251 | ... |
2252 +-------------------+
2253 | Read-write data |
2254 +-------------------+ Page boundary
2255 | <Padding> |
2256 +-------------------+
2257 | Read-only data |
2258 +-------------------+ Page boundary
2259 | <Padding> |
2260 +-------------------+
2261 | Exception vectors |
2262 +-------------------+ 2 KB boundary
2263 | <Padding> |
2264 +-------------------+
2265 | Code |
2266 +-------------------+ BLx_BASE
2267
2268With this more condensed memory layout, the separation of read-only data will
2269add zero or one page to the memory footprint of each BL image. Each platform
2270should consider the trade-off between memory footprint and security.
2271
Dan Handley610e7e12018-03-01 18:44:00 +00002272This build flag is disabled by default, minimising memory footprint. On Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002273platforms, it is enabled.
2274
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002275Publish and Subscribe Framework
2276-------------------------------
2277
2278The Publish and Subscribe Framework allows EL3 components to define and publish
2279events, to which other EL3 components can subscribe.
2280
2281The following macros are provided by the framework:
2282
2283- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2284 the event name, which must be a valid C identifier. All calls to
2285 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2286 ``pubsub_events.h``.
2287
2288- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2289 subscribed handlers and calling them in turn. The handlers will be passed the
2290 parameter ``arg``. The expected use-case is to broadcast an event.
2291
2292- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2293 ``NULL`` is passed to subscribed handlers.
2294
2295- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2296 subscribe to ``event``. The handler will be executed whenever the ``event``
2297 is published.
2298
2299- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2300 subscribed for ``event``. ``subscriber`` must be a local variable of type
2301 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2302 iteration. This macro can be used for those patterns that none of the
2303 ``PUBLISH_EVENT_*()`` macros cover.
2304
2305Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2306result in build error. Subscribing to an undefined event however won't.
2307
2308Subscribed handlers must be of type ``pubsub_cb_t``, with following function
2309signature:
2310
Paul Beesley493e3492019-03-13 15:11:04 +00002311.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002312
2313 typedef void* (*pubsub_cb_t)(const void *arg);
2314
2315There may be arbitrary number of handlers registered to the same event. The
2316order in which subscribed handlers are notified when that event is published is
2317not defined. Subscribed handlers may be executed in any order; handlers should
2318not assume any relative ordering amongst them.
2319
2320Publishing an event on a PE will result in subscribed handlers executing on that
2321PE only; it won't cause handlers to execute on a different PE.
2322
2323Note that publishing an event on a PE blocks until all the subscribed handlers
2324finish executing on the PE.
2325
Dan Handley610e7e12018-03-01 18:44:00 +00002326TF-A generic code publishes and subscribes to some events within. Platform
2327ports are discouraged from subscribing to them. These events may be withdrawn,
2328renamed, or have their semantics altered in the future. Platforms may however
2329register, publish, and subscribe to platform-specific events.
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01002330
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002331Publish and Subscribe Example
2332~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2333
2334A publisher that wants to publish event ``foo`` would:
2335
2336- Define the event ``foo`` in the ``pubsub_events.h``.
2337
Paul Beesley493e3492019-03-13 15:11:04 +00002338 .. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002339
2340 REGISTER_PUBSUB_EVENT(foo);
2341
2342- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2343 publish the event at the appropriate path and time of execution.
2344
2345A subscriber that wants to subscribe to event ``foo`` published above would
2346implement:
2347
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002348.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002349
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002350 void *foo_handler(const void *arg)
2351 {
2352 void *result;
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002353
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002354 /* Do handling ... */
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002355
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002356 return result;
2357 }
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002358
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002359 SUBSCRIBE_TO_EVENT(foo, foo_handler);
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002360
Daniel Boulby468f0d72018-09-18 11:45:51 +01002361
2362Reclaiming the BL31 initialization code
2363~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2364
2365A significant amount of the code used for the initialization of BL31 is never
2366needed again after boot time. In order to reduce the runtime memory
2367footprint, the memory used for this code can be reclaimed after initialization
2368has finished and be used for runtime data.
2369
2370The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
2371with a ``.text.init.*`` attribute which can be filtered and placed suitably
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002372within the BL image for later reclamation by the platform. The platform can
2373specify the filter and the memory region for this init section in BL31 via the
Daniel Boulby468f0d72018-09-18 11:45:51 +01002374plat.ld.S linker script. For example, on the FVP, this section is placed
2375overlapping the secondary CPU stacks so that after the cold boot is done, this
2376memory can be reclaimed for the stacks. The init memory section is initially
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002377mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
Daniel Boulby468f0d72018-09-18 11:45:51 +01002378completed, the FVP changes the attributes of this section to ``RW``,
2379``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
2380are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
2381section section can be reclaimed for any data which is accessed after cold
2382boot initialization and it is upto the platform to make the decision.
2383
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002384Performance Measurement Framework
2385---------------------------------
2386
2387The Performance Measurement Framework (PMF) facilitates collection of
Dan Handley610e7e12018-03-01 18:44:00 +00002388timestamps by registered services and provides interfaces to retrieve them
2389from within TF-A. A platform can choose to expose appropriate SMCs to
2390retrieve these collected timestamps.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002391
2392By default, the global physical counter is used for the timestamp
2393value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2394timestamps captured by other CPUs.
2395
2396Timestamp identifier format
2397~~~~~~~~~~~~~~~~~~~~~~~~~~~
2398
2399A PMF timestamp is uniquely identified across the system via the
2400timestamp ID or ``tid``. The ``tid`` is composed as follows:
2401
2402::
2403
2404 Bits 0-7: The local timestamp identifier.
2405 Bits 8-9: Reserved.
2406 Bits 10-15: The service identifier.
2407 Bits 16-31: Reserved.
2408
2409#. The service identifier. Each PMF service is identified by a
2410 service name and a service identifier. Both the service name and
2411 identifier are unique within the system as a whole.
2412
2413#. The local timestamp identifier. This identifier is unique within a given
2414 service.
2415
2416Registering a PMF service
2417~~~~~~~~~~~~~~~~~~~~~~~~~
2418
2419To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2420is used. The arguments required are the service name, the service ID,
2421the total number of local timestamps to be captured and a set of flags.
2422
2423The ``flags`` field can be specified as a bitwise-OR of the following values:
2424
2425::
2426
2427 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2428 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2429
2430The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2431timestamps in a PMF specific linker section at build time.
2432Additionally, it defines necessary functions to capture and
2433retrieve a particular timestamp for the given service at runtime.
2434
Dan Handley610e7e12018-03-01 18:44:00 +00002435The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2436from within TF-A. In order to retrieve timestamps from outside of TF-A, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002437``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2438accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2439macro but additionally supports retrieving timestamps using SMCs.
2440
2441Capturing a timestamp
2442~~~~~~~~~~~~~~~~~~~~~
2443
2444PMF timestamps are stored in a per-service timestamp region. On a
2445system with multiple CPUs, each timestamp is captured and stored
2446in a per-CPU cache line aligned memory region.
2447
2448Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2449used to capture a timestamp at the location where it is used. The macro
2450takes the service name, a local timestamp identifier and a flag as arguments.
2451
2452The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2453instructs PMF to do cache maintenance following the capture. Cache
2454maintenance is required if any of the service's timestamps are captured
2455with data cache disabled.
2456
2457To capture a timestamp in assembly code, the caller should use
2458``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2459calculate the address of where the timestamp would be stored. The
2460caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2461and store it at the determined address for later retrieval.
2462
2463Retrieving a timestamp
2464~~~~~~~~~~~~~~~~~~~~~~
2465
Dan Handley610e7e12018-03-01 18:44:00 +00002466From within TF-A, timestamps for individual CPUs can be retrieved using either
2467``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros.
2468These macros accept the CPU's MPIDR value, or its ordinal position
2469respectively.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002470
Dan Handley610e7e12018-03-01 18:44:00 +00002471From outside TF-A, timestamps for individual CPUs can be retrieved by calling
2472into ``pmf_smc_handler()``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002473
Paul Beesley493e3492019-03-13 15:11:04 +00002474::
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002475
2476 Interface : pmf_smc_handler()
2477 Argument : unsigned int smc_fid, u_register_t x1,
2478 u_register_t x2, u_register_t x3,
2479 u_register_t x4, void *cookie,
2480 void *handle, u_register_t flags
2481 Return : uintptr_t
2482
2483 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2484 when the caller of the SMC is running in AArch32 mode
2485 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2486 x1: Timestamp identifier.
2487 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2488 This can be the `mpidr` of a different core to the one initiating
2489 the SMC. In that case, service specific cache maintenance may be
2490 required to ensure the updated copy of the timestamp is returned.
2491 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2492 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2493 cache invalidate before reading the timestamp. This ensures
2494 an updated copy is returned.
2495
2496The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2497in this implementation.
2498
2499PMF code structure
2500~~~~~~~~~~~~~~~~~~
2501
2502#. ``pmf_main.c`` consists of core functions that implement service registration,
2503 initialization, storing, dumping and retrieving timestamps.
2504
2505#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2506
2507#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2508
2509#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2510 assembly code.
2511
2512#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
2513
Dan Handley610e7e12018-03-01 18:44:00 +00002514Armv8-A Architecture Extensions
2515-------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002516
Dan Handley610e7e12018-03-01 18:44:00 +00002517TF-A makes use of Armv8-A Architecture Extensions where applicable. This
2518section lists the usage of Architecture Extensions, and build flags
2519controlling them.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002520
2521In general, and unless individually mentioned, the build options
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002522``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to
Dan Handley610e7e12018-03-01 18:44:00 +00002523target when building TF-A. Subsequent Arm Architecture Extensions are backward
2524compatible with previous versions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002525
2526The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a
2527valid numeric value. These build options only control whether or not
Dan Handley610e7e12018-03-01 18:44:00 +00002528Architecture Extension-specific code is included in the build. Otherwise, TF-A
2529targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8
2530and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002531
2532See also the *Summary of build options* in `User Guide`_.
2533
2534For details on the Architecture Extension and available features, please refer
2535to the respective Architecture Extension Supplement.
2536
Dan Handley610e7e12018-03-01 18:44:00 +00002537Armv8.1-A
2538~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002539
2540This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2541``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
2542
2543- The Compare and Swap instruction is used to implement spinlocks. Otherwise,
2544 the load-/store-exclusive instruction pair is used.
2545
Dan Handley610e7e12018-03-01 18:44:00 +00002546Armv8.2-A
2547~~~~~~~~~
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002548
Antonio Nino Diaz633703a2019-02-19 13:14:06 +00002549- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the
2550 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple
Sandrine Bailleuxfee6e262018-01-29 14:48:15 +01002551 Processing Elements in the same Inner Shareable domain use the same
2552 translation table entries for a given stage of translation for a particular
2553 translation regime.
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002554
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002555Armv8.3-A
2556~~~~~~~~~
2557
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00002558- Pointer authentication features of Armv8.3-A are unconditionally enabled in
2559 the Non-secure world so that lower ELs are allowed to use them without
2560 causing a trap to EL3.
2561
2562 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS``
2563 must be set to 1. This will add all pointer authentication system registers
2564 to the context that is saved when doing a world switch.
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002565
Alexei Fedorov2831d582019-03-13 11:05:07 +00002566 The TF-A itself has support for pointer authentication at runtime
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002567 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002568 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1,
2569 BL2, BL31, and the TSP if it is used.
2570
Alexei Fedorov2831d582019-03-13 11:05:07 +00002571 These options are experimental features.
2572
2573 Note that Pointer Authentication is enabled for Non-secure world irrespective
2574 of the value of these build flags if the CPU supports it.
2575
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002576 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of
2577 enabling PAuth is lower because the compiler will use the optimized
2578 PAuth instructions rather than the backwards-compatible ones.
2579
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002580Armv8.5-A
2581~~~~~~~~~
2582
2583- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
2584 option set to 1. This option defaults to 0 and this is an experimental feature.
2585
Dan Handley610e7e12018-03-01 18:44:00 +00002586Armv7-A
2587~~~~~~~
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002588
2589This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7.
2590
Dan Handley610e7e12018-03-01 18:44:00 +00002591There are several Armv7-A extensions available. Obviously the TrustZone
2592extension is mandatory to support the TF-A bootloader and runtime services.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002593
Dan Handley610e7e12018-03-01 18:44:00 +00002594Platform implementing an Armv7-A system can to define from its target
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002595Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002596``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002597Cortex-A15 target.
2598
2599Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
2600Note that using neon at runtime has constraints on non secure wolrd context.
Dan Handley610e7e12018-03-01 18:44:00 +00002601TF-A does not yet provide VFP context management.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002602
2603Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
2604the toolchain target architecture directive.
2605
2606Platform may choose to not define straight the toolchain target architecture
2607directive by defining ``MARCH32_DIRECTIVE``.
2608I.e:
2609
Paul Beesley493e3492019-03-13 15:11:04 +00002610.. code:: make
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002611
2612 MARCH32_DIRECTIVE := -mach=armv7-a
2613
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002614Code Structure
2615--------------
2616
Dan Handley610e7e12018-03-01 18:44:00 +00002617TF-A code is logically divided between the three boot loader stages mentioned
2618in the previous sections. The code is also divided into the following
2619categories (present as directories in the source code):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002620
2621- **Platform specific.** Choice of architecture specific code depends upon
2622 the platform.
2623- **Common code.** This is platform and architecture agnostic code.
2624- **Library code.** This code comprises of functionality commonly used by all
2625 other code. The PSCI implementation and other EL3 runtime frameworks reside
2626 as Library components.
2627- **Stage specific.** Code specific to a boot stage.
2628- **Drivers.**
2629- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2630 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2631
2632Each boot loader stage uses code from one or more of the above mentioned
2633categories. Based upon the above, the code layout looks like this:
2634
2635::
2636
2637 Directory Used by BL1? Used by BL2? Used by BL31?
2638 bl1 Yes No No
2639 bl2 No Yes No
2640 bl31 No No Yes
2641 plat Yes Yes Yes
2642 drivers Yes No Yes
2643 common Yes Yes Yes
2644 lib Yes Yes Yes
2645 services No No Yes
2646
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002647The build system provides a non configurable build option IMAGE_BLx for each
2648boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be
Dan Handley610e7e12018-03-01 18:44:00 +00002649defined by the build system. This enables TF-A to compile certain code only
2650for specific boot loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002651
2652All assembler files have the ``.S`` extension. The linker source files for each
2653boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2654linker scripts which have the extension ``.ld``.
2655
2656FDTs provide a description of the hardware platform and are used by the Linux
2657kernel at boot time. These can be found in the ``fdts`` directory.
2658
2659References
2660----------
2661
Sandrine Bailleux30918422019-04-24 10:41:24 +02002662.. [#] `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_
Douglas Raillard30d7b362017-06-28 16:14:55 +01002663.. [#] `Power State Coordination Interface PDD`_
2664.. [#] `SMC Calling Convention PDD`_
Dan Handley610e7e12018-03-01 18:44:00 +00002665.. [#] `TF-A Interrupt Management Design guide`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002666
2667--------------
2668
Antonio Nino Diaz633703a2019-02-19 13:14:06 +00002669*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002670
2671.. _Reset Design: ./reset-design.rst
Paul Beesleyea225122019-02-11 17:54:45 +00002672.. _Porting Guide: ../getting_started/porting-guide.rst
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002673.. _Firmware Update: ../components/firmware-update.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002674.. _PSCI PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2675.. _SMC calling convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
Paul Beesleyea225122019-02-11 17:54:45 +00002676.. _PSCI Library integration guide: ../getting_started/psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002677.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
2678.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2679.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Paul Beesleyea225122019-02-11 17:54:45 +00002680.. _here: ../getting_started/psci-lib-integration-guide.rst
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002681.. _CPU specific build macros: ./cpu-specific-build-macros.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002682.. _CPUBM: ./cpu-specific-build-macros.rst
Dan Handley610e7e12018-03-01 18:44:00 +00002683.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html
Paul Beesleyea225122019-02-11 17:54:45 +00002684.. _User Guide: ../getting_started/user-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002685.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00002686.. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002687.. _Translation tables design: ../components/xlat-tables-lib-v2-design.rst
2688.. _Exception Handling Framework: ../components/exception-handling.rst
2689.. _ROMLIB Design: ../components/romlib-design.rst
Sandrine Bailleux30918422019-04-24 10:41:24 +02002690.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002691
Paul Beesley814f8c02019-03-13 15:49:27 +00002692.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png