blob: 0d6a50fdb3cf90c9f08556ac35303ade2574dd8c [file] [log] [blame]
developerc1b2cd12022-07-28 18:35:24 +08001From f70e83ccdca85840c3bf9e7a31fb871a12724dc2 Mon Sep 17 00:00:00 2001
2From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Thu, 28 Jul 2022 14:49:16 +0800
4Subject: [PATCH 3/3] add wed ser support
5
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerfd8e1152023-02-14 11:29:23 +08008 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 +
9 drivers/net/ethernet/mediatek/mtk_wed.c | 361 ++++++++++++++-----
10 drivers/net/ethernet/mediatek/mtk_wed.h | 11 +
developerc1b2cd12022-07-28 18:35:24 +080011 drivers/net/ethernet/mediatek/mtk_wed_regs.h | 12 +
developerfd8e1152023-02-14 11:29:23 +080012 include/linux/soc/mediatek/mtk_wed.h | 27 +-
13 5 files changed, 320 insertions(+), 99 deletions(-)
developerc1b2cd12022-07-28 18:35:24 +080014
developer2ed23d42022-08-09 16:20:46 +080015diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developerfd8e1152023-02-14 11:29:23 +080016index 2b52fa0..2f98525 100644
developer2ed23d42022-08-09 16:20:46 +080017--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
18+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developerfd8e1152023-02-14 11:29:23 +080019@@ -3680,6 +3680,9 @@ static void mtk_pending_work(struct work_struct *work)
developerbc6b5852022-11-22 21:09:44 +080020 for (i = 0; i < MTK_MAC_COUNT; i++) {
21 if (!eth->netdev[i])
22 continue;
developer2ed23d42022-08-09 16:20:46 +080023+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
developerfd8e1152023-02-14 11:29:23 +080024+ mtk_wed_fe_reset();
developer2ed23d42022-08-09 16:20:46 +080025+#else
developer4780eea2022-12-27 16:45:15 +080026 if (mtk_reset_flag == MTK_FE_STOP_TRAFFIC) {
27 pr_info("send MTK_FE_STOP_TRAFFIC event\n");
28 call_netdevice_notifiers(MTK_FE_STOP_TRAFFIC,
developerfd8e1152023-02-14 11:29:23 +080029@@ -3693,6 +3696,7 @@ static void mtk_pending_work(struct work_struct *work)
developer4780eea2022-12-27 16:45:15 +080030 if (!wait_for_completion_timeout(&wait_ser_done, 3000))
developerfd8e1152023-02-14 11:29:23 +080031 pr_warn("wait for MTK_FE_START_RESET\n");
developerbc6b5852022-11-22 21:09:44 +080032 rtnl_lock();
developer2ed23d42022-08-09 16:20:46 +080033+#endif
developerbc6b5852022-11-22 21:09:44 +080034 break;
35 }
developer2ed23d42022-08-09 16:20:46 +080036
developerfd8e1152023-02-14 11:29:23 +080037@@ -3731,6 +3735,9 @@ static void mtk_pending_work(struct work_struct *work)
developer4780eea2022-12-27 16:45:15 +080038 for (i = 0; i < MTK_MAC_COUNT; i++) {
39 if (!eth->netdev[i])
developerbc6b5852022-11-22 21:09:44 +080040 continue;
developer2ed23d42022-08-09 16:20:46 +080041+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
developerfd8e1152023-02-14 11:29:23 +080042+ mtk_wed_fe_reset_complete();
developer2ed23d42022-08-09 16:20:46 +080043+#else
developer4780eea2022-12-27 16:45:15 +080044 if (mtk_reset_flag == MTK_FE_STOP_TRAFFIC) {
45 pr_info("send MTK_FE_START_TRAFFIC event\n");
46 call_netdevice_notifiers(MTK_FE_START_TRAFFIC,
developerfd8e1152023-02-14 11:29:23 +080047@@ -3740,6 +3747,7 @@ static void mtk_pending_work(struct work_struct *work)
developer4780eea2022-12-27 16:45:15 +080048 call_netdevice_notifiers(MTK_FE_RESET_DONE,
49 eth->netdev[i]);
50 }
developer2ed23d42022-08-09 16:20:46 +080051+#endif
developer4780eea2022-12-27 16:45:15 +080052 call_netdevice_notifiers(MTK_FE_RESET_NAT_DONE,
53 eth->netdev[i]);
developerbc6b5852022-11-22 21:09:44 +080054 break;
developerc1b2cd12022-07-28 18:35:24 +080055diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
developerfd8e1152023-02-14 11:29:23 +080056index ff8f658..0917a5a 100644
developerc1b2cd12022-07-28 18:35:24 +080057--- a/drivers/net/ethernet/mediatek/mtk_wed.c
58+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
developer2ed23d42022-08-09 16:20:46 +080059@@ -13,8 +13,10 @@
60 #include <linux/debugfs.h>
61 #include <linux/iopoll.h>
62 #include <linux/soc/mediatek/mtk_wed.h>
63+#include <net/rtnetlink.h>
64
65 #include "mtk_eth_soc.h"
66+#include "mtk_eth_reset.h"
67 #include "mtk_wed_regs.h"
68 #include "mtk_wed.h"
69 #include "mtk_ppe.h"
70@@ -71,23 +73,27 @@ mtk_wdma_read_reset(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +080071 return wdma_r32(dev, MTK_WDMA_GLO_CFG);
72 }
73
74-static void
75+static int
76 mtk_wdma_rx_reset(struct mtk_wed_device *dev)
77 {
78 u32 status;
79 u32 mask = MTK_WDMA_GLO_CFG_RX_DMA_BUSY;
80- int i;
81+ int busy, i;
82
83 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_DMA_EN);
84- if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
85- !(status & mask), 0, 1000))
86- WARN_ON_ONCE(1);
87+ busy = readx_poll_timeout(mtk_wdma_read_reset, dev, status,
88+ !(status & mask), 0, 10000);
89+
90+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
91+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
92
93 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
94 if (!dev->rx_wdma[i].desc) {
95 wdma_w32(dev, MTK_WDMA_RING_RX(i) +
96 MTK_WED_RING_OFS_CPU_IDX, 0);
97 }
98+
99+ return busy;
100 }
101
102 static void
developer2ed23d42022-08-09 16:20:46 +0800103@@ -99,14 +105,14 @@ mtk_wdma_tx_reset(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800104
105 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
106 if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
107- !(status & mask), 0, 1000))
108+ !(status & mask), 0, 10000))
109 WARN_ON_ONCE(1);
110
111+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
112+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
113 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
developer2ed23d42022-08-09 16:20:46 +0800114- if (!dev->tx_wdma[i].desc) {
developer553bdd92022-08-12 09:58:45 +0800115- wdma_w32(dev, MTK_WDMA_RING_TX(i) +
116- MTK_WED_RING_OFS_CPU_IDX, 0);
developer2ed23d42022-08-09 16:20:46 +0800117- }
developer553bdd92022-08-12 09:58:45 +0800118+ wdma_w32(dev, MTK_WDMA_RING_TX(i) +
119+ MTK_WED_RING_OFS_CPU_IDX, 0);
developer2ed23d42022-08-09 16:20:46 +0800120 }
121
122 static u32
developerfd8e1152023-02-14 11:29:23 +0800123@@ -172,6 +178,51 @@ mtk_wed_wo_reset(struct mtk_wed_device *dev)
124 iounmap((void *)reg);
125 }
126
127+void mtk_wed_fe_reset(void)
128+{
129+ int i;
130+
131+ mutex_lock(&hw_lock);
132+
133+ for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
134+ struct mtk_wed_hw *hw = hw_list[i];
135+ struct mtk_wed_device *dev = hw->wed_dev;
136+ int err;
137+
138+ if (!dev || !dev->wlan.reset)
139+ continue;
140+
141+ pr_info("%s: receive fe reset start event, trigger SER\n", __func__);
142+
143+ /* reset callback blocks until WLAN reset is completed */
144+ err = dev->wlan.reset(dev);
145+ if (err)
146+ dev_err(dev->dev, "wlan reset failed: %d\n", err);
147+ }
148+
149+ mutex_unlock(&hw_lock);
150+}
151+
152+void mtk_wed_fe_reset_complete(void)
153+{
154+ int i;
155+
156+ mutex_lock(&hw_lock);
157+
158+ for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
159+ struct mtk_wed_hw *hw = hw_list[i];
160+ struct mtk_wed_device *dev = hw->wed_dev;
161+
162+ if (!dev || !dev->wlan.reset_complete)
163+ continue;
164+
165+ pr_info("%s: receive fe reset done event, continue SER\n", __func__);
166+ dev->wlan.reset_complete(dev);
167+ }
168+
169+ mutex_unlock(&hw_lock);
170+}
171+
172 static struct mtk_wed_hw *
173 mtk_wed_assign(struct mtk_wed_device *dev)
174 {
175@@ -505,8 +556,8 @@ mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
developerc1b2cd12022-07-28 18:35:24 +0800176 wifi_w32(dev, dev->wlan.wpdma_rx_glo -
177 dev->wlan.phy_base, val);
178 } else {
179- dev_err(dev->hw->dev, "mtk_wed%d: rx dma enable failed!\n",
180- dev->hw->index);
181+ dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable failed!\n",
182+ dev->hw->index, idx);
183 }
184 }
185
developerfd8e1152023-02-14 11:29:23 +0800186@@ -557,7 +608,7 @@ mtk_wed_dma_enable(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800187 FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
188 0x2));
189
190- for (idx = 0; idx < MTK_WED_RX_QUEUES; idx++)
191+ for (idx = 0; idx < dev->hw->ring_num; idx++)
192 mtk_wed_check_wfdma_rx_fill(dev, idx);
193 }
194 }
developerfd8e1152023-02-14 11:29:23 +0800195@@ -594,36 +645,45 @@ mtk_wed_dma_disable(struct mtk_wed_device *dev)
196 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
197 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
198 }
199+
200+ mtk_wed_set_512_support(dev, false);
developerc1b2cd12022-07-28 18:35:24 +0800201 }
202
203 static void
developerfd8e1152023-02-14 11:29:23 +0800204 mtk_wed_stop(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800205 {
206- mtk_wed_dma_disable(dev);
207- mtk_wed_set_512_support(dev, false);
208-
209 if (dev->ver > MTK_WED_V1) {
210 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
211 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
212 }
213 mtk_wed_set_ext_int(dev, false);
214
developerfd8e1152023-02-14 11:29:23 +0800215+ wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
216+ wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
217+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
218+ wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
219+ wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
220+}
221+
222+static void
223+mtk_wed_deinit(struct mtk_wed_device *dev)
224+{
225+ mtk_wed_stop(dev);
226+ mtk_wed_dma_disable(dev);
227+
228 wed_clr(dev, MTK_WED_CTRL,
229 MTK_WED_CTRL_WDMA_INT_AGENT_EN |
230 MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
231 MTK_WED_CTRL_WED_TX_BM_EN |
232 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
233
developerc1b2cd12022-07-28 18:35:24 +0800234- if (dev->ver > MTK_WED_V1) {
developerfd8e1152023-02-14 11:29:23 +0800235- wed_clr(dev, MTK_WED_CTRL,
developerc1b2cd12022-07-28 18:35:24 +0800236- MTK_WED_CTRL_WED_RX_BM_EN);
developerfd8e1152023-02-14 11:29:23 +0800237- }
238+ if (dev->hw->ver == 1)
239+ return;
developerc1b2cd12022-07-28 18:35:24 +0800240
developerfd8e1152023-02-14 11:29:23 +0800241- wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
242- wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
243- wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
244- wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
245- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
246+ wed_clr(dev, MTK_WED_CTRL,
247+ MTK_WED_CTRL_RX_ROUTE_QM_EN |
248+ MTK_WED_CTRL_WED_RX_BM_EN |
249+ MTK_WED_CTRL_RX_RRO_QM_EN);
250 }
251
252 static void
253@@ -634,16 +694,13 @@ mtk_wed_detach(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800254
255 mutex_lock(&hw_lock);
256
257- mtk_wed_stop(dev);
developerfd8e1152023-02-14 11:29:23 +0800258+ mtk_wed_deinit(dev);
developerc1b2cd12022-07-28 18:35:24 +0800259
260- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
261- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
262+ mtk_wdma_rx_reset(dev);
263
264 mtk_wed_reset(dev, MTK_WED_RESET_WED);
265
266- wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
267- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
268- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
269+ mtk_wdma_tx_reset(dev);
270
271 mtk_wed_free_buffer(dev);
272 mtk_wed_free_tx_rings(dev);
developerfd8e1152023-02-14 11:29:23 +0800273@@ -653,8 +710,6 @@ mtk_wed_detach(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800274 mtk_wed_wo_exit(hw);
275 }
276
277- mtk_wdma_rx_reset(dev);
278-
developer144824b2022-11-25 21:27:43 +0800279 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
developerc1b2cd12022-07-28 18:35:24 +0800280 wlan_node = dev->wlan.pci_dev->dev.of_node;
281 if (of_dma_is_coherent(wlan_node))
developerfd8e1152023-02-14 11:29:23 +0800282@@ -748,7 +803,7 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800283 {
284 u32 mask, set;
285
286- mtk_wed_stop(dev);
developerfd8e1152023-02-14 11:29:23 +0800287+ mtk_wed_deinit(dev);
developerc1b2cd12022-07-28 18:35:24 +0800288 mtk_wed_reset(dev, MTK_WED_RESET_WED);
289
290 if (dev->ver > MTK_WED_V1)
developerfd8e1152023-02-14 11:29:23 +0800291@@ -961,44 +1016,127 @@ mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size, int scale, bool tx)
developerc1b2cd12022-07-28 18:35:24 +0800292 }
293
294 static u32
295-mtk_wed_check_busy(struct mtk_wed_device *dev)
296+mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
297 {
298- if (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY)
299- return true;
300-
301- if (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) &
302- MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY)
303- return true;
304-
305- if (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY)
306- return true;
307-
308- if (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) &
309- MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
310- return true;
311-
312- if (wdma_r32(dev, MTK_WDMA_GLO_CFG) &
313- MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
314- return true;
315-
316- if (wed_r32(dev, MTK_WED_CTRL) &
317- (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY))
318+ if (wed_r32(dev, reg) & mask)
319 return true;
320
321 return false;
322 }
323
324 static int
325-mtk_wed_poll_busy(struct mtk_wed_device *dev)
326+mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
327 {
328- int sleep = 15000;
329+ int sleep = 1000;
330 int timeout = 100 * sleep;
331 u32 val;
332
333 return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
334- timeout, false, dev);
335+ timeout, false, dev, reg, mask);
developerfd8e1152023-02-14 11:29:23 +0800336 }
337
developerc1b2cd12022-07-28 18:35:24 +0800338+static void
339+mtk_wed_rx_reset(struct mtk_wed_device *dev)
340+{
341+ struct mtk_wed_wo *wo = dev->hw->wed_wo;
342+ u8 state = WO_STATE_SER_RESET;
343+ bool busy = false;
344+ int i;
345+
developer144824b2022-11-25 21:27:43 +0800346+ mtk_wed_mcu_send_msg(wo, MODULE_ID_WO, MTK_WED_WO_CMD_CHANGE_STATE,
developerc1b2cd12022-07-28 18:35:24 +0800347+ &state, sizeof(state), true);
348+
349+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN);
350+ busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
351+ MTK_WED_WPDMA_RX_D_RX_DRV_BUSY);
352+ if (busy) {
353+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
354+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV);
355+ } else {
356+ wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
357+ MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
358+ MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
359+
360+ wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
361+ MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
362+ MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
363+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
364+ MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
365+ MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
366+
367+ wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
368+ }
369+
370+ /* reset rro qm */
371+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
372+ busy = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
373+ MTK_WED_CTRL_RX_RRO_QM_BUSY);
374+ if (busy) {
375+ mtk_wed_reset(dev, MTK_WED_RESET_RX_RRO_QM);
376+ } else {
377+ wed_set(dev, MTK_WED_RROQM_RST_IDX,
378+ MTK_WED_RROQM_RST_IDX_MIOD |
379+ MTK_WED_RROQM_RST_IDX_FDBK);
380+ wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
381+ }
382+
383+ /* reset route qm */
384+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
385+ busy = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
386+ MTK_WED_CTRL_RX_ROUTE_QM_BUSY);
387+ if (busy) {
388+ mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
389+ } else {
390+ wed_set(dev, MTK_WED_RTQM_GLO_CFG,
391+ MTK_WED_RTQM_Q_RST);
392+ }
393+
394+ /* reset tx wdma */
395+ mtk_wdma_tx_reset(dev);
396+
397+ /* reset tx wdma drv */
398+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN);
399+ mtk_wed_poll_busy(dev, MTK_WED_CTRL,
400+ MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
401+ mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
402+
403+ /* reset wed rx dma */
404+ busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
405+ MTK_WED_GLO_CFG_RX_DMA_BUSY);
406+ wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_RX_DMA_EN);
407+ if (busy) {
408+ mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
409+ } else {
410+ wed_set(dev, MTK_WED_RESET_IDX,
411+ MTK_WED_RESET_IDX_RX);
412+ wed_w32(dev, MTK_WED_RESET_IDX, 0);
413+ }
414+
415+ /* reset rx bm */
416+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
417+ mtk_wed_poll_busy(dev, MTK_WED_CTRL,
418+ MTK_WED_CTRL_WED_RX_BM_BUSY);
419+ mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
420+
421+ /* wo change to enable state */
422+ state = WO_STATE_ENABLE;
developer144824b2022-11-25 21:27:43 +0800423+ mtk_wed_mcu_send_msg(wo, MODULE_ID_WO, MTK_WED_WO_CMD_CHANGE_STATE,
developerc1b2cd12022-07-28 18:35:24 +0800424+ &state, sizeof(state), true);
425+
426+ /* wed_rx_ring_reset */
427+ for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++) {
428+ struct mtk_wdma_desc *desc = dev->rx_ring[i].desc;
429+
430+ if (!desc)
431+ continue;
432+
433+ mtk_wed_ring_reset(desc, MTK_WED_RX_RING_SIZE, 1, false);
434+ }
435+
436+ mtk_wed_free_rx_bm(dev);
developerfd8e1152023-02-14 11:29:23 +0800437+}
438+
developerc1b2cd12022-07-28 18:35:24 +0800439+
440 static void
441 mtk_wed_reset_dma(struct mtk_wed_device *dev)
442 {
developerfd8e1152023-02-14 11:29:23 +0800443@@ -1012,25 +1150,28 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800444 if (!desc)
445 continue;
446
447- mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE, dev->ver, true);
448+ mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE, 1, true);
449 }
450
451- if (mtk_wed_poll_busy(dev))
452- busy = mtk_wed_check_busy(dev);
453+ /* 1.Reset WED Tx DMA */
454+ wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_EN);
455+ busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_BUSY);
456
457 if (busy) {
458 mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
459 } else {
460 wed_w32(dev, MTK_WED_RESET_IDX,
461- MTK_WED_RESET_IDX_TX |
462- MTK_WED_RESET_IDX_RX);
463+ MTK_WED_RESET_IDX_TX);
464 wed_w32(dev, MTK_WED_RESET_IDX, 0);
465 }
466
467- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
468- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
469+ /* 2. Reset WDMA Rx DMA/Driver_Engine */
470+ busy = !!mtk_wdma_rx_reset(dev);
471
472- mtk_wdma_rx_reset(dev);
473+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
474+ busy = !!(busy ||
475+ mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG,
476+ MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY));
477
478 if (busy) {
479 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
developerfd8e1152023-02-14 11:29:23 +0800480@@ -1047,15 +1188,30 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800481 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
482 }
483
484+ /* 3. Reset WED WPDMA Tx Driver Engine */
485+ wed_clr(dev, MTK_WED_CTRL,
486+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
487+
488 for (i = 0; i < 100; i++) {
489 val = wed_r32(dev, MTK_WED_TX_BM_INTF);
490 if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
491 break;
492 }
493-
494 mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
495+
496+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_BM_EN);
497 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
498
499+ /* 4. Reset WED WPDMA Tx Driver Engine */
500+ busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
501+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY);
502+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
503+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
504+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
505+
506+ busy = !!(busy ||
507+ mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
508+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY));
509 if (busy) {
510 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
511 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
developerfd8e1152023-02-14 11:29:23 +0800512@@ -1065,6 +1221,16 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800513 MTK_WED_WPDMA_RESET_IDX_TX |
514 MTK_WED_WPDMA_RESET_IDX_RX);
515 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
516+ if (dev->ver > MTK_WED_V1) {
517+ wed_w32(dev, MTK_WED_RESET_IDX,
518+ MTK_WED_RESET_WPDMA_IDX_RX);
519+ wed_w32(dev, MTK_WED_RESET_IDX, 0);
520+ }
521+ }
522+
523+ if (dev->ver > MTK_WED_V1) {
524+ dev->init_done = false;
525+ mtk_wed_rx_reset(dev);
526 }
527
developer2ed23d42022-08-09 16:20:46 +0800528 }
developerfd8e1152023-02-14 11:29:23 +0800529@@ -1101,13 +1267,15 @@ mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
developer2ed23d42022-08-09 16:20:46 +0800530 }
531
532 static int
533-mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
534+mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev,
535+ int idx, int size, bool reset)
536 {
537 struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
538
539- if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
540- dev->ver, true))
541- return -ENOMEM;
542+ if(!reset)
543+ if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
544+ dev->ver, true))
545+ return -ENOMEM;
546
547 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
548 wdma->desc_phys);
developerfd8e1152023-02-14 11:29:23 +0800549@@ -1124,13 +1292,15 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
developerc1b2cd12022-07-28 18:35:24 +0800550 }
developer2ed23d42022-08-09 16:20:46 +0800551
552 static int
553-mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
554+mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev,
555+ int idx, int size, bool reset)
556 {
557 struct mtk_wed_ring *wdma = &dev->rx_wdma[idx];
558
559- if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
560- dev->ver, true))
561- return -ENOMEM;
562+ if (!reset)
563+ if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
564+ dev->ver, true))
565+ return -ENOMEM;
566
567 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
568 wdma->desc_phys);
developerfd8e1152023-02-14 11:29:23 +0800569@@ -1140,7 +1310,9 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
developer2ed23d42022-08-09 16:20:46 +0800570 MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
571 wdma_w32(dev,
572 MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
573-
574+ if (reset)
575+ mtk_wed_ring_reset(wdma->desc, MTK_WED_WDMA_RING_SIZE,
576+ dev->ver, true);
577 if (idx == 0) {
578 wed_w32(dev, MTK_WED_WDMA_RING_TX
579 + MTK_WED_RING_OFS_BASE, wdma->desc_phys);
developerfd8e1152023-02-14 11:29:23 +0800580@@ -1253,9 +1425,12 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
developerc1b2cd12022-07-28 18:35:24 +0800581 {
582 int i, ret;
583
584+ if (dev->ver > MTK_WED_V1)
585+ ret = mtk_wed_rx_bm_alloc(dev);
586+
587 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
588 if (!dev->tx_wdma[i].desc)
developer2ed23d42022-08-09 16:20:46 +0800589- mtk_wed_wdma_rx_ring_setup(dev, i, 16);
590+ mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
591
592 mtk_wed_hw_init(dev);
593
developerfd8e1152023-02-14 11:29:23 +0800594@@ -1347,10 +1522,6 @@ mtk_wed_attach(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800595 goto error;
596
597 if (dev->ver > MTK_WED_V1) {
598- ret = mtk_wed_rx_bm_alloc(dev);
599- if (ret)
600- goto error;
601-
602 ret = mtk_wed_rro_alloc(dev);
603 if (ret)
604 goto error;
developerfd8e1152023-02-14 11:29:23 +0800605@@ -1358,6 +1529,10 @@ mtk_wed_attach(struct mtk_wed_device *dev)
developer2ed23d42022-08-09 16:20:46 +0800606
607 mtk_wed_hw_init_early(dev);
608
609+ init_completion(&dev->fe_reset_done);
610+ init_completion(&dev->wlan_reset_done);
611+ atomic_set(&dev->fe_reset, 0);
612+
613 if (dev->ver == MTK_WED_V1)
614 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
615 BIT(hw->index), 0);
developerfd8e1152023-02-14 11:29:23 +0800616@@ -1374,7 +1549,8 @@ out:
developerc1b2cd12022-07-28 18:35:24 +0800617 }
618
619 static int
620-mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
621+mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx,
622+ void __iomem *regs, bool reset)
623 {
624 struct mtk_wed_ring *ring = &dev->tx_ring[idx];
625
developerfd8e1152023-02-14 11:29:23 +0800626@@ -1392,10 +1568,12 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
developerc1b2cd12022-07-28 18:35:24 +0800627
628 BUG_ON(idx > ARRAY_SIZE(dev->tx_ring));
629
630- if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE, 1, true))
631- return -ENOMEM;
developer2ed23d42022-08-09 16:20:46 +0800632+ if (!reset)
developerc1b2cd12022-07-28 18:35:24 +0800633+ if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE,
634+ 1, true))
635+ return -ENOMEM;
636
developer2ed23d42022-08-09 16:20:46 +0800637- if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
638+ if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, reset))
639 return -ENOMEM;
developerc1b2cd12022-07-28 18:35:24 +0800640
developer2ed23d42022-08-09 16:20:46 +0800641 ring->reg_base = MTK_WED_RING_TX(idx);
developerfd8e1152023-02-14 11:29:23 +0800642@@ -1443,21 +1621,24 @@ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
developerc1b2cd12022-07-28 18:35:24 +0800643 }
644
645 static int
646-mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
647+mtk_wed_rx_ring_setup(struct mtk_wed_device *dev,
648+ int idx, void __iomem *regs, bool reset)
649 {
650 struct mtk_wed_ring *ring = &dev->rx_ring[idx];
651
652 BUG_ON(idx > ARRAY_SIZE(dev->rx_ring));
653
developer2ed23d42022-08-09 16:20:46 +0800654+ if (!reset)
developerc1b2cd12022-07-28 18:35:24 +0800655+ if (mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE,
656+ 1, false))
657+ return -ENOMEM;
658
659- if (mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE, 1, false))
660- return -ENOMEM;
661-
662- if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
developer2ed23d42022-08-09 16:20:46 +0800663+ if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, reset))
664 return -ENOMEM;
665
developerc1b2cd12022-07-28 18:35:24 +0800666 ring->reg_base = MTK_WED_RING_RX_DATA(idx);
667 ring->wpdma = regs;
668+ dev->hw->ring_num = idx + 1;
669
670 /* WPDMA -> WED */
671 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
672diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h
developerfd8e1152023-02-14 11:29:23 +0800673index 8ef5253..490873c 100644
developerc1b2cd12022-07-28 18:35:24 +0800674--- a/drivers/net/ethernet/mediatek/mtk_wed.h
675+++ b/drivers/net/ethernet/mediatek/mtk_wed.h
676@@ -47,6 +47,7 @@ struct mtk_wed_hw {
677 u32 num_flows;
678 u32 wdma_phy;
679 char dirname[5];
680+ int ring_num;
681 int irq;
682 int index;
683 u32 ver;
developerfd8e1152023-02-14 11:29:23 +0800684@@ -158,6 +159,9 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
685 void mtk_wed_exit(void);
686 int mtk_wed_flow_add(int index);
687 void mtk_wed_flow_remove(int index);
688+void mtk_wed_fe_reset(void);
689+void mtk_wed_fe_reset_complete(void);
690+
691 #else
692 static inline void
693 mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
694@@ -175,6 +179,13 @@ static inline int mtk_wed_flow_add(int index)
695 static inline void mtk_wed_flow_remove(int index)
696 {
697 }
698+static inline void mtk_wed_fe_reset(void)
699+{
700+}
701+
702+static inline void mtk_wed_fe_reset_complete(void)
703+{
704+}
developer2ed23d42022-08-09 16:20:46 +0800705 #endif
developerfd8e1152023-02-14 11:29:23 +0800706
707 #ifdef CONFIG_DEBUG_FS
developerc1b2cd12022-07-28 18:35:24 +0800708diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
709index 9d021e2..cfcd94f 100644
710--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
711+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
712@@ -38,11 +38,15 @@ struct mtk_wdma_desc {
713
714 #define MTK_WED_RESET 0x008
715 #define MTK_WED_RESET_TX_BM BIT(0)
716+#define MTK_WED_RESET_RX_BM BIT(1)
717 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
718 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
719 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
720+#define MTK_WED_RESET_WPDMA_RX_D_DRV BIT(10)
721 #define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)
722 #define MTK_WED_RESET_WED_TX_DMA BIT(12)
723+#define MTK_WED_RESET_WED_RX_DMA BIT(13)
724+#define MTK_WED_RESET_WDMA_TX_DRV BIT(16)
725 #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
726 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
727 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
728@@ -186,7 +190,12 @@ struct mtk_wdma_desc {
729
730 #define MTK_WED_RESET_IDX 0x20c
731 #define MTK_WED_RESET_IDX_TX GENMASK(3, 0)
732+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
733+#define MTK_WED_RESET_IDX_RX GENMASK(7, 6)
734+#else
735 #define MTK_WED_RESET_IDX_RX GENMASK(17, 16)
736+#endif
737+#define MTK_WED_RESET_WPDMA_IDX_RX GENMASK(31, 30)
738
739 #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)
740 #define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4)
741@@ -300,6 +309,9 @@ struct mtk_wdma_desc {
742
743 #define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c
744 #define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
745+#define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY BIT(1)
746+#define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE BIT(3)
747+#define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE BIT(4)
748 #define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7)
749 #define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24)
750
751diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h
developerfd8e1152023-02-14 11:29:23 +0800752index e8fca31..98ed390 100644
developerc1b2cd12022-07-28 18:35:24 +0800753--- a/include/linux/soc/mediatek/mtk_wed.h
754+++ b/include/linux/soc/mediatek/mtk_wed.h
developerfd8e1152023-02-14 11:29:23 +0800755@@ -163,18 +163,23 @@ struct mtk_wed_device {
developer2ed23d42022-08-09 16:20:46 +0800756 void (*release_rx_buf)(struct mtk_wed_device *wed);
developer144824b2022-11-25 21:27:43 +0800757 void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
758 struct mtk_wed_wo_rx_stats *stats);
developerfd8e1152023-02-14 11:29:23 +0800759+ int (*reset)(struct mtk_wed_device *wed);
760+ void (*reset_complete)(struct mtk_wed_device *wed);
developer2ed23d42022-08-09 16:20:46 +0800761 } wlan;
762+ struct completion fe_reset_done;
763+ struct completion wlan_reset_done;
764+ atomic_t fe_reset;
765 #endif
766 };
767
developerc1b2cd12022-07-28 18:35:24 +0800768 struct mtk_wed_ops {
769 int (*attach)(struct mtk_wed_device *dev);
770 int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,
771- void __iomem *regs);
772+ void __iomem *regs, bool reset);
773 int (*txfree_ring_setup)(struct mtk_wed_device *dev,
774 void __iomem *regs);
775 int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
776- void __iomem *regs);
777+ void __iomem *regs, bool reset);
778 int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
779 void *data, int len);
780 void (*detach)(struct mtk_wed_device *dev);
developerfd8e1152023-02-14 11:29:23 +0800781@@ -228,12 +233,13 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800782 #define mtk_wed_device_active(_dev) !!(_dev)->ops
783 #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
784 #define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)
785-#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \
786- (_dev)->ops->tx_ring_setup(_dev, _ring, _regs)
developerfd8e1152023-02-14 11:29:23 +0800787+#define mtk_wed_device_stop(_dev) (_dev)->ops->stop(_dev)
developerc1b2cd12022-07-28 18:35:24 +0800788+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) \
789+ (_dev)->ops->tx_ring_setup(_dev, _ring, _regs, _reset)
790 #define mtk_wed_device_txfree_ring_setup(_dev, _regs) \
791 (_dev)->ops->txfree_ring_setup(_dev, _regs)
792-#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) \
793- (_dev)->ops->rx_ring_setup(_dev, _ring, _regs)
794+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) \
795+ (_dev)->ops->rx_ring_setup(_dev, _ring, _regs, _reset)
796 #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
797 (_dev)->ops->msg_update(_dev, _id, _msg, _len)
798 #define mtk_wed_device_reg_read(_dev, _reg) \
developerfd8e1152023-02-14 11:29:23 +0800799@@ -244,6 +250,8 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800800 (_dev)->ops->irq_get(_dev, _mask)
801 #define mtk_wed_device_irq_set_mask(_dev, _mask) \
802 (_dev)->ops->irq_set_mask(_dev, _mask)
803+#define mtk_wed_device_dma_reset(_dev) \
804+ (_dev)->ops->reset_dma(_dev)
805 #define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
806 (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
807 #else
developerfd8e1152023-02-14 11:29:23 +0800808@@ -253,14 +261,15 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800809 }
810 #define mtk_wed_device_detach(_dev) do {} while (0)
811 #define mtk_wed_device_start(_dev, _mask) do {} while (0)
812-#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV
developerfd8e1152023-02-14 11:29:23 +0800813+#define mtk_wed_device_stop(_dev) do {} while (0)
developerc1b2cd12022-07-28 18:35:24 +0800814+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
815 #define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV
816-#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) -ENODEV
817-#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV
818+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
819 #define mtk_wed_device_reg_read(_dev, _reg) 0
820 #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
821 #define mtk_wed_device_irq_get(_dev, _mask) 0
822 #define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)
823+#define mtk_wed_device_dma_reset(_dev) do {} while (0)
824 #define mtk_wed_device_ppe_check(_dev, _hash) do {} while (0)
825 #endif
826
827--
8282.18.0
829