blob: b2714d0bd370b3c6281db9d42d6635c4cc0ad798 [file] [log] [blame]
developerc1b2cd12022-07-28 18:35:24 +08001From f70e83ccdca85840c3bf9e7a31fb871a12724dc2 Mon Sep 17 00:00:00 2001
2From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Thu, 28 Jul 2022 14:49:16 +0800
4Subject: [PATCH 3/3] add wed ser support
5
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developer2ed23d42022-08-09 16:20:46 +08008 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +-
developer553bdd92022-08-12 09:58:45 +08009 drivers/net/ethernet/mediatek/mtk_wed.c | 347 ++++++++++++++-----
developer2ed23d42022-08-09 16:20:46 +080010 drivers/net/ethernet/mediatek/mtk_wed.h | 2 +
developerc1b2cd12022-07-28 18:35:24 +080011 drivers/net/ethernet/mediatek/mtk_wed_regs.h | 12 +
developer2ed23d42022-08-09 16:20:46 +080012 include/linux/soc/mediatek/mtk_wed.h | 28 +-
developer553bdd92022-08-12 09:58:45 +080013 5 files changed, 297 insertions(+), 101 deletions(-)
developerc1b2cd12022-07-28 18:35:24 +080014
developer2ed23d42022-08-09 16:20:46 +080015diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developer4780eea2022-12-27 16:45:15 +080016index 51b40fa..8dbea6b 100644
developer2ed23d42022-08-09 16:20:46 +080017--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
18+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developer4780eea2022-12-27 16:45:15 +080019@@ -3662,6 +3662,9 @@ static void mtk_pending_work(struct work_struct *work)
developerbc6b5852022-11-22 21:09:44 +080020 for (i = 0; i < MTK_MAC_COUNT; i++) {
21 if (!eth->netdev[i])
22 continue;
developer2ed23d42022-08-09 16:20:46 +080023+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
developerbc6b5852022-11-22 21:09:44 +080024+ mtk_wed_fe_reset(MTK_FE_START_RESET);
developer2ed23d42022-08-09 16:20:46 +080025+#else
developer4780eea2022-12-27 16:45:15 +080026 if (mtk_reset_flag == MTK_FE_STOP_TRAFFIC) {
27 pr_info("send MTK_FE_STOP_TRAFFIC event\n");
28 call_netdevice_notifiers(MTK_FE_STOP_TRAFFIC,
29@@ -3675,6 +3678,7 @@ static void mtk_pending_work(struct work_struct *work)
30 if (!wait_for_completion_timeout(&wait_ser_done, 3000))
31 pr_warn("wait for MTK_FE_START_RESET failed\n");
developerbc6b5852022-11-22 21:09:44 +080032 rtnl_lock();
developer2ed23d42022-08-09 16:20:46 +080033+#endif
developerbc6b5852022-11-22 21:09:44 +080034 break;
35 }
developer2ed23d42022-08-09 16:20:46 +080036
developer4780eea2022-12-27 16:45:15 +080037@@ -3713,6 +3717,9 @@ static void mtk_pending_work(struct work_struct *work)
38 for (i = 0; i < MTK_MAC_COUNT; i++) {
39 if (!eth->netdev[i])
developerbc6b5852022-11-22 21:09:44 +080040 continue;
developer2ed23d42022-08-09 16:20:46 +080041+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
developerbc6b5852022-11-22 21:09:44 +080042+ mtk_wed_fe_reset(MTK_FE_RESET_DONE);
developer2ed23d42022-08-09 16:20:46 +080043+#else
developer4780eea2022-12-27 16:45:15 +080044 if (mtk_reset_flag == MTK_FE_STOP_TRAFFIC) {
45 pr_info("send MTK_FE_START_TRAFFIC event\n");
46 call_netdevice_notifiers(MTK_FE_START_TRAFFIC,
47@@ -3722,6 +3729,7 @@ static void mtk_pending_work(struct work_struct *work)
48 call_netdevice_notifiers(MTK_FE_RESET_DONE,
49 eth->netdev[i]);
50 }
developer2ed23d42022-08-09 16:20:46 +080051+#endif
developer4780eea2022-12-27 16:45:15 +080052 call_netdevice_notifiers(MTK_FE_RESET_NAT_DONE,
53 eth->netdev[i]);
developerbc6b5852022-11-22 21:09:44 +080054 break;
developerc1b2cd12022-07-28 18:35:24 +080055diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
developer553bdd92022-08-12 09:58:45 +080056index 7552795..c98d749 100644
developerc1b2cd12022-07-28 18:35:24 +080057--- a/drivers/net/ethernet/mediatek/mtk_wed.c
58+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
developer2ed23d42022-08-09 16:20:46 +080059@@ -13,8 +13,10 @@
60 #include <linux/debugfs.h>
61 #include <linux/iopoll.h>
62 #include <linux/soc/mediatek/mtk_wed.h>
63+#include <net/rtnetlink.h>
64
65 #include "mtk_eth_soc.h"
66+#include "mtk_eth_reset.h"
67 #include "mtk_wed_regs.h"
68 #include "mtk_wed.h"
69 #include "mtk_ppe.h"
70@@ -71,23 +73,27 @@ mtk_wdma_read_reset(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +080071 return wdma_r32(dev, MTK_WDMA_GLO_CFG);
72 }
73
74-static void
75+static int
76 mtk_wdma_rx_reset(struct mtk_wed_device *dev)
77 {
78 u32 status;
79 u32 mask = MTK_WDMA_GLO_CFG_RX_DMA_BUSY;
80- int i;
81+ int busy, i;
82
83 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_DMA_EN);
84- if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
85- !(status & mask), 0, 1000))
86- WARN_ON_ONCE(1);
87+ busy = readx_poll_timeout(mtk_wdma_read_reset, dev, status,
88+ !(status & mask), 0, 10000);
89+
90+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
91+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
92
93 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
94 if (!dev->rx_wdma[i].desc) {
95 wdma_w32(dev, MTK_WDMA_RING_RX(i) +
96 MTK_WED_RING_OFS_CPU_IDX, 0);
97 }
98+
99+ return busy;
100 }
101
102 static void
developer2ed23d42022-08-09 16:20:46 +0800103@@ -99,14 +105,14 @@ mtk_wdma_tx_reset(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800104
105 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
106 if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
107- !(status & mask), 0, 1000))
108+ !(status & mask), 0, 10000))
109 WARN_ON_ONCE(1);
110
111+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
112+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
113 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
developer2ed23d42022-08-09 16:20:46 +0800114- if (!dev->tx_wdma[i].desc) {
developer553bdd92022-08-12 09:58:45 +0800115- wdma_w32(dev, MTK_WDMA_RING_TX(i) +
116- MTK_WED_RING_OFS_CPU_IDX, 0);
developer2ed23d42022-08-09 16:20:46 +0800117- }
developer553bdd92022-08-12 09:58:45 +0800118+ wdma_w32(dev, MTK_WDMA_RING_TX(i) +
119+ MTK_WED_RING_OFS_CPU_IDX, 0);
developer2ed23d42022-08-09 16:20:46 +0800120 }
121
122 static u32
developerc1b2cd12022-07-28 18:35:24 +0800123@@ -505,8 +511,8 @@ mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
124 wifi_w32(dev, dev->wlan.wpdma_rx_glo -
125 dev->wlan.phy_base, val);
126 } else {
127- dev_err(dev->hw->dev, "mtk_wed%d: rx dma enable failed!\n",
128- dev->hw->index);
129+ dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable failed!\n",
130+ dev->hw->index, idx);
131 }
132 }
133
134@@ -557,7 +563,7 @@ mtk_wed_dma_enable(struct mtk_wed_device *dev)
135 FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
136 0x2));
137
138- for (idx = 0; idx < MTK_WED_RX_QUEUES; idx++)
139+ for (idx = 0; idx < dev->hw->ring_num; idx++)
140 mtk_wed_check_wfdma_rx_fill(dev, idx);
141 }
142 }
143@@ -597,26 +603,31 @@ mtk_wed_dma_disable(struct mtk_wed_device *dev)
144 }
145
146 static void
147-mtk_wed_stop(struct mtk_wed_device *dev)
148+mtk_wed_stop(struct mtk_wed_device *dev, bool reset)
149 {
150- mtk_wed_dma_disable(dev);
151- mtk_wed_set_512_support(dev, false);
152-
153 if (dev->ver > MTK_WED_V1) {
154 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
155 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
156 }
157 mtk_wed_set_ext_int(dev, false);
158
159- wed_clr(dev, MTK_WED_CTRL,
160- MTK_WED_CTRL_WDMA_INT_AGENT_EN |
161- MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
162- MTK_WED_CTRL_WED_TX_BM_EN |
163- MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
164-
165- if (dev->ver > MTK_WED_V1) {
166+ if (!reset) {
167+ mtk_wed_dma_disable(dev);
168+ mtk_wed_set_512_support(dev, false);
169+ if (dev->ver > MTK_WED_V1) {
170+ wed_clr(dev, MTK_WED_CTRL,
171+ MTK_WED_CTRL_RX_RRO_QM_EN |
172+ MTK_WED_CTRL_RX_ROUTE_QM_EN |
173+ MTK_WED_CTRL_WED_RX_BM_EN);
174+ } else {
175+ regmap_write(dev->hw->mirror,
176+ dev->hw->index * 4, 0);
177+ }
178 wed_clr(dev, MTK_WED_CTRL,
179- MTK_WED_CTRL_WED_RX_BM_EN);
180+ MTK_WED_CTRL_WDMA_INT_AGENT_EN |
181+ MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
182+ MTK_WED_CTRL_WED_TX_BM_EN |
183+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
184 }
185
186 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
187@@ -634,16 +645,13 @@ mtk_wed_detach(struct mtk_wed_device *dev)
188
189 mutex_lock(&hw_lock);
190
191- mtk_wed_stop(dev);
192+ mtk_wed_stop(dev, false);
193
194- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
195- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
196+ mtk_wdma_rx_reset(dev);
197
198 mtk_wed_reset(dev, MTK_WED_RESET_WED);
199
200- wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
201- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
202- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
203+ mtk_wdma_tx_reset(dev);
204
205 mtk_wed_free_buffer(dev);
206 mtk_wed_free_tx_rings(dev);
207@@ -653,8 +661,6 @@ mtk_wed_detach(struct mtk_wed_device *dev)
208 mtk_wed_wo_exit(hw);
209 }
210
211- mtk_wdma_rx_reset(dev);
212-
developer144824b2022-11-25 21:27:43 +0800213 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
developerc1b2cd12022-07-28 18:35:24 +0800214 wlan_node = dev->wlan.pci_dev->dev.of_node;
215 if (of_dma_is_coherent(wlan_node))
216@@ -748,7 +754,7 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev)
217 {
218 u32 mask, set;
219
220- mtk_wed_stop(dev);
221+ mtk_wed_stop(dev, false);
222 mtk_wed_reset(dev, MTK_WED_RESET_WED);
223
224 if (dev->ver > MTK_WED_V1)
225@@ -961,44 +967,127 @@ mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size, int scale, bool tx)
226 }
227
228 static u32
229-mtk_wed_check_busy(struct mtk_wed_device *dev)
230+mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
231 {
232- if (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY)
233- return true;
234-
235- if (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) &
236- MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY)
237- return true;
238-
239- if (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY)
240- return true;
241-
242- if (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) &
243- MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
244- return true;
245-
246- if (wdma_r32(dev, MTK_WDMA_GLO_CFG) &
247- MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
248- return true;
249-
250- if (wed_r32(dev, MTK_WED_CTRL) &
251- (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY))
252+ if (wed_r32(dev, reg) & mask)
253 return true;
254
255 return false;
256 }
257
258 static int
259-mtk_wed_poll_busy(struct mtk_wed_device *dev)
260+mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
261 {
262- int sleep = 15000;
263+ int sleep = 1000;
264 int timeout = 100 * sleep;
265 u32 val;
266
267 return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
268- timeout, false, dev);
269+ timeout, false, dev, reg, mask);
developer553bdd92022-08-12 09:58:45 +0800270+}
271+
developerc1b2cd12022-07-28 18:35:24 +0800272+static void
273+mtk_wed_rx_reset(struct mtk_wed_device *dev)
274+{
275+ struct mtk_wed_wo *wo = dev->hw->wed_wo;
276+ u8 state = WO_STATE_SER_RESET;
277+ bool busy = false;
278+ int i;
279+
developer144824b2022-11-25 21:27:43 +0800280+ mtk_wed_mcu_send_msg(wo, MODULE_ID_WO, MTK_WED_WO_CMD_CHANGE_STATE,
developerc1b2cd12022-07-28 18:35:24 +0800281+ &state, sizeof(state), true);
282+
283+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN);
284+ busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
285+ MTK_WED_WPDMA_RX_D_RX_DRV_BUSY);
286+ if (busy) {
287+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
288+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV);
289+ } else {
290+ wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
291+ MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
292+ MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
293+
294+ wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
295+ MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
296+ MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
297+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
298+ MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
299+ MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
300+
301+ wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
302+ }
303+
304+ /* reset rro qm */
305+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
306+ busy = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
307+ MTK_WED_CTRL_RX_RRO_QM_BUSY);
308+ if (busy) {
309+ mtk_wed_reset(dev, MTK_WED_RESET_RX_RRO_QM);
310+ } else {
311+ wed_set(dev, MTK_WED_RROQM_RST_IDX,
312+ MTK_WED_RROQM_RST_IDX_MIOD |
313+ MTK_WED_RROQM_RST_IDX_FDBK);
314+ wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
315+ }
316+
317+ /* reset route qm */
318+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
319+ busy = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
320+ MTK_WED_CTRL_RX_ROUTE_QM_BUSY);
321+ if (busy) {
322+ mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
323+ } else {
324+ wed_set(dev, MTK_WED_RTQM_GLO_CFG,
325+ MTK_WED_RTQM_Q_RST);
326+ }
327+
328+ /* reset tx wdma */
329+ mtk_wdma_tx_reset(dev);
330+
331+ /* reset tx wdma drv */
332+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN);
333+ mtk_wed_poll_busy(dev, MTK_WED_CTRL,
334+ MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
335+ mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
336+
337+ /* reset wed rx dma */
338+ busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
339+ MTK_WED_GLO_CFG_RX_DMA_BUSY);
340+ wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_RX_DMA_EN);
341+ if (busy) {
342+ mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
343+ } else {
344+ wed_set(dev, MTK_WED_RESET_IDX,
345+ MTK_WED_RESET_IDX_RX);
346+ wed_w32(dev, MTK_WED_RESET_IDX, 0);
347+ }
348+
349+ /* reset rx bm */
350+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
351+ mtk_wed_poll_busy(dev, MTK_WED_CTRL,
352+ MTK_WED_CTRL_WED_RX_BM_BUSY);
353+ mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
354+
355+ /* wo change to enable state */
356+ state = WO_STATE_ENABLE;
developer144824b2022-11-25 21:27:43 +0800357+ mtk_wed_mcu_send_msg(wo, MODULE_ID_WO, MTK_WED_WO_CMD_CHANGE_STATE,
developerc1b2cd12022-07-28 18:35:24 +0800358+ &state, sizeof(state), true);
359+
360+ /* wed_rx_ring_reset */
361+ for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++) {
362+ struct mtk_wdma_desc *desc = dev->rx_ring[i].desc;
363+
364+ if (!desc)
365+ continue;
366+
367+ mtk_wed_ring_reset(desc, MTK_WED_RX_RING_SIZE, 1, false);
368+ }
369+
370+ mtk_wed_free_rx_bm(dev);
developer553bdd92022-08-12 09:58:45 +0800371 }
372
developerc1b2cd12022-07-28 18:35:24 +0800373+
374 static void
375 mtk_wed_reset_dma(struct mtk_wed_device *dev)
376 {
377@@ -1012,25 +1101,28 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
378 if (!desc)
379 continue;
380
381- mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE, dev->ver, true);
382+ mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE, 1, true);
383 }
384
385- if (mtk_wed_poll_busy(dev))
386- busy = mtk_wed_check_busy(dev);
387+ /* 1.Reset WED Tx DMA */
388+ wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_EN);
389+ busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_BUSY);
390
391 if (busy) {
392 mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
393 } else {
394 wed_w32(dev, MTK_WED_RESET_IDX,
395- MTK_WED_RESET_IDX_TX |
396- MTK_WED_RESET_IDX_RX);
397+ MTK_WED_RESET_IDX_TX);
398 wed_w32(dev, MTK_WED_RESET_IDX, 0);
399 }
400
401- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
402- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
403+ /* 2. Reset WDMA Rx DMA/Driver_Engine */
404+ busy = !!mtk_wdma_rx_reset(dev);
405
406- mtk_wdma_rx_reset(dev);
407+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
408+ busy = !!(busy ||
409+ mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG,
410+ MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY));
411
412 if (busy) {
413 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
414@@ -1047,15 +1139,30 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
415 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
416 }
417
418+ /* 3. Reset WED WPDMA Tx Driver Engine */
419+ wed_clr(dev, MTK_WED_CTRL,
420+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
421+
422 for (i = 0; i < 100; i++) {
423 val = wed_r32(dev, MTK_WED_TX_BM_INTF);
424 if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
425 break;
426 }
427-
428 mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
429+
430+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_BM_EN);
431 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
432
433+ /* 4. Reset WED WPDMA Tx Driver Engine */
434+ busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
435+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY);
436+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
437+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
438+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
439+
440+ busy = !!(busy ||
441+ mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
442+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY));
443 if (busy) {
444 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
445 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
446@@ -1065,6 +1172,16 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
447 MTK_WED_WPDMA_RESET_IDX_TX |
448 MTK_WED_WPDMA_RESET_IDX_RX);
449 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
450+ if (dev->ver > MTK_WED_V1) {
451+ wed_w32(dev, MTK_WED_RESET_IDX,
452+ MTK_WED_RESET_WPDMA_IDX_RX);
453+ wed_w32(dev, MTK_WED_RESET_IDX, 0);
454+ }
455+ }
456+
457+ if (dev->ver > MTK_WED_V1) {
458+ dev->init_done = false;
459+ mtk_wed_rx_reset(dev);
460 }
461
developer2ed23d42022-08-09 16:20:46 +0800462 }
463@@ -1101,13 +1218,15 @@ mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
464 }
465
466 static int
467-mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
468+mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev,
469+ int idx, int size, bool reset)
470 {
471 struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
472
473- if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
474- dev->ver, true))
475- return -ENOMEM;
476+ if(!reset)
477+ if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
478+ dev->ver, true))
479+ return -ENOMEM;
480
481 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
482 wdma->desc_phys);
483@@ -1124,13 +1243,15 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
developerc1b2cd12022-07-28 18:35:24 +0800484 }
developer2ed23d42022-08-09 16:20:46 +0800485
486 static int
487-mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
488+mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev,
489+ int idx, int size, bool reset)
490 {
491 struct mtk_wed_ring *wdma = &dev->rx_wdma[idx];
492
493- if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
494- dev->ver, true))
495- return -ENOMEM;
496+ if (!reset)
497+ if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
498+ dev->ver, true))
499+ return -ENOMEM;
500
501 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
502 wdma->desc_phys);
503@@ -1140,7 +1261,9 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
504 MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
505 wdma_w32(dev,
506 MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
507-
508+ if (reset)
509+ mtk_wed_ring_reset(wdma->desc, MTK_WED_WDMA_RING_SIZE,
510+ dev->ver, true);
511 if (idx == 0) {
512 wed_w32(dev, MTK_WED_WDMA_RING_TX
513 + MTK_WED_RING_OFS_BASE, wdma->desc_phys);
514@@ -1253,9 +1376,12 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
developerc1b2cd12022-07-28 18:35:24 +0800515 {
516 int i, ret;
517
518+ if (dev->ver > MTK_WED_V1)
519+ ret = mtk_wed_rx_bm_alloc(dev);
520+
521 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
522 if (!dev->tx_wdma[i].desc)
developer2ed23d42022-08-09 16:20:46 +0800523- mtk_wed_wdma_rx_ring_setup(dev, i, 16);
524+ mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
525
526 mtk_wed_hw_init(dev);
527
528@@ -1340,10 +1466,6 @@ mtk_wed_attach(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800529 goto error;
530
531 if (dev->ver > MTK_WED_V1) {
532- ret = mtk_wed_rx_bm_alloc(dev);
533- if (ret)
534- goto error;
535-
536 ret = mtk_wed_rro_alloc(dev);
537 if (ret)
538 goto error;
developer2ed23d42022-08-09 16:20:46 +0800539@@ -1351,6 +1473,10 @@ mtk_wed_attach(struct mtk_wed_device *dev)
540
541 mtk_wed_hw_init_early(dev);
542
543+ init_completion(&dev->fe_reset_done);
544+ init_completion(&dev->wlan_reset_done);
545+ atomic_set(&dev->fe_reset, 0);
546+
547 if (dev->ver == MTK_WED_V1)
548 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
549 BIT(hw->index), 0);
550@@ -1367,7 +1493,8 @@ out:
developerc1b2cd12022-07-28 18:35:24 +0800551 }
552
553 static int
554-mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
555+mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx,
556+ void __iomem *regs, bool reset)
557 {
558 struct mtk_wed_ring *ring = &dev->tx_ring[idx];
559
developer2ed23d42022-08-09 16:20:46 +0800560@@ -1385,10 +1512,12 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
developerc1b2cd12022-07-28 18:35:24 +0800561
562 BUG_ON(idx > ARRAY_SIZE(dev->tx_ring));
563
564- if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE, 1, true))
565- return -ENOMEM;
developer2ed23d42022-08-09 16:20:46 +0800566+ if (!reset)
developerc1b2cd12022-07-28 18:35:24 +0800567+ if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE,
568+ 1, true))
569+ return -ENOMEM;
570
developer2ed23d42022-08-09 16:20:46 +0800571- if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
572+ if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, reset))
573 return -ENOMEM;
developerc1b2cd12022-07-28 18:35:24 +0800574
developer2ed23d42022-08-09 16:20:46 +0800575 ring->reg_base = MTK_WED_RING_TX(idx);
576@@ -1436,21 +1565,24 @@ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
developerc1b2cd12022-07-28 18:35:24 +0800577 }
578
579 static int
580-mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
581+mtk_wed_rx_ring_setup(struct mtk_wed_device *dev,
582+ int idx, void __iomem *regs, bool reset)
583 {
584 struct mtk_wed_ring *ring = &dev->rx_ring[idx];
585
586 BUG_ON(idx > ARRAY_SIZE(dev->rx_ring));
587
developer2ed23d42022-08-09 16:20:46 +0800588+ if (!reset)
developerc1b2cd12022-07-28 18:35:24 +0800589+ if (mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE,
590+ 1, false))
591+ return -ENOMEM;
592
593- if (mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE, 1, false))
594- return -ENOMEM;
595-
596- if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
developer2ed23d42022-08-09 16:20:46 +0800597+ if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, reset))
598 return -ENOMEM;
599
developerc1b2cd12022-07-28 18:35:24 +0800600 ring->reg_base = MTK_WED_RING_RX_DATA(idx);
601 ring->wpdma = regs;
602+ dev->hw->ring_num = idx + 1;
603
604 /* WPDMA -> WED */
605 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
developer2ed23d42022-08-09 16:20:46 +0800606@@ -1492,6 +1624,41 @@ mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
607 wed_w32(dev, MTK_WED_INT_MASK, mask);
608 }
609
610+void mtk_wed_fe_reset(int cmd)
611+{
612+ int i;
613+
614+ for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
615+ struct mtk_wed_hw *hw = hw_list[i];
616+ struct mtk_wed_device *dev;
617+
618+ dev = hw->wed_dev ;
619+ if (!dev)
620+ continue;
621+
622+ switch (cmd) {
623+ case MTK_FE_START_RESET:
624+ pr_info("%s: receive fe reset start event, trigger SER\n", __func__);
625+ atomic_set(&dev->fe_reset, 1);
626+ dev->wlan.ser_trigger(dev);
627+ rtnl_unlock();
628+ wait_for_completion(&dev->wlan_reset_done);
629+ rtnl_lock();
630+
631+ break;
632+ case MTK_FE_RESET_DONE:
633+ pr_info("%s: receive fe reset done event, continue SER\n", __func__);
634+ complete(&dev->fe_reset_done);
635+ break;
636+ default:
637+ break;
638+ }
639+
640+ }
641+
642+ return;
643+}
644+
645 int mtk_wed_flow_add(int index)
646 {
647 struct mtk_wed_hw *hw = hw_list[index];
developerc1b2cd12022-07-28 18:35:24 +0800648diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h
developer2ed23d42022-08-09 16:20:46 +0800649index 8ef5253..f757eac 100644
developerc1b2cd12022-07-28 18:35:24 +0800650--- a/drivers/net/ethernet/mediatek/mtk_wed.h
651+++ b/drivers/net/ethernet/mediatek/mtk_wed.h
652@@ -47,6 +47,7 @@ struct mtk_wed_hw {
653 u32 num_flows;
654 u32 wdma_phy;
655 char dirname[5];
656+ int ring_num;
657 int irq;
658 int index;
659 u32 ver;
developer2ed23d42022-08-09 16:20:46 +0800660@@ -196,5 +197,6 @@ void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
661 int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo,int to_id, int cmd,
662 const void *data, int len, bool wait_resp);
663 int mtk_wed_wo_rx_poll(struct napi_struct *napi, int budget);
664+void mtk_wed_fe_reset(int cmd);
665
666 #endif
developerc1b2cd12022-07-28 18:35:24 +0800667diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
668index 9d021e2..cfcd94f 100644
669--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
670+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
671@@ -38,11 +38,15 @@ struct mtk_wdma_desc {
672
673 #define MTK_WED_RESET 0x008
674 #define MTK_WED_RESET_TX_BM BIT(0)
675+#define MTK_WED_RESET_RX_BM BIT(1)
676 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
677 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
678 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
679+#define MTK_WED_RESET_WPDMA_RX_D_DRV BIT(10)
680 #define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)
681 #define MTK_WED_RESET_WED_TX_DMA BIT(12)
682+#define MTK_WED_RESET_WED_RX_DMA BIT(13)
683+#define MTK_WED_RESET_WDMA_TX_DRV BIT(16)
684 #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
685 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
686 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
687@@ -186,7 +190,12 @@ struct mtk_wdma_desc {
688
689 #define MTK_WED_RESET_IDX 0x20c
690 #define MTK_WED_RESET_IDX_TX GENMASK(3, 0)
691+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
692+#define MTK_WED_RESET_IDX_RX GENMASK(7, 6)
693+#else
694 #define MTK_WED_RESET_IDX_RX GENMASK(17, 16)
695+#endif
696+#define MTK_WED_RESET_WPDMA_IDX_RX GENMASK(31, 30)
697
698 #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)
699 #define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4)
700@@ -300,6 +309,9 @@ struct mtk_wdma_desc {
701
702 #define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c
703 #define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
704+#define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY BIT(1)
705+#define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE BIT(3)
706+#define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE BIT(4)
707 #define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7)
708 #define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24)
709
710diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h
developer2ed23d42022-08-09 16:20:46 +0800711index 9a9cc1b..31f4a26 100644
developerc1b2cd12022-07-28 18:35:24 +0800712--- a/include/linux/soc/mediatek/mtk_wed.h
713+++ b/include/linux/soc/mediatek/mtk_wed.h
developer144824b2022-11-25 21:27:43 +0800714@@ -161,23 +161,27 @@ struct mtk_wed_device {
developer2ed23d42022-08-09 16:20:46 +0800715 void (*release_rx_buf)(struct mtk_wed_device *wed);
developer144824b2022-11-25 21:27:43 +0800716 void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
717 struct mtk_wed_wo_rx_stats *stats);
developer2ed23d42022-08-09 16:20:46 +0800718+ void (*ser_trigger)(struct mtk_wed_device *wed);
719 } wlan;
720+ struct completion fe_reset_done;
721+ struct completion wlan_reset_done;
722+ atomic_t fe_reset;
723 #endif
724 };
725
developerc1b2cd12022-07-28 18:35:24 +0800726 struct mtk_wed_ops {
727 int (*attach)(struct mtk_wed_device *dev);
728 int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,
729- void __iomem *regs);
730+ void __iomem *regs, bool reset);
731 int (*txfree_ring_setup)(struct mtk_wed_device *dev,
732 void __iomem *regs);
733 int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
734- void __iomem *regs);
735+ void __iomem *regs, bool reset);
736 int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
737 void *data, int len);
738 void (*detach)(struct mtk_wed_device *dev);
739
740- void (*stop)(struct mtk_wed_device *dev);
741+ void (*stop)(struct mtk_wed_device *dev, bool reset);
742 void (*start)(struct mtk_wed_device *dev, u32 irq_mask);
743 void (*reset_dma)(struct mtk_wed_device *dev);
744
developer144824b2022-11-25 21:27:43 +0800745@@ -226,12 +230,13 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800746 #define mtk_wed_device_active(_dev) !!(_dev)->ops
747 #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
748 #define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)
749-#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \
750- (_dev)->ops->tx_ring_setup(_dev, _ring, _regs)
751+#define mtk_wed_device_stop(_dev, _reset) (_dev)->ops->stop(_dev, _reset)
752+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) \
753+ (_dev)->ops->tx_ring_setup(_dev, _ring, _regs, _reset)
754 #define mtk_wed_device_txfree_ring_setup(_dev, _regs) \
755 (_dev)->ops->txfree_ring_setup(_dev, _regs)
756-#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) \
757- (_dev)->ops->rx_ring_setup(_dev, _ring, _regs)
758+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) \
759+ (_dev)->ops->rx_ring_setup(_dev, _ring, _regs, _reset)
760 #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
761 (_dev)->ops->msg_update(_dev, _id, _msg, _len)
762 #define mtk_wed_device_reg_read(_dev, _reg) \
developer144824b2022-11-25 21:27:43 +0800763@@ -242,6 +247,8 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800764 (_dev)->ops->irq_get(_dev, _mask)
765 #define mtk_wed_device_irq_set_mask(_dev, _mask) \
766 (_dev)->ops->irq_set_mask(_dev, _mask)
767+#define mtk_wed_device_dma_reset(_dev) \
768+ (_dev)->ops->reset_dma(_dev)
769 #define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
770 (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
771 #else
developer144824b2022-11-25 21:27:43 +0800772@@ -251,14 +258,15 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
developerc1b2cd12022-07-28 18:35:24 +0800773 }
774 #define mtk_wed_device_detach(_dev) do {} while (0)
775 #define mtk_wed_device_start(_dev, _mask) do {} while (0)
776-#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV
777+#define mtk_wed_device_stop(_dev, _reset) do {} while (0)
778+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
779 #define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV
780-#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) -ENODEV
781-#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV
782+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
783 #define mtk_wed_device_reg_read(_dev, _reg) 0
784 #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
785 #define mtk_wed_device_irq_get(_dev, _mask) 0
786 #define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)
787+#define mtk_wed_device_dma_reset(_dev) do {} while (0)
788 #define mtk_wed_device_ppe_check(_dev, _hash) do {} while (0)
789 #endif
790
791--
7922.18.0
793