blob: ca84955a6027794901bff00275059317f8973a80 [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +08001From 31b16ccb455139f23e4989c0795564350774c8c6 Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:22 +0800
4Subject: [PATCH]
5 [adv-feature][999-2501-cpufreq-Enable-clocks-and-regulators.patch]
6
7---
8 drivers/cpufreq/mediatek-cpufreq.c | 41 +++++++++++++++++++++++++++---
9 1 file changed, 37 insertions(+), 4 deletions(-)
10
developer2cdaeb12022-10-04 20:25:05 +080011diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
developer5d148cb2023-06-02 13:08:11 +080012index 03bb7b58d..010a947a6 100644
developer2cdaeb12022-10-04 20:25:05 +080013--- a/drivers/cpufreq/mediatek-cpufreq.c
14+++ b/drivers/cpufreq/mediatek-cpufreq.c
15@@ -351,6 +351,12 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
16 goto out_free_resources;
17 }
18
19+ ret = regulator_enable(proc_reg);
20+ if (ret) {
21+ dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
22+ goto out_free_resources;
23+ }
24+
25 /* Both presence and absence of sram regulator are valid cases. */
26 sram_reg = regulator_get_exclusive(cpu_dev, "sram");
27
28@@ -368,13 +374,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
29 goto out_free_resources;
30 }
31
32+ ret = clk_prepare_enable(cpu_clk);
33+ if (ret)
34+ goto out_free_opp_table;
35+
36+ ret = clk_prepare_enable(inter_clk);
37+ if (ret)
38+ goto out_disable_mux_clock;
39+
40 /* Search a safe voltage for intermediate frequency. */
41 rate = clk_get_rate(inter_clk);
42 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
43 if (IS_ERR(opp)) {
44 pr_err("failed to get intermediate opp for cpu%d\n", cpu);
45 ret = PTR_ERR(opp);
46- goto out_free_opp_table;
47+ goto out_disable_inter_clock;
48 }
49 info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
50 dev_pm_opp_put(opp);
51@@ -393,10 +407,23 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
52
53 return 0;
54
55+out_disable_inter_clock:
56+ if(!IS_ERR(inter_clk))
57+ clk_disable_unprepare(inter_clk);
58+
59+out_disable_mux_clock:
60+ if(!IS_ERR(cpu_clk))
61+ clk_disable_unprepare(cpu_clk);
62+
63 out_free_opp_table:
64 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
65
66 out_free_resources:
67+ if (!IS_ERR(proc_reg)) {
68+ if (regulator_is_enabled(proc_reg))
69+ regulator_disable(proc_reg);
70+ }
71+
72 if (!IS_ERR(proc_reg))
73 regulator_put(proc_reg);
74 if (!IS_ERR(sram_reg))
75@@ -411,14 +438,20 @@ out_free_resources:
76
77 static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
78 {
79- if (!IS_ERR(info->proc_reg))
80+ if (!IS_ERR(info->proc_reg)){
81+ regulator_disable(info->proc_reg);
82 regulator_put(info->proc_reg);
83+ }
84 if (!IS_ERR(info->sram_reg))
85 regulator_put(info->sram_reg);
86- if (!IS_ERR(info->cpu_clk))
87+ if (!IS_ERR(info->cpu_clk)){
88+ clk_disable_unprepare(info->cpu_clk);
89 clk_put(info->cpu_clk);
90- if (!IS_ERR(info->inter_clk))
91+ }
92+ if (!IS_ERR(info->inter_clk)){
93+ clk_disable_unprepare(info->inter_clk);
94 clk_put(info->inter_clk);
95+ }
96
97 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
98 }
developer5d148cb2023-06-02 13:08:11 +080099--
1002.34.1
101