[][openwrt][update the patches in accordance with the new naming rules]
[Description]
Change all mtk patches in accordance with the new naming rules
"999-20xx-" : Basic Part
"999-21xx-" : Slow Speed I/O
"999-22xx-" : Slow Speed I/O
"999-23xx-" : SPI & Storage
"999-24xx-" : SPI & Storage
"999-25xx-" : Advanced features
"999-26xx-" : High Speed I/O
"999-27xx-" : Networking
"999-28xx-" : MISC
"999-29xx-" : Uncategorized
[Release-log]
N/A
Change-Id: I245da3b0e5b7299b42473c20cc6f0899cffc1ad2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7530987
diff --git a/target/linux/mediatek/patches-5.4/999-2501-cpufreq-Enable-clocks-and-regulators.patch b/target/linux/mediatek/patches-5.4/999-2501-cpufreq-Enable-clocks-and-regulators.patch
new file mode 100644
index 0000000..ca84955
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/999-2501-cpufreq-Enable-clocks-and-regulators.patch
@@ -0,0 +1,101 @@
+From 31b16ccb455139f23e4989c0795564350774c8c6 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 2 Jun 2023 13:06:22 +0800
+Subject: [PATCH]
+ [adv-feature][999-2501-cpufreq-Enable-clocks-and-regulators.patch]
+
+---
+ drivers/cpufreq/mediatek-cpufreq.c | 41 +++++++++++++++++++++++++++---
+ 1 file changed, 37 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
+index 03bb7b58d..010a947a6 100644
+--- a/drivers/cpufreq/mediatek-cpufreq.c
++++ b/drivers/cpufreq/mediatek-cpufreq.c
+@@ -351,6 +351,12 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
+ goto out_free_resources;
+ }
+
++ ret = regulator_enable(proc_reg);
++ if (ret) {
++ dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
++ goto out_free_resources;
++ }
++
+ /* Both presence and absence of sram regulator are valid cases. */
+ sram_reg = regulator_get_exclusive(cpu_dev, "sram");
+
+@@ -368,13 +374,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
+ goto out_free_resources;
+ }
+
++ ret = clk_prepare_enable(cpu_clk);
++ if (ret)
++ goto out_free_opp_table;
++
++ ret = clk_prepare_enable(inter_clk);
++ if (ret)
++ goto out_disable_mux_clock;
++
+ /* Search a safe voltage for intermediate frequency. */
+ rate = clk_get_rate(inter_clk);
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
+ if (IS_ERR(opp)) {
+ pr_err("failed to get intermediate opp for cpu%d\n", cpu);
+ ret = PTR_ERR(opp);
+- goto out_free_opp_table;
++ goto out_disable_inter_clock;
+ }
+ info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+@@ -393,10 +407,23 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
+
+ return 0;
+
++out_disable_inter_clock:
++ if(!IS_ERR(inter_clk))
++ clk_disable_unprepare(inter_clk);
++
++out_disable_mux_clock:
++ if(!IS_ERR(cpu_clk))
++ clk_disable_unprepare(cpu_clk);
++
+ out_free_opp_table:
+ dev_pm_opp_of_cpumask_remove_table(&info->cpus);
+
+ out_free_resources:
++ if (!IS_ERR(proc_reg)) {
++ if (regulator_is_enabled(proc_reg))
++ regulator_disable(proc_reg);
++ }
++
+ if (!IS_ERR(proc_reg))
+ regulator_put(proc_reg);
+ if (!IS_ERR(sram_reg))
+@@ -411,14 +438,20 @@ out_free_resources:
+
+ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
+ {
+- if (!IS_ERR(info->proc_reg))
++ if (!IS_ERR(info->proc_reg)){
++ regulator_disable(info->proc_reg);
+ regulator_put(info->proc_reg);
++ }
+ if (!IS_ERR(info->sram_reg))
+ regulator_put(info->sram_reg);
+- if (!IS_ERR(info->cpu_clk))
++ if (!IS_ERR(info->cpu_clk)){
++ clk_disable_unprepare(info->cpu_clk);
+ clk_put(info->cpu_clk);
+- if (!IS_ERR(info->inter_clk))
++ }
++ if (!IS_ERR(info->inter_clk)){
++ clk_disable_unprepare(info->inter_clk);
+ clk_put(info->inter_clk);
++ }
+
+ dev_pm_opp_of_cpumask_remove_table(&info->cpus);
+ }
+--
+2.34.1
+