blob: 50bdbd8c4dfdeea87372e397a73ec95e4f202d62 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018-2019 MediaTek Inc.
3
4/* A library for MediaTek SGMII circuit
5 *
6 * Author: Sean Wang <sean.wang@mediatek.com>
7 *
8 */
9
10#include <linux/mfd/syscon.h>
11#include <linux/of.h>
12#include <linux/regmap.h>
13
14#include "mtk_eth_soc.h"
15
16int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
17{
18 struct device_node *np;
19 int i;
20
21 ss->ana_rgc3 = ana_rgc3;
22
23 for (i = 0; i < MTK_MAX_DEVS; i++) {
24 np = of_parse_phandle(r, "mediatek,sgmiisys", i);
25 if (!np)
26 break;
27
28 ss->regmap[i] = syscon_node_to_regmap(np);
29 if (IS_ERR(ss->regmap[i]))
30 return PTR_ERR(ss->regmap[i]);
developerf8ac94a2021-07-29 16:40:01 +080031
32 ss->flags[i] &= ~(MTK_SGMII_PN_SWAP);
33 if (of_property_read_bool(np, "pn_swap"))
34 ss->flags[i] |= MTK_SGMII_PN_SWAP;
developerfd40db22021-04-29 10:08:25 +080035 }
36
37 return 0;
38}
39
developerfb556ca2021-10-13 10:52:09 +080040int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, unsigned int id)
developerfd40db22021-04-29 10:08:25 +080041{
42 unsigned int val;
43
44 if (!ss->regmap[id])
45 return -EINVAL;
46
47 /* Setup the link timer and QPHY power up inside SGMIISYS */
48 regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
49 SGMII_LINK_TIMER_DEFAULT);
50
51 regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
52 val |= SGMII_REMOTE_FAULT_DIS;
53 regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
54
55 regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
56 val |= SGMII_AN_RESTART;
57 regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
58
developerf8ac94a2021-07-29 16:40:01 +080059 if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP))
60 regmap_update_bits(ss->regmap[id], SGMSYS_QPHY_WRAP_CTRL,
61 SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX);
62
developerfd40db22021-04-29 10:08:25 +080063 regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
64 val &= ~SGMII_PHYA_PWD;
65 regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
66
67 return 0;
68}
69
developerfb556ca2021-10-13 10:52:09 +080070int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, unsigned int id,
developerfd40db22021-04-29 10:08:25 +080071 const struct phylink_link_state *state)
72{
73 unsigned int val;
74
75 if (!ss->regmap[id])
76 return -EINVAL;
77
78 regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
79 val &= ~RG_PHY_SPEED_MASK;
80 if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
81 val |= RG_PHY_SPEED_3_125G;
82 regmap_write(ss->regmap[id], ss->ana_rgc3, val);
83
84 /* Disable SGMII AN */
85 regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
86 val &= ~SGMII_AN_ENABLE;
87 regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
88
89 /* SGMII force mode setting */
90 regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
91 val &= ~SGMII_IF_MODE_MASK;
92
93 switch (state->speed) {
94 case SPEED_10:
95 val |= SGMII_SPEED_10;
96 break;
97 case SPEED_100:
98 val |= SGMII_SPEED_100;
99 break;
100 case SPEED_2500:
101 case SPEED_1000:
102 val |= SGMII_SPEED_1000;
103 break;
104 };
105
106 if (state->duplex == DUPLEX_FULL)
107 val |= SGMII_DUPLEX_FULL;
108
109 regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
110
developerf8ac94a2021-07-29 16:40:01 +0800111 if(MTK_HAS_FLAGS(ss->flags[id],MTK_SGMII_PN_SWAP))
112 regmap_update_bits(ss->regmap[id], SGMSYS_QPHY_WRAP_CTRL,
113 SGMII_PN_SWAP_MASK, SGMII_PN_SWAP_TX_RX);
developerfd40db22021-04-29 10:08:25 +0800114 /* Release PHYA power down state */
115 regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
116 val &= ~SGMII_PHYA_PWD;
117 regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
118
119 return 0;
120}
121
122void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
123{
124 struct mtk_sgmii *ss = eth->sgmii;
125 unsigned int val, sid;
126
127 /* Decide how GMAC and SGMIISYS be mapped */
128 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
129 0 : mac_id;
130
131 if (!ss->regmap[sid])
132 return;
133
134 regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val);
135 val |= SGMII_AN_RESTART;
136 regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val);
137}