developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986b.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7986b RFB"; |
| 5 | compatible = "mediatek,mt7986b-rfb"; |
| 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000"; |
| 9 | }; |
| 10 | |
| 11 | memory { |
| 12 | // fpga ddr2: 128MB*2 |
| 13 | reg = <0 0x40000000 0 0x10000000>; |
| 14 | }; |
developer | c20f345 | 2021-05-26 17:27:35 +0800 | [diff] [blame] | 15 | |
| 16 | nmbm_snfi { |
| 17 | compatible = "generic,nmbm"; |
| 18 | |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <1>; |
| 21 | |
| 22 | lower-mtd-device = <&snand>; |
| 23 | forced-create; |
developer | c9faf4a | 2021-06-17 09:22:21 +0800 | [diff] [blame] | 24 | empty-page-ecc-protected; |
developer | c20f345 | 2021-05-26 17:27:35 +0800 | [diff] [blame] | 25 | |
| 26 | partitions { |
| 27 | compatible = "fixed-partitions"; |
| 28 | #address-cells = <1>; |
| 29 | #size-cells = <1>; |
| 30 | |
| 31 | partition@0 { |
| 32 | label = "BL2"; |
| 33 | reg = <0x00000 0x0100000>; |
| 34 | read-only; |
| 35 | }; |
| 36 | |
| 37 | partition@100000 { |
| 38 | label = "u-boot-env"; |
| 39 | reg = <0x0100000 0x0080000>; |
| 40 | }; |
| 41 | |
| 42 | partition@180000 { |
| 43 | label = "Factory"; |
| 44 | reg = <0x180000 0x0200000>; |
| 45 | }; |
| 46 | |
| 47 | partition@380000 { |
| 48 | label = "FIP"; |
| 49 | reg = <0x380000 0x0200000>; |
| 50 | }; |
| 51 | |
| 52 | partition@580000 { |
| 53 | label = "ubi"; |
| 54 | reg = <0x580000 0x4000000>; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
developer | 86fc2a7 | 2021-06-23 17:30:23 +0800 | [diff] [blame] | 58 | |
| 59 | nmbm_spim_nand { |
| 60 | compatible = "generic,nmbm"; |
| 61 | |
| 62 | #address-cells = <1>; |
| 63 | #size-cells = <1>; |
| 64 | |
| 65 | lower-mtd-device = <&spi_nand>; |
| 66 | forced-create; |
| 67 | |
| 68 | partitions { |
| 69 | compatible = "fixed-partitions"; |
| 70 | #address-cells = <1>; |
| 71 | #size-cells = <1>; |
| 72 | |
| 73 | partition@0 { |
| 74 | label = "BL2"; |
| 75 | reg = <0x00000 0x0100000>; |
| 76 | read-only; |
| 77 | }; |
| 78 | |
| 79 | partition@100000 { |
| 80 | label = "u-boot-env"; |
| 81 | reg = <0x0100000 0x0080000>; |
| 82 | }; |
| 83 | |
| 84 | partition@180000 { |
| 85 | label = "Factory"; |
| 86 | reg = <0x180000 0x0200000>; |
| 87 | }; |
| 88 | |
| 89 | partition@380000 { |
| 90 | label = "FIP"; |
| 91 | reg = <0x380000 0x0200000>; |
| 92 | }; |
| 93 | |
| 94 | partition@580000 { |
| 95 | label = "ubi"; |
| 96 | reg = <0x580000 0x4000000>; |
| 97 | }; |
| 98 | }; |
| 99 | }; |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame^] | 100 | |
| 101 | reg_3p3v: regulator-3p3v { |
| 102 | compatible = "regulator-fixed"; |
| 103 | regulator-name = "fixed-3.3V"; |
| 104 | regulator-min-microvolt = <3300000>; |
| 105 | regulator-max-microvolt = <3300000>; |
| 106 | regulator-boot-on; |
| 107 | regulator-always-on; |
| 108 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | &uart0 { |
| 112 | status = "okay"; |
| 113 | }; |
| 114 | |
| 115 | &watchdog { |
| 116 | status = "okay"; |
| 117 | }; |
| 118 | |
| 119 | ð { |
| 120 | status = "okay"; |
| 121 | |
| 122 | gmac0: mac@0 { |
| 123 | compatible = "mediatek,eth-mac"; |
| 124 | reg = <0>; |
| 125 | phy-mode = "2500base-x"; |
| 126 | |
| 127 | fixed-link { |
| 128 | speed = <2500>; |
| 129 | full-duplex; |
| 130 | pause; |
| 131 | }; |
| 132 | }; |
| 133 | |
| 134 | gmac1: mac@1 { |
| 135 | compatible = "mediatek,eth-mac"; |
| 136 | reg = <1>; |
| 137 | phy-mode = "2500base-x"; |
| 138 | |
| 139 | fixed-link { |
| 140 | speed = <2500>; |
| 141 | full-duplex; |
| 142 | pause; |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | mdio: mdio-bus { |
| 147 | #address-cells = <1>; |
| 148 | #size-cells = <0>; |
| 149 | |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 150 | phy5: phy@5 { |
| 151 | compatible = "ethernet-phy-id67c9.de0a"; |
| 152 | reg = <5>; |
| 153 | reset-gpios = <&pio 6 1>; |
| 154 | reset-deassert-us = <20000>; |
| 155 | phy-mode = "2500base-x"; |
| 156 | }; |
| 157 | |
| 158 | phy6: phy@6 { |
| 159 | compatible = "ethernet-phy-id67c9.de0a"; |
| 160 | reg = <6>; |
| 161 | phy-mode = "2500base-x"; |
| 162 | }; |
| 163 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 164 | switch@0 { |
| 165 | compatible = "mediatek,mt7531"; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 166 | reg = <31>; |
developer | 5105943 | 2021-05-03 16:01:06 +0800 | [diff] [blame] | 167 | reset-gpios = <&pio 5 0>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 168 | |
| 169 | ports { |
| 170 | #address-cells = <1>; |
| 171 | #size-cells = <0>; |
| 172 | |
| 173 | port@0 { |
| 174 | reg = <0>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 175 | label = "lan0"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | port@1 { |
| 179 | reg = <1>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 180 | label = "lan1"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 181 | }; |
| 182 | |
| 183 | port@2 { |
| 184 | reg = <2>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 185 | label = "lan2"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | port@3 { |
| 189 | reg = <3>; |
developer | c0f3c7f | 2021-05-17 11:48:36 +0800 | [diff] [blame] | 190 | label = "lan3"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 191 | }; |
| 192 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 193 | port@6 { |
| 194 | reg = <6>; |
| 195 | label = "cpu"; |
| 196 | ethernet = <&gmac0>; |
| 197 | phy-mode = "2500base-x"; |
| 198 | |
| 199 | fixed-link { |
| 200 | speed = <2500>; |
| 201 | full-duplex; |
| 202 | pause; |
| 203 | }; |
| 204 | }; |
| 205 | }; |
| 206 | }; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | &hnat { |
developer | e576351 | 2021-05-21 01:04:58 +0800 | [diff] [blame] | 211 | mtketh-wan = "eth1"; |
developer | d7edc13 | 2021-05-06 13:49:50 +0800 | [diff] [blame] | 212 | mtketh-lan = "lan"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 213 | mtketh-max-gmac = <2>; |
| 214 | status = "okay"; |
| 215 | }; |
| 216 | |
| 217 | &spi0 { |
| 218 | pinctrl-names = "default"; |
| 219 | pinctrl-0 = <&spi_flash_pins>; |
| 220 | cs-gpios = <0>, <0>; |
| 221 | status = "okay"; |
| 222 | spi_nor@0 { |
| 223 | #address-cells = <1>; |
| 224 | #size-cells = <1>; |
| 225 | compatible = "jedec,spi-nor"; |
| 226 | reg = <0>; |
| 227 | spi-max-frequency = <20000000>; |
| 228 | spi-tx-buswidth = <4>; |
| 229 | spi-rx-buswidth = <4>; |
| 230 | |
| 231 | partition@00000 { |
| 232 | label = "BL2"; |
| 233 | reg = <0x00000 0x0040000>; |
| 234 | }; |
| 235 | partition@40000 { |
| 236 | label = "u-boot-env"; |
| 237 | reg = <0x40000 0x0010000>; |
| 238 | }; |
developer | 298705c | 2021-06-05 18:48:19 +0800 | [diff] [blame] | 239 | factory: partition@50000 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 240 | label = "Factory"; |
| 241 | reg = <0x50000 0x00B0000>; |
| 242 | }; |
| 243 | partition@100000 { |
| 244 | label = "FIP"; |
| 245 | reg = <0x100000 0x0080000>; |
| 246 | }; |
| 247 | partition@180000 { |
| 248 | label = "firmware"; |
| 249 | reg = <0x180000 0xE00000>; |
| 250 | }; |
| 251 | }; |
developer | 86fc2a7 | 2021-06-23 17:30:23 +0800 | [diff] [blame] | 252 | spi_nand: spi_nand@1 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 253 | #address-cells = <1>; |
| 254 | #size-cells = <1>; |
| 255 | compatible = "spi-nand"; |
| 256 | reg = <1>; |
| 257 | spi-max-frequency = <20000000>; |
| 258 | spi-tx-buswidth = <4>; |
| 259 | spi-rx-buswidth = <4>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 260 | }; |
| 261 | }; |
| 262 | |
| 263 | &snand { |
| 264 | pinctrl-names = "default"; |
| 265 | /* pin shared with spic */ |
| 266 | pinctrl-0 = <&snfi_pins>; |
| 267 | status = "okay"; |
| 268 | mediatek,quad-spi; |
| 269 | |
| 270 | partitions { |
| 271 | compatible = "fixed-partitions"; |
| 272 | #address-cells = <1>; |
| 273 | #size-cells = <1>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 274 | }; |
| 275 | }; |
| 276 | |
| 277 | &spi1 { |
| 278 | pinctrl-names = "default"; |
| 279 | /* pin shared with snfi */ |
| 280 | pinctrl-0 = <&spic_pins>; |
| 281 | status = "okay"; |
| 282 | }; |
| 283 | |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame^] | 284 | &mmc0 { |
| 285 | pinctrl-names = "default", "state_uhs"; |
| 286 | pinctrl-0 = <&mmc0_pins_default>; |
| 287 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 288 | bus-width = <8>; |
| 289 | max-frequency = <50000000>; |
| 290 | cap-mmc-highspeed; |
| 291 | vmmc-supply = <®_3p3v>; |
| 292 | vqmmc-supply = <®_3p3v>; |
| 293 | non-removable; |
| 294 | status = "okay"; |
| 295 | }; |
| 296 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 297 | &pio { |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 298 | spi_flash_pins: spi-flash-pins-33-to-38 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 299 | mux { |
| 300 | function = "flash"; |
| 301 | groups = "spi0", "spi0_wp_hold"; |
| 302 | }; |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 303 | conf-pu { |
| 304 | pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; |
| 305 | drive-strength = <MTK_DRIVE_8mA>; |
| 306 | mediatek,pull-up-adv = <0>; /* bias-disable */ |
| 307 | }; |
| 308 | conf-pd { |
| 309 | pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; |
| 310 | drive-strength = <MTK_DRIVE_8mA>; |
| 311 | mediatek,pull-down-adv = <0>; /* bias-disable */ |
| 312 | }; |
| 313 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 314 | }; |
| 315 | |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 316 | snfi_pins: snfi-pins-23-to-28 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 317 | mux { |
| 318 | function = "flash"; |
| 319 | groups = "snfi"; |
| 320 | }; |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 321 | conf-clk { |
| 322 | pins = "SPI0_CLK"; |
| 323 | drive-strength = <MTK_DRIVE_8mA>; |
| 324 | mediatek,pull-down-adv = <0>; /* bias-disable */ |
| 325 | }; |
| 326 | conf-pu { |
| 327 | pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; |
| 328 | drive-strength = <MTK_DRIVE_6mA>; |
| 329 | mediatek,pull-up-adv = <0>; /* bias-disable */ |
| 330 | }; |
| 331 | conf-pd { |
| 332 | pins = "SPI0_MOSI", "SPI0_MISO"; |
| 333 | drive-strength = <MTK_DRIVE_6mA>; |
| 334 | mediatek,pull-down-adv = <0>; /* bias-disable */ |
| 335 | }; |
| 336 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | spic_pins: spi1-pins { |
| 340 | mux { |
| 341 | function = "spi"; |
developer | 19d22f6 | 2021-05-27 17:36:23 +0800 | [diff] [blame] | 342 | groups = "spi1_2"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 343 | }; |
| 344 | }; |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame^] | 345 | |
| 346 | mmc0_pins_default: mmc0-pins-22-to-32-default { |
| 347 | mux { |
| 348 | function = "flash"; |
| 349 | groups = "emmc_45"; |
| 350 | }; |
| 351 | conf-cmd-dat { |
| 352 | pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", |
| 353 | "SPI0_CS", "SPI0_HOLD", "SPI0_WP", |
| 354 | "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; |
| 355 | input-enable; |
| 356 | drive-strength = <MTK_DRIVE_4mA>; |
| 357 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 358 | }; |
| 359 | conf-clk { |
| 360 | pins = "SPI1_CS"; |
| 361 | drive-strength = <MTK_DRIVE_6mA>; |
| 362 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 363 | }; |
| 364 | conf-rst { |
| 365 | pins = "PWM1"; |
| 366 | drive-strength = <MTK_DRIVE_4mA>; |
| 367 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 368 | }; |
| 369 | }; |
| 370 | |
| 371 | mmc0_pins_uhs: mmc0-pins-22-to-32-uhs { |
| 372 | mux { |
| 373 | function = "flash"; |
| 374 | groups = "emmc_45"; |
| 375 | }; |
| 376 | conf-cmd-dat { |
| 377 | pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", |
| 378 | "SPI0_CS", "SPI0_HOLD", "SPI0_WP", |
| 379 | "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; |
| 380 | input-enable; |
| 381 | drive-strength = <MTK_DRIVE_4mA>; |
| 382 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 383 | }; |
| 384 | conf-clk { |
| 385 | pins = "SPI1_CS"; |
| 386 | drive-strength = <MTK_DRIVE_6mA>; |
| 387 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 388 | }; |
| 389 | conf-rst { |
| 390 | pins = "PWM1"; |
| 391 | drive-strength = <MTK_DRIVE_4mA>; |
| 392 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 393 | }; |
| 394 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 395 | }; |