| /dts-v1/; |
| #include "mt7986b.dtsi" |
| / { |
| model = "MediaTek MT7986b RFB"; |
| compatible = "mediatek,mt7986b-rfb"; |
| chosen { |
| bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| earlycon=uart8250,mmio32,0x11002000"; |
| }; |
| |
| memory { |
| // fpga ddr2: 128MB*2 |
| reg = <0 0x40000000 0 0x10000000>; |
| }; |
| |
| nmbm_snfi { |
| compatible = "generic,nmbm"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| lower-mtd-device = <&snand>; |
| forced-create; |
| empty-page-ecc-protected; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "BL2"; |
| reg = <0x00000 0x0100000>; |
| read-only; |
| }; |
| |
| partition@100000 { |
| label = "u-boot-env"; |
| reg = <0x0100000 0x0080000>; |
| }; |
| |
| partition@180000 { |
| label = "Factory"; |
| reg = <0x180000 0x0200000>; |
| }; |
| |
| partition@380000 { |
| label = "FIP"; |
| reg = <0x380000 0x0200000>; |
| }; |
| |
| partition@580000 { |
| label = "ubi"; |
| reg = <0x580000 0x4000000>; |
| }; |
| }; |
| }; |
| |
| nmbm_spim_nand { |
| compatible = "generic,nmbm"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| lower-mtd-device = <&spi_nand>; |
| forced-create; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "BL2"; |
| reg = <0x00000 0x0100000>; |
| read-only; |
| }; |
| |
| partition@100000 { |
| label = "u-boot-env"; |
| reg = <0x0100000 0x0080000>; |
| }; |
| |
| partition@180000 { |
| label = "Factory"; |
| reg = <0x180000 0x0200000>; |
| }; |
| |
| partition@380000 { |
| label = "FIP"; |
| reg = <0x380000 0x0200000>; |
| }; |
| |
| partition@580000 { |
| label = "ubi"; |
| reg = <0x580000 0x4000000>; |
| }; |
| }; |
| }; |
| |
| reg_3p3v: regulator-3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "fixed-3.3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| |
| &uart0 { |
| status = "okay"; |
| }; |
| |
| &watchdog { |
| status = "okay"; |
| }; |
| |
| ð { |
| status = "okay"; |
| |
| gmac0: mac@0 { |
| compatible = "mediatek,eth-mac"; |
| reg = <0>; |
| phy-mode = "2500base-x"; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| |
| gmac1: mac@1 { |
| compatible = "mediatek,eth-mac"; |
| reg = <1>; |
| phy-mode = "2500base-x"; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| |
| mdio: mdio-bus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| phy5: phy@5 { |
| compatible = "ethernet-phy-id67c9.de0a"; |
| reg = <5>; |
| reset-gpios = <&pio 6 1>; |
| reset-deassert-us = <20000>; |
| phy-mode = "2500base-x"; |
| }; |
| |
| phy6: phy@6 { |
| compatible = "ethernet-phy-id67c9.de0a"; |
| reg = <6>; |
| phy-mode = "2500base-x"; |
| }; |
| |
| switch@0 { |
| compatible = "mediatek,mt7531"; |
| reg = <31>; |
| reset-gpios = <&pio 5 0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| label = "lan0"; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| label = "lan1"; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| label = "lan2"; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| label = "lan3"; |
| }; |
| |
| port@6 { |
| reg = <6>; |
| label = "cpu"; |
| ethernet = <&gmac0>; |
| phy-mode = "2500base-x"; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| &hnat { |
| mtketh-wan = "eth1"; |
| mtketh-lan = "lan"; |
| mtketh-max-gmac = <2>; |
| status = "okay"; |
| }; |
| |
| &spi0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_flash_pins>; |
| cs-gpios = <0>, <0>; |
| status = "okay"; |
| spi_nor@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <20000000>; |
| spi-tx-buswidth = <4>; |
| spi-rx-buswidth = <4>; |
| |
| partition@00000 { |
| label = "BL2"; |
| reg = <0x00000 0x0040000>; |
| }; |
| partition@40000 { |
| label = "u-boot-env"; |
| reg = <0x40000 0x0010000>; |
| }; |
| factory: partition@50000 { |
| label = "Factory"; |
| reg = <0x50000 0x00B0000>; |
| }; |
| partition@100000 { |
| label = "FIP"; |
| reg = <0x100000 0x0080000>; |
| }; |
| partition@180000 { |
| label = "firmware"; |
| reg = <0x180000 0xE00000>; |
| }; |
| }; |
| spi_nand: spi_nand@1 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spi-nand"; |
| reg = <1>; |
| spi-max-frequency = <20000000>; |
| spi-tx-buswidth = <4>; |
| spi-rx-buswidth = <4>; |
| }; |
| }; |
| |
| &snand { |
| pinctrl-names = "default"; |
| /* pin shared with spic */ |
| pinctrl-0 = <&snfi_pins>; |
| status = "okay"; |
| mediatek,quad-spi; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| }; |
| |
| &spi1 { |
| pinctrl-names = "default"; |
| /* pin shared with snfi */ |
| pinctrl-0 = <&spic_pins>; |
| status = "okay"; |
| }; |
| |
| &mmc0 { |
| pinctrl-names = "default", "state_uhs"; |
| pinctrl-0 = <&mmc0_pins_default>; |
| pinctrl-1 = <&mmc0_pins_uhs>; |
| bus-width = <8>; |
| max-frequency = <50000000>; |
| cap-mmc-highspeed; |
| vmmc-supply = <®_3p3v>; |
| vqmmc-supply = <®_3p3v>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &pio { |
| spi_flash_pins: spi-flash-pins-33-to-38 { |
| mux { |
| function = "flash"; |
| groups = "spi0", "spi0_wp_hold"; |
| }; |
| conf-pu { |
| pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; |
| drive-strength = <MTK_DRIVE_8mA>; |
| mediatek,pull-up-adv = <0>; /* bias-disable */ |
| }; |
| conf-pd { |
| pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; |
| drive-strength = <MTK_DRIVE_8mA>; |
| mediatek,pull-down-adv = <0>; /* bias-disable */ |
| }; |
| |
| }; |
| |
| snfi_pins: snfi-pins-23-to-28 { |
| mux { |
| function = "flash"; |
| groups = "snfi"; |
| }; |
| conf-clk { |
| pins = "SPI0_CLK"; |
| drive-strength = <MTK_DRIVE_8mA>; |
| mediatek,pull-down-adv = <0>; /* bias-disable */ |
| }; |
| conf-pu { |
| pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; |
| drive-strength = <MTK_DRIVE_6mA>; |
| mediatek,pull-up-adv = <0>; /* bias-disable */ |
| }; |
| conf-pd { |
| pins = "SPI0_MOSI", "SPI0_MISO"; |
| drive-strength = <MTK_DRIVE_6mA>; |
| mediatek,pull-down-adv = <0>; /* bias-disable */ |
| }; |
| |
| }; |
| |
| spic_pins: spi1-pins { |
| mux { |
| function = "spi"; |
| groups = "spi1_2"; |
| }; |
| }; |
| |
| mmc0_pins_default: mmc0-pins-22-to-32-default { |
| mux { |
| function = "flash"; |
| groups = "emmc_45"; |
| }; |
| conf-cmd-dat { |
| pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", |
| "SPI0_CS", "SPI0_HOLD", "SPI0_WP", |
| "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; |
| input-enable; |
| drive-strength = <MTK_DRIVE_4mA>; |
| mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| }; |
| conf-clk { |
| pins = "SPI1_CS"; |
| drive-strength = <MTK_DRIVE_6mA>; |
| mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| }; |
| conf-rst { |
| pins = "PWM1"; |
| drive-strength = <MTK_DRIVE_4mA>; |
| mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| }; |
| }; |
| |
| mmc0_pins_uhs: mmc0-pins-22-to-32-uhs { |
| mux { |
| function = "flash"; |
| groups = "emmc_45"; |
| }; |
| conf-cmd-dat { |
| pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", |
| "SPI0_CS", "SPI0_HOLD", "SPI0_WP", |
| "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; |
| input-enable; |
| drive-strength = <MTK_DRIVE_4mA>; |
| mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| }; |
| conf-clk { |
| pins = "SPI1_CS"; |
| drive-strength = <MTK_DRIVE_6mA>; |
| mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| }; |
| conf-rst { |
| pins = "PWM1"; |
| drive-strength = <MTK_DRIVE_4mA>; |
| mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| }; |
| }; |
| }; |