developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 MediaTek Inc. |
| 3 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | #include <dt-bindings/phy/phy.h> |
| 18 | #include <dt-bindings/reset/ti-syscon.h> |
| 19 | #include <dt-bindings/clock/mt7981-clk.h> |
| 20 | / { |
| 21 | compatible = "mediatek,mt7981-rfb"; |
| 22 | interrupt-parent = <&gic>; |
| 23 | #address-cells = <2>; |
| 24 | #size-cells = <2>; |
| 25 | cpus { |
| 26 | #address-cells = <1>; |
| 27 | #size-cells = <0>; |
| 28 | cpu@0 { |
| 29 | device_type = "cpu"; |
| 30 | compatible = "arm,cortex-a53"; |
| 31 | enable-method = "psci"; |
| 32 | reg = <0x0>; |
| 33 | }; |
| 34 | |
| 35 | cpu@1 { |
| 36 | device_type = "cpu"; |
| 37 | compatible = "arm,cortex-a53"; |
| 38 | enable-method = "psci"; |
| 39 | reg = <0x1>; |
| 40 | }; |
| 41 | }; |
| 42 | |
| 43 | auxadc: adc@1100d000 { |
| 44 | compatible = "mediatek,mt7981-auxadc", |
| 45 | "mediatek,mt7622-auxadc"; |
| 46 | reg = <0 0x1100d000 0 0x1000>; |
| 47 | clocks = <&system_clk>; |
| 48 | clock-names = "main"; |
| 49 | #io-channel-cells = <1>; |
| 50 | }; |
| 51 | |
| 52 | wed: wed@15010000 { |
| 53 | compatible = "mediatek,wed"; |
| 54 | wed_num = <2>; |
| 55 | /* add this property for wed get the pci slot number. */ |
| 56 | pci_slot_map = <0>, <1>; |
| 57 | reg = <0 0x15010000 0 0x1000>, |
| 58 | <0 0x15011000 0 0x1000>; |
| 59 | interrupt-parent = <&gic>; |
| 60 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 62 | }; |
| 63 | |
| 64 | wdma: wdma@15104800 { |
| 65 | compatible = "mediatek,wed-wdma"; |
| 66 | reg = <0 0x15104800 0 0x400>, |
| 67 | <0 0x15104c00 0 0x400>; |
| 68 | }; |
| 69 | |
| 70 | ap2woccif: ap2woccif@151A5000 { |
| 71 | compatible = "mediatek,ap2woccif"; |
| 72 | reg = <0 0x151A5000 0 0x1000>, |
| 73 | <0 0x151AD000 0 0x1000>; |
| 74 | interrupt-parent = <&gic>; |
| 75 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| 77 | }; |
| 78 | |
| 79 | wocpu0_ilm: wocpu0_ilm@151E0000 { |
| 80 | compatible = "mediatek,wocpu0_ilm"; |
| 81 | reg = <0 0x151E0000 0 0x8000>; |
| 82 | }; |
| 83 | |
| 84 | wocpu_dlm: wocpu_dlm@151E8000 { |
| 85 | compatible = "mediatek,wocpu_dlm"; |
| 86 | reg = <0 0x151E8000 0 0x2000>, |
| 87 | <0 0x151F8000 0 0x2000>; |
| 88 | |
| 89 | resets = <ðsysrst 0>; |
| 90 | reset-names = "wocpu_rst"; |
| 91 | }; |
| 92 | |
| 93 | cpu_boot: wocpu_boot@15194000 { |
| 94 | compatible = "mediatek,wocpu_boot"; |
| 95 | reg = <0 0x15194000 0 0x1000>; |
| 96 | }; |
| 97 | |
| 98 | reserved-memory { |
| 99 | #address-cells = <2>; |
| 100 | #size-cells = <2>; |
| 101 | ranges; |
| 102 | |
| 103 | /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| 104 | secmon_reserved: secmon@43000000 { |
| 105 | reg = <0 0x43000000 0 0x30000>; |
| 106 | no-map; |
| 107 | }; |
| 108 | |
| 109 | wmcpu_emi: wmcpu-reserved@47C80000 { |
| 110 | compatible = "mediatek,wmcpu-reserved"; |
| 111 | no-map; |
| 112 | reg = <0 0x47C80000 0 0x00100000>; |
| 113 | }; |
| 114 | |
| 115 | wocpu0_emi: wocpu0_emi@47D80000 { |
| 116 | compatible = "mediatek,wocpu0_emi"; |
| 117 | no-map; |
| 118 | reg = <0 0x47D80000 0 0x40000>; |
| 119 | shared = <0>; |
| 120 | }; |
| 121 | |
| 122 | wocpu_data: wocpu_data@47DC0000 { |
| 123 | compatible = "mediatek,wocpu_data"; |
| 124 | no-map; |
| 125 | reg = <0 0x47DC0000 0 0x240000>; |
| 126 | shared = <1>; |
| 127 | }; |
| 128 | }; |
| 129 | |
| 130 | psci { |
| 131 | compatible = "arm,psci-0.2"; |
| 132 | method = "smc"; |
| 133 | }; |
| 134 | |
| 135 | clk40m: oscillator@0 { |
| 136 | compatible = "fixed-clock"; |
| 137 | #clock-cells = <0>; |
| 138 | clock-frequency = <40000000>; |
| 139 | clock-output-names = "clkxtal"; |
| 140 | }; |
| 141 | |
| 142 | infracfg_ao: infracfg_ao@10001000 { |
| 143 | compatible = "mediatek,mt7981-infracfg_ao", "syscon"; |
developer | dcd5aba | 2021-12-01 13:47:17 +0800 | [diff] [blame] | 144 | reg = <0 0x10001000 0 0x68>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 145 | #clock-cells = <1>; |
| 146 | }; |
| 147 | |
| 148 | infracfg: infracfg@10001040 { |
| 149 | compatible = "mediatek,mt7981-infracfg", "syscon"; |
developer | dcd5aba | 2021-12-01 13:47:17 +0800 | [diff] [blame] | 150 | reg = <0 0x10001068 0 0x1000>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 151 | #clock-cells = <1>; |
| 152 | }; |
| 153 | |
| 154 | topckgen: topckgen@1001B000 { |
| 155 | compatible = "mediatek,mt7981-topckgen", "syscon"; |
| 156 | reg = <0 0x1001B000 0 0x1000>; |
| 157 | #clock-cells = <1>; |
| 158 | }; |
| 159 | |
| 160 | apmixedsys: apmixedsys@1001E000 { |
| 161 | compatible = "mediatek,mt7981-apmixedsys", "syscon"; |
| 162 | reg = <0 0x1001E000 0 0x1000>; |
| 163 | #clock-cells = <1>; |
| 164 | }; |
| 165 | |
| 166 | system_clk: dummy_system_clk { |
| 167 | compatible = "fixed-clock"; |
| 168 | clock-frequency = <40000000>; |
| 169 | #clock-cells = <0>; |
| 170 | }; |
| 171 | |
| 172 | uart_clk: dummy_uart_clk { |
| 173 | compatible = "fixed-clock"; |
| 174 | clock-frequency = <40000000>; |
| 175 | #clock-cells = <0>; |
| 176 | }; |
| 177 | |
| 178 | gpt_clk: dummy_gpt_clk { |
| 179 | compatible = "fixed-clock"; |
| 180 | clock-frequency = <20000000>; |
| 181 | #clock-cells = <0>; |
| 182 | }; |
| 183 | |
developer | 33b0c63 | 2021-11-11 16:25:17 +0800 | [diff] [blame] | 184 | spi_clk: dummy_spi_clk { |
| 185 | compatible = "fixed-clock"; |
| 186 | clock-frequency = <208000000>; |
| 187 | #clock-cells = <0>; |
| 188 | }; |
| 189 | |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 190 | timer { |
| 191 | compatible = "arm,armv8-timer"; |
| 192 | interrupt-parent = <&gic>; |
developer | 3f7ec6d | 2021-11-12 14:59:41 +0800 | [diff] [blame] | 193 | clock-frequency = <13000000>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 194 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 195 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 196 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 197 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| 198 | |
| 199 | }; |
| 200 | |
| 201 | watchdog: watchdog@1001c000 { |
| 202 | compatible = "mediatek,mt7622-wdt", |
| 203 | "mediatek,mt6589-wdt"; |
| 204 | reg = <0 0x1001c000 0 0x1000>; |
| 205 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 206 | #reset-cells = <1>; |
| 207 | }; |
| 208 | |
| 209 | gic: interrupt-controller@c000000 { |
| 210 | compatible = "arm,gic-v3"; |
| 211 | #interrupt-cells = <3>; |
| 212 | interrupt-parent = <&gic>; |
| 213 | interrupt-controller; |
| 214 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 215 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 216 | |
| 217 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 218 | }; |
| 219 | |
| 220 | uart0: serial@11002000 { |
| 221 | compatible = "mediatek,mt7986-uart", |
| 222 | "mediatek,mt6577-uart"; |
| 223 | reg = <0 0x11002000 0 0x400>; |
| 224 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| 225 | clocks = <&uart_clk>; |
| 226 | status = "disabled"; |
| 227 | }; |
| 228 | |
| 229 | uart1: serial@11003000 { |
| 230 | compatible = "mediatek,mt7986-uart", |
| 231 | "mediatek,mt6577-uart"; |
| 232 | reg = <0 0x11003000 0 0x400>; |
| 233 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| 234 | clocks = <&uart_clk>; |
| 235 | status = "disabled"; |
| 236 | }; |
| 237 | |
| 238 | uart2: serial@11004000 { |
| 239 | compatible = "mediatek,mt7986-uart", |
| 240 | "mediatek,mt6577-uart"; |
| 241 | reg = <0 0x11004000 0 0x400>; |
| 242 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| 243 | clocks = <&uart_clk>; |
| 244 | status = "disabled"; |
| 245 | }; |
| 246 | |
developer | e08c9a6 | 2021-12-01 14:13:05 +0800 | [diff] [blame] | 247 | i2c0: i2c@11008000 { |
| 248 | compatible = "mediatek,mt7986-i2c"; |
| 249 | reg = <0 0x11008000 0 0x90>, |
| 250 | <0 0x10217080 0 0x80>; |
| 251 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | clock-div = <5>; |
| 253 | clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, |
| 254 | <&infracfg_ao CK_INFRA_AP_DMA_CK>; |
| 255 | clock-names = "main", "dma"; |
| 256 | #address-cells = <1>; |
| 257 | #size-cells = <0>; |
| 258 | status = "disabled"; |
| 259 | }; |
| 260 | |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 261 | pcie: pcie@11280000 { |
| 262 | compatible = "mediatek,mt7981-pcie", |
| 263 | "mediatek,mt7986-pcie"; |
| 264 | device_type = "pci"; |
| 265 | reg = <0 0x11280000 0 0x4000>; |
| 266 | reg-names = "pcie-mac"; |
| 267 | #address-cells = <3>; |
| 268 | #size-cells = <2>; |
| 269 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 270 | bus-range = <0x00 0xff>; |
| 271 | ranges = <0x82000000 0 0x20000000 |
| 272 | 0x0 0x20000000 0 0x10000000>; |
| 273 | status = "disabled"; |
| 274 | |
| 275 | phys = <&u3port0 PHY_TYPE_PCIE>; |
| 276 | phy-names = "pcie-phy"; |
| 277 | |
| 278 | #interrupt-cells = <1>; |
| 279 | interrupt-map-mask = <0 0 0 7>; |
| 280 | interrupt-map = <0 0 0 1 &pcie_intc 0>, |
| 281 | <0 0 0 2 &pcie_intc 1>, |
| 282 | <0 0 0 3 &pcie_intc 2>, |
| 283 | <0 0 0 4 &pcie_intc 3>; |
| 284 | pcie_intc: interrupt-controller { |
| 285 | interrupt-controller; |
| 286 | #address-cells = <0>; |
| 287 | #interrupt-cells = <1>; |
| 288 | }; |
| 289 | }; |
| 290 | |
developer | e3c7cd1 | 2021-11-30 14:49:26 +0800 | [diff] [blame] | 291 | crypto: crypto@10320000 { |
| 292 | compatible = "inside-secure,safexcel-eip97"; |
| 293 | reg = <0 0x10320000 0 0x40000>; |
| 294 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 295 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 296 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 297 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 298 | interrupt-names = "ring0", "ring1", "ring2", "ring3"; |
| 299 | clocks = <&topckgen CK_TOP_EIP97B>; |
| 300 | clock-names = "top_eip97_ck"; |
| 301 | assigned-clocks = <&topckgen CK_TOP_EIP97B_SEL>; |
| 302 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>; |
| 303 | }; |
| 304 | |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 305 | pio: pinctrl@11d00000 { |
| 306 | compatible = "mediatek,mt7981-pinctrl"; |
| 307 | reg = <0 0x11d00000 0 0x1000>, |
| 308 | <0 0x11c00000 0 0x1000>, |
| 309 | <0 0x11c10000 0 0x1000>, |
| 310 | <0 0x11d20000 0 0x1000>, |
| 311 | <0 0x11e00000 0 0x1000>, |
| 312 | <0 0x11e20000 0 0x1000>, |
| 313 | <0 0x11f00000 0 0x1000>, |
| 314 | <0 0x11f10000 0 0x1000>, |
| 315 | <0 0x1000b000 0 0x1000>; |
| 316 | reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", |
| 317 | "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", |
| 318 | "iocfg_tm_base", "iocfg_tl_base", "eint"; |
| 319 | gpio-controller; |
| 320 | #gpio-cells = <2>; |
| 321 | gpio-ranges = <&pio 0 0 56>; |
| 322 | interrupt-controller; |
| 323 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| 324 | interrupt-parent = <&gic>; |
| 325 | #interrupt-cells = <2>; |
| 326 | }; |
| 327 | |
| 328 | ethsys: syscon@15000000 { |
| 329 | #address-cells = <1>; |
| 330 | #size-cells = <1>; |
developer | 9e9fb4c | 2021-11-30 17:33:04 +0800 | [diff] [blame] | 331 | compatible = "mediatek,mt7981-ethsys", |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 332 | "syscon"; |
| 333 | reg = <0 0x15000000 0 0x1000>; |
| 334 | #clock-cells = <1>; |
| 335 | #reset-cells = <1>; |
| 336 | |
| 337 | ethsysrst: reset-controller { |
| 338 | compatible = "ti,syscon-reset"; |
| 339 | #reset-cells = <1>; |
| 340 | ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| 341 | }; |
| 342 | }; |
| 343 | |
| 344 | eth: ethernet@15100000 { |
| 345 | compatible = "mediatek,mt7981-eth"; |
| 346 | reg = <0 0x15100000 0 0x80000>; |
| 347 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 348 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| 349 | <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 350 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
developer | 9e9fb4c | 2021-11-30 17:33:04 +0800 | [diff] [blame] | 351 | clocks = <ðsys CK_ETH_FE_EN>, |
| 352 | <ðsys CK_ETH_GP2_EN>, |
| 353 | <ðsys CK_ETH_GP1_EN>, |
| 354 | <ðsys CK_ETH_WOCPU0_EN>, |
| 355 | <&sgmiisys0 CK_SGM0_TX_EN>, |
| 356 | <&sgmiisys0 CK_SGM0_RX_EN>, |
| 357 | <&sgmiisys0 CK_SGM0_CK0_EN>, |
| 358 | <&sgmiisys0 CK_SGM0_CDR_CK0_EN>, |
| 359 | <&sgmiisys1 CK_SGM1_TX_EN>, |
| 360 | <&sgmiisys1 CK_SGM1_RX_EN>, |
| 361 | <&sgmiisys1 CK_SGM1_CK1_EN>, |
| 362 | <&sgmiisys1 CK_SGM1_CDR_CK1_EN>; |
| 363 | clock-names = "fe", "gp2", "gp1", "wocpu0", |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 364 | "sgmii_tx250m", "sgmii_rx250m", |
| 365 | "sgmii_cdr_ref", "sgmii_cdr_fb", |
| 366 | "sgmii2_tx250m", "sgmii2_rx250m", |
| 367 | "sgmii2_cdr_ref", "sgmii2_cdr_fb"; |
developer | 9e9fb4c | 2021-11-30 17:33:04 +0800 | [diff] [blame] | 368 | assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| 369 | <&topckgen CK_TOP_SGM_325M_SEL>; |
| 370 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>, |
| 371 | <&topckgen CK_TOP_CB_SGM_325M>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 372 | mediatek,ethsys = <ðsys>; |
| 373 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 374 | mediatek,infracfg = <&topmisc>; |
| 375 | #reset-cells = <1>; |
| 376 | #address-cells = <1>; |
| 377 | #size-cells = <0>; |
| 378 | status = "disabled"; |
| 379 | }; |
| 380 | |
| 381 | hnat: hnat@15000000 { |
| 382 | compatible = "mediatek,mtk-hnat_v4"; |
| 383 | reg = <0 0x15100000 0 0x80000>; |
| 384 | resets = <ðsys 0>; |
| 385 | reset-names = "mtketh"; |
| 386 | status = "disabled"; |
| 387 | }; |
| 388 | |
| 389 | sgmiisys0: syscon@10060000 { |
developer | 9e9fb4c | 2021-11-30 17:33:04 +0800 | [diff] [blame] | 390 | compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 391 | reg = <0 0x10060000 0 0x1000>; |
| 392 | pn_swap; |
| 393 | #clock-cells = <1>; |
| 394 | }; |
| 395 | |
| 396 | sgmiisys1: syscon@10070000 { |
developer | 9e9fb4c | 2021-11-30 17:33:04 +0800 | [diff] [blame] | 397 | compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 398 | reg = <0 0x10070000 0 0x1000>; |
| 399 | #clock-cells = <1>; |
| 400 | }; |
| 401 | |
| 402 | topmisc: topmisc@11d10000 { |
| 403 | compatible = "mediatek,mt7981-topmisc", "syscon"; |
| 404 | reg = <0 0x11d10000 0 0x10000>; |
| 405 | #clock-cells = <1>; |
| 406 | }; |
| 407 | |
| 408 | snand: snfi@11005000 { |
| 409 | compatible = "mediatek,mt7986-snand"; |
| 410 | reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; |
| 411 | reg-names = "nfi", "ecc"; |
| 412 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
developer | af7c350 | 2021-11-10 20:49:31 +0800 | [diff] [blame] | 413 | clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| 414 | <&infracfg_ao CK_INFRA_NFI1_CK>, |
| 415 | <&infracfg_ao CK_INFRA_NFI_HCK_CK>; |
| 416 | clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; |
| 417 | assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 418 | <&topckgen CK_TOP_NFI1X_SEL>; |
| 419 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, |
| 420 | <&topckgen CK_TOP_CB_M_D8>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 421 | #address-cells = <1>; |
| 422 | #size-cells = <0>; |
| 423 | status = "disabled"; |
| 424 | }; |
| 425 | |
| 426 | mmc0: mmc@11230000 { |
| 427 | compatible = "mediatek,mt7986-mmc"; |
| 428 | reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; |
| 429 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 430 | clocks = <&system_clk>, |
| 431 | <&system_clk>, |
| 432 | <&system_clk>; |
| 433 | clock-names = "source", "hclk", "source_cg"; |
| 434 | status = "disabled"; |
| 435 | }; |
| 436 | |
| 437 | wbsys: wbsys@18000000 { |
| 438 | compatible = "mediatek,wbsys"; |
| 439 | reg = <0 0x18000000 0 0x1000000>; |
| 440 | interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| 441 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 442 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 443 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| 444 | chip_id = <0x7981>; |
| 445 | }; |
| 446 | |
| 447 | wed_pcie: wed_pcie@10003000 { |
| 448 | compatible = "mediatek,wed_pcie"; |
| 449 | reg = <0 0x10003000 0 0x10>; |
| 450 | }; |
| 451 | |
| 452 | spi0: spi@1100a000 { |
| 453 | compatible = "mediatek,ipm-spi-quad"; |
| 454 | reg = <0 0x1100a000 0 0x100>; |
| 455 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
developer | 33b0c63 | 2021-11-11 16:25:17 +0800 | [diff] [blame] | 456 | clocks = <&spi_clk>, |
| 457 | <&spi_clk>, |
| 458 | <&spi_clk>, |
| 459 | <&spi_clk>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 460 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| 461 | status = "disabled"; |
| 462 | }; |
| 463 | |
| 464 | spi1: spi@1100b000 { |
| 465 | compatible = "mediatek,ipm-spi-single"; |
| 466 | reg = <0 0x1100b000 0 0x100>; |
| 467 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
developer | 33b0c63 | 2021-11-11 16:25:17 +0800 | [diff] [blame] | 468 | clocks = <&spi_clk>, |
| 469 | <&spi_clk>, |
| 470 | <&spi_clk>, |
| 471 | <&spi_clk>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 472 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| 473 | status = "disabled"; |
| 474 | }; |
| 475 | |
| 476 | spi2: spi@11009000 { |
| 477 | compatible = "mediatek,ipm-spi-quad"; |
| 478 | reg = <0 0x11009000 0 0x100>; |
| 479 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
developer | 33b0c63 | 2021-11-11 16:25:17 +0800 | [diff] [blame] | 480 | clocks = <&spi_clk>, |
| 481 | <&spi_clk>, |
| 482 | <&spi_clk>, |
| 483 | <&spi_clk>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 484 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| 485 | status = "disabled"; |
| 486 | }; |
| 487 | |
| 488 | |
| 489 | consys: consys@10000000 { |
| 490 | compatible = "mediatek,mt7981-consys"; |
| 491 | reg = <0 0x10000000 0 0x8600000>; |
| 492 | memory-region = <&wmcpu_emi>; |
| 493 | }; |
| 494 | |
| 495 | xhci: xhci@11200000 { |
| 496 | compatible = "mediatek,mt7986-xhci", |
| 497 | "mediatek,mtk-xhci"; |
| 498 | reg = <0 0x11200000 0 0x2e00>, |
| 499 | <0 0x11203e00 0 0x0100>; |
| 500 | reg-names = "mac", "ippc"; |
| 501 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 502 | phys = <&u2port0 PHY_TYPE_USB2>; |
| 503 | clocks = <&system_clk>, |
| 504 | <&system_clk>, |
| 505 | <&system_clk>, |
| 506 | <&system_clk>, |
| 507 | <&system_clk>; |
| 508 | clock-names = "sys_ck", |
| 509 | "xhci_ck", |
| 510 | "ref_ck", |
| 511 | "mcu_ck", |
| 512 | "dma_ck"; |
| 513 | #address-cells = <2>; |
| 514 | #size-cells = <2>; |
| 515 | mediatek,u3p-dis-msk = <0x01>; |
| 516 | status = "disabled"; |
| 517 | }; |
| 518 | |
| 519 | usbtphy: usb-phy@11e10000 { |
| 520 | compatible = "mediatek,mt7986", |
| 521 | "mediatek,generic-tphy-v2"; |
| 522 | #address-cells = <2>; |
| 523 | #size-cells = <2>; |
| 524 | ranges; |
| 525 | status = "okay"; |
| 526 | |
| 527 | u2port0: usb-phy@11e10000 { |
| 528 | reg = <0 0x11e10000 0 0x700>; |
| 529 | clocks = <&system_clk>; |
| 530 | clock-names = "ref"; |
| 531 | #phy-cells = <1>; |
| 532 | status = "okay"; |
| 533 | }; |
| 534 | |
| 535 | u3port0: usb-phy@11e10700 { |
| 536 | reg = <0 0x11e10700 0 0x900>; |
| 537 | clocks = <&system_clk>; |
| 538 | clock-names = "ref"; |
| 539 | #phy-cells = <1>; |
| 540 | mediatek,syscon-type = <&topmisc 0x218 0>; |
| 541 | status = "okay"; |
| 542 | }; |
| 543 | }; |
| 544 | |
| 545 | reg_3p3v: regulator-3p3v { |
| 546 | compatible = "regulator-fixed"; |
| 547 | regulator-name = "fixed-3.3V"; |
| 548 | regulator-min-microvolt = <3300000>; |
| 549 | regulator-max-microvolt = <3300000>; |
| 550 | regulator-boot-on; |
| 551 | regulator-always-on; |
| 552 | }; |
| 553 | |
| 554 | clkitg: clkitg { |
| 555 | compatible = "simple-bus"; |
| 556 | }; |
developer | a7de8be | 2021-11-15 21:14:31 +0800 | [diff] [blame] | 557 | |
| 558 | efuse: efuse@11f20000 { |
| 559 | compatible = "mediatek,efuse"; |
| 560 | reg = <0 0x11f20000 0 0x1000>; |
| 561 | #address-cells = <1>; |
| 562 | #size-cells = <1>; |
| 563 | |
| 564 | thermal_calibration: calib@274 { |
| 565 | reg = <0x274 0xc>; |
| 566 | }; |
| 567 | |
| 568 | phy_calibration: calib@8dc { |
| 569 | reg = <0x8dc 0x10>; |
| 570 | }; |
| 571 | }; |
developer | e3c7cd1 | 2021-11-30 14:49:26 +0800 | [diff] [blame] | 572 | |
| 573 | afe: audio-controller@11210000 { |
| 574 | compatible = "mediatek,mt79xx-audio"; |
| 575 | reg = <0 0x11210000 0 0x9000>; |
| 576 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 577 | clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>, |
| 578 | <&infracfg_ao CK_INFRA_AUD_26M_CK>, |
| 579 | <&infracfg_ao CK_INFRA_AUD_L_CK>, |
| 580 | <&infracfg_ao CK_INFRA_AUD_AUD_CK>, |
| 581 | <&infracfg_ao CK_INFRA_AUD_EG2_CK>; |
| 582 | clock-names = "aud_bus_ck", |
| 583 | "aud_26m_ck", |
| 584 | "aud_l_ck", |
| 585 | "aud_aud_ck", |
| 586 | "aud_eg2_ck"; |
| 587 | assigned-clocks = <&topckgen CK_TOP_AUD_SEL>, |
| 588 | <&topckgen CK_TOP_A1SYS_SEL>, |
| 589 | <&topckgen CK_TOP_AUD_L_SEL>, |
| 590 | <&topckgen CK_TOP_A_TUNER_SEL>; |
| 591 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 592 | <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 593 | <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 594 | <&topckgen CK_TOP_CB_CKSQ_40M>; |
| 595 | status = "disabled"; |
| 596 | }; |
developer | edeb397 | 2021-12-02 14:02:24 +0800 | [diff] [blame^] | 597 | |
| 598 | ice: ice_debug { |
| 599 | compatible = "mediatek,mt7981-ice_debug", |
| 600 | "mediatek,mt2701-ice_debug"; |
| 601 | clocks = <&infracfg_ao CK_INFRA_DBG_CK>; |
| 602 | clock-names = "ice_dbg"; |
| 603 | }; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 604 | }; |
| 605 | #include "mt7981-clkitg.dtsi" |