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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / af7c350a58fecdf5320818f6da859ad83490e2dc / . / target / linux / mediatek / files-5.4 / arch / arm64 / boot / dts / mediatek / mt7981.dtsi
blob: 850b20cc84277fdfe7f6c920accfcde9d738dfc8 [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +0800[diff] [blame]1/*
2 * Copyright (c) 2020 MediaTek Inc.
3 * Author: Sam.Shih <sam.shih@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/phy/phy.h>
18#include <dt-bindings/reset/ti-syscon.h>
19#include <dt-bindings/clock/mt7981-clk.h>
20/ {
21 compatible = "mediatek,mt7981-rfb";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a53";
31 enable-method = "psci";
32 reg = <0x0>;
33 };
34
35 cpu@1 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 reg = <0x1>;
40 };
41 };
42
43 auxadc: adc@1100d000 {
44 compatible = "mediatek,mt7981-auxadc",
45 "mediatek,mt7622-auxadc";
46 reg = <0 0x1100d000 0 0x1000>;
47 clocks = <&system_clk>;
48 clock-names = "main";
49 #io-channel-cells = <1>;
50 };
51
52 wed: wed@15010000 {
53 compatible = "mediatek,wed";
54 wed_num = <2>;
55 /* add this property for wed get the pci slot number. */
56 pci_slot_map = <0>, <1>;
57 reg = <0 0x15010000 0 0x1000>,
58 <0 0x15011000 0 0x1000>;
59 interrupt-parent = <&gic>;
60 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
62 };
63
64 wdma: wdma@15104800 {
65 compatible = "mediatek,wed-wdma";
66 reg = <0 0x15104800 0 0x400>,
67 <0 0x15104c00 0 0x400>;
68 };
69
70 ap2woccif: ap2woccif@151A5000 {
71 compatible = "mediatek,ap2woccif";
72 reg = <0 0x151A5000 0 0x1000>,
73 <0 0x151AD000 0 0x1000>;
74 interrupt-parent = <&gic>;
75 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
77 };
78
79 wocpu0_ilm: wocpu0_ilm@151E0000 {
80 compatible = "mediatek,wocpu0_ilm";
81 reg = <0 0x151E0000 0 0x8000>;
82 };
83
84 wocpu_dlm: wocpu_dlm@151E8000 {
85 compatible = "mediatek,wocpu_dlm";
86 reg = <0 0x151E8000 0 0x2000>,
87 <0 0x151F8000 0 0x2000>;
88
89 resets = <&ethsysrst 0>;
90 reset-names = "wocpu_rst";
91 };
92
93 cpu_boot: wocpu_boot@15194000 {
94 compatible = "mediatek,wocpu_boot";
95 reg = <0 0x15194000 0 0x1000>;
96 };
97
98 reserved-memory {
99 #address-cells = <2>;
100 #size-cells = <2>;
101 ranges;
102
103 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
104 secmon_reserved: secmon@43000000 {
105 reg = <0 0x43000000 0 0x30000>;
106 no-map;
107 };
108
109 wmcpu_emi: wmcpu-reserved@47C80000 {
110 compatible = "mediatek,wmcpu-reserved";
111 no-map;
112 reg = <0 0x47C80000 0 0x00100000>;
113 };
114
115 wocpu0_emi: wocpu0_emi@47D80000 {
116 compatible = "mediatek,wocpu0_emi";
117 no-map;
118 reg = <0 0x47D80000 0 0x40000>;
119 shared = <0>;
120 };
121
122 wocpu_data: wocpu_data@47DC0000 {
123 compatible = "mediatek,wocpu_data";
124 no-map;
125 reg = <0 0x47DC0000 0 0x240000>;
126 shared = <1>;
127 };
128 };
129
130 psci {
131 compatible = "arm,psci-0.2";
132 method = "smc";
133 };
134
135 clk40m: oscillator@0 {
136 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 clock-frequency = <40000000>;
139 clock-output-names = "clkxtal";
140 };
141
142 infracfg_ao: infracfg_ao@10001000 {
143 compatible = "mediatek,mt7981-infracfg_ao", "syscon";
144 reg = <0 0x10001000 0 0x30>;
145 #clock-cells = <1>;
146 };
147
148 infracfg: infracfg@10001040 {
149 compatible = "mediatek,mt7981-infracfg", "syscon";
150 reg = <0 0x10001040 0 0x1000>;
151 #clock-cells = <1>;
152 };
153
154 topckgen: topckgen@1001B000 {
155 compatible = "mediatek,mt7981-topckgen", "syscon";
156 reg = <0 0x1001B000 0 0x1000>;
157 #clock-cells = <1>;
158 };
159
160 apmixedsys: apmixedsys@1001E000 {
161 compatible = "mediatek,mt7981-apmixedsys", "syscon";
162 reg = <0 0x1001E000 0 0x1000>;
163 #clock-cells = <1>;
164 };
165
166 system_clk: dummy_system_clk {
167 compatible = "fixed-clock";
168 clock-frequency = <40000000>;
169 #clock-cells = <0>;
170 };
171
172 uart_clk: dummy_uart_clk {
173 compatible = "fixed-clock";
174 clock-frequency = <40000000>;
175 #clock-cells = <0>;
176 };
177
178 gpt_clk: dummy_gpt_clk {
179 compatible = "fixed-clock";
180 clock-frequency = <20000000>;
181 #clock-cells = <0>;
182 };
183
184 timer {
185 compatible = "arm,armv8-timer";
186 interrupt-parent = <&gic>;
187 clock-frequency = <40000000>;
188 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
189 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
190 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
191 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
192
193 };
194
195 watchdog: watchdog@1001c000 {
196 compatible = "mediatek,mt7622-wdt",
197 "mediatek,mt6589-wdt";
198 reg = <0 0x1001c000 0 0x1000>;
199 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
200 #reset-cells = <1>;
201 };
202
203 gic: interrupt-controller@c000000 {
204 compatible = "arm,gic-v3";
205 #interrupt-cells = <3>;
206 interrupt-parent = <&gic>;
207 interrupt-controller;
208 reg = <0 0x0c000000 0 0x40000>, /* GICD */
209 <0 0x0c080000 0 0x200000>; /* GICR */
210
211 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
212 };
213
214 uart0: serial@11002000 {
215 compatible = "mediatek,mt7986-uart",
216 "mediatek,mt6577-uart";
217 reg = <0 0x11002000 0 0x400>;
218 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&uart_clk>;
220 status = "disabled";
221 };
222
223 uart1: serial@11003000 {
224 compatible = "mediatek,mt7986-uart",
225 "mediatek,mt6577-uart";
226 reg = <0 0x11003000 0 0x400>;
227 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&uart_clk>;
229 status = "disabled";
230 };
231
232 uart2: serial@11004000 {
233 compatible = "mediatek,mt7986-uart",
234 "mediatek,mt6577-uart";
235 reg = <0 0x11004000 0 0x400>;
236 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&uart_clk>;
238 status = "disabled";
239 };
240
241 pcie: pcie@11280000 {
242 compatible = "mediatek,mt7981-pcie",
243 "mediatek,mt7986-pcie";
244 device_type = "pci";
245 reg = <0 0x11280000 0 0x4000>;
246 reg-names = "pcie-mac";
247 #address-cells = <3>;
248 #size-cells = <2>;
249 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
250 bus-range = <0x00 0xff>;
251 ranges = <0x82000000 0 0x20000000
252 0x0 0x20000000 0 0x10000000>;
253 status = "disabled";
254
255 phys = <&u3port0 PHY_TYPE_PCIE>;
256 phy-names = "pcie-phy";
257
258 #interrupt-cells = <1>;
259 interrupt-map-mask = <0 0 0 7>;
260 interrupt-map = <0 0 0 1 &pcie_intc 0>,
261 <0 0 0 2 &pcie_intc 1>,
262 <0 0 0 3 &pcie_intc 2>,
263 <0 0 0 4 &pcie_intc 3>;
264 pcie_intc: interrupt-controller {
265 interrupt-controller;
266 #address-cells = <0>;
267 #interrupt-cells = <1>;
268 };
269 };
270
271 pio: pinctrl@11d00000 {
272 compatible = "mediatek,mt7981-pinctrl";
273 reg = <0 0x11d00000 0 0x1000>,
274 <0 0x11c00000 0 0x1000>,
275 <0 0x11c10000 0 0x1000>,
276 <0 0x11d20000 0 0x1000>,
277 <0 0x11e00000 0 0x1000>,
278 <0 0x11e20000 0 0x1000>,
279 <0 0x11f00000 0 0x1000>,
280 <0 0x11f10000 0 0x1000>,
281 <0 0x1000b000 0 0x1000>;
282 reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
283 "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
284 "iocfg_tm_base", "iocfg_tl_base", "eint";
285 gpio-controller;
286 #gpio-cells = <2>;
287 gpio-ranges = <&pio 0 0 56>;
288 interrupt-controller;
289 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-parent = <&gic>;
291 #interrupt-cells = <2>;
292 };
293
294 ethsys: syscon@15000000 {
295 #address-cells = <1>;
296 #size-cells = <1>;
297 compatible = "mediatek,mt7986-ethsys",
298 "syscon";
299 reg = <0 0x15000000 0 0x1000>;
300 #clock-cells = <1>;
301 #reset-cells = <1>;
302
303 ethsysrst: reset-controller {
304 compatible = "ti,syscon-reset";
305 #reset-cells = <1>;
306 ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
307 };
308 };
309
310 eth: ethernet@15100000 {
311 compatible = "mediatek,mt7981-eth";
312 reg = <0 0x15100000 0 0x80000>;
313 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&system_clk>,
318 <&system_clk>,
319 <&system_clk>,
320 <&system_clk>,
321 <&system_clk>,
322 <&system_clk>,
323 <&system_clk>,
324 <&system_clk>,
325 <&system_clk>,
326 <&system_clk>,
327 <&system_clk>,
328 <&system_clk>,
329 <&system_clk>;
330 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
331 "sgmii_tx250m", "sgmii_rx250m",
332 "sgmii_cdr_ref", "sgmii_cdr_fb",
333 "sgmii2_tx250m", "sgmii2_rx250m",
334 "sgmii2_cdr_ref", "sgmii2_cdr_fb";
335 mediatek,ethsys = <&ethsys>;
336 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
337 mediatek,infracfg = <&topmisc>;
338 #reset-cells = <1>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
343
344 hnat: hnat@15000000 {
345 compatible = "mediatek,mtk-hnat_v4";
346 reg = <0 0x15100000 0 0x80000>;
347 resets = <&ethsys 0>;
348 reset-names = "mtketh";
349 status = "disabled";
350 };
351
352 sgmiisys0: syscon@10060000 {
353 compatible = "mediatek,mt7986-sgmiisys", "syscon";
354 reg = <0 0x10060000 0 0x1000>;
355 pn_swap;
356 #clock-cells = <1>;
357 };
358
359 sgmiisys1: syscon@10070000 {
360 compatible = "mediatek,mt7986-sgmiisys", "syscon";
361 reg = <0 0x10070000 0 0x1000>;
362 #clock-cells = <1>;
363 };
364
365 topmisc: topmisc@11d10000 {
366 compatible = "mediatek,mt7981-topmisc", "syscon";
367 reg = <0 0x11d10000 0 0x10000>;
368 #clock-cells = <1>;
369 };
370
371 snand: snfi@11005000 {
372 compatible = "mediatek,mt7986-snand";
373 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
374 reg-names = "nfi", "ecc";
375 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
developeraf7c3502021-11-10 20:49:31 +0800[diff] [blame^]376 clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
377 <&infracfg_ao CK_INFRA_NFI1_CK>,
378 <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
379 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
380 assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
381 <&topckgen CK_TOP_NFI1X_SEL>;
382 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
383 <&topckgen CK_TOP_CB_M_D8>;
developer24455dd2021-10-28 10:55:41 +0800[diff] [blame]384 #address-cells = <1>;
385 #size-cells = <0>;
386 status = "disabled";
387 };
388
389 mmc0: mmc@11230000 {
390 compatible = "mediatek,mt7986-mmc";
391 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
392 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&system_clk>,
394 <&system_clk>,
395 <&system_clk>;
396 clock-names = "source", "hclk", "source_cg";
397 status = "disabled";
398 };
399
400 wbsys: wbsys@18000000 {
401 compatible = "mediatek,wbsys";
402 reg = <0 0x18000000 0 0x1000000>;
403 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
407 chip_id = <0x7981>;
408 };
409
410 wed_pcie: wed_pcie@10003000 {
411 compatible = "mediatek,wed_pcie";
412 reg = <0 0x10003000 0 0x10>;
413 };
414
415 spi0: spi@1100a000 {
416 compatible = "mediatek,ipm-spi-quad";
417 reg = <0 0x1100a000 0 0x100>;
418 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&uart_clk>,
420 <&uart_clk>,
421 <&uart_clk>,
422 <&uart_clk>;
423 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
424 status = "disabled";
425 };
426
427 spi1: spi@1100b000 {
428 compatible = "mediatek,ipm-spi-single";
429 reg = <0 0x1100b000 0 0x100>;
430 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&uart_clk>,
432 <&uart_clk>,
433 <&uart_clk>,
434 <&uart_clk>;
435 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
436 status = "disabled";
437 };
438
439 spi2: spi@11009000 {
440 compatible = "mediatek,ipm-spi-quad";
441 reg = <0 0x11009000 0 0x100>;
442 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&uart_clk>,
444 <&uart_clk>,
445 <&uart_clk>,
446 <&uart_clk>;
447 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
448 status = "disabled";
449 };
450
451
452 consys: consys@10000000 {
453 compatible = "mediatek,mt7981-consys";
454 reg = <0 0x10000000 0 0x8600000>;
455 memory-region = <&wmcpu_emi>;
456 };
457
458 xhci: xhci@11200000 {
459 compatible = "mediatek,mt7986-xhci",
460 "mediatek,mtk-xhci";
461 reg = <0 0x11200000 0 0x2e00>,
462 <0 0x11203e00 0 0x0100>;
463 reg-names = "mac", "ippc";
464 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
465 phys = <&u2port0 PHY_TYPE_USB2>;
466 clocks = <&system_clk>,
467 <&system_clk>,
468 <&system_clk>,
469 <&system_clk>,
470 <&system_clk>;
471 clock-names = "sys_ck",
472 "xhci_ck",
473 "ref_ck",
474 "mcu_ck",
475 "dma_ck";
476 #address-cells = <2>;
477 #size-cells = <2>;
478 mediatek,u3p-dis-msk = <0x01>;
479 status = "disabled";
480 };
481
482 usbtphy: usb-phy@11e10000 {
483 compatible = "mediatek,mt7986",
484 "mediatek,generic-tphy-v2";
485 #address-cells = <2>;
486 #size-cells = <2>;
487 ranges;
488 status = "okay";
489
490 u2port0: usb-phy@11e10000 {
491 reg = <0 0x11e10000 0 0x700>;
492 clocks = <&system_clk>;
493 clock-names = "ref";
494 #phy-cells = <1>;
495 status = "okay";
496 };
497
498 u3port0: usb-phy@11e10700 {
499 reg = <0 0x11e10700 0 0x900>;
500 clocks = <&system_clk>;
501 clock-names = "ref";
502 #phy-cells = <1>;
503 mediatek,syscon-type = <&topmisc 0x218 0>;
504 status = "okay";
505 };
506 };
507
508 reg_3p3v: regulator-3p3v {
509 compatible = "regulator-fixed";
510 regulator-name = "fixed-3.3V";
511 regulator-min-microvolt = <3300000>;
512 regulator-max-microvolt = <3300000>;
513 regulator-boot-on;
514 regulator-always-on;
515 };
516
517 clkitg: clkitg {
518 compatible = "simple-bus";
519 };
520};
521#include "mt7981-clkitg.dtsi"