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developer20bb2202023-04-17 09:22:47 +08001From d0242b056d4e4f22dcdec8755798e5461cf131b5 Mon Sep 17 00:00:00 2001
developer2324aa22023-04-12 11:30:15 +08002From: Bo Jiao <Bo.Jiao@mediatek.com>
3Date: Tue, 11 Apr 2023 10:56:17 +0800
developer20bb2202023-04-17 09:22:47 +08004Subject: [PATCH] wifi: mt76: mt7915: disable wfdma tx/rx during SER recovery.
developer2324aa22023-04-12 11:30:15 +08005
6Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com>
7---
8 dma.c | 6 ++
developer20bb2202023-04-17 09:22:47 +08009 mt7915/dma.c | 148 +++++++++++++++++++++++++++---------------------
developer2324aa22023-04-12 11:30:15 +080010 mt7915/mac.c | 17 +++++-
11 mt7915/mt7915.h | 1 +
developer20bb2202023-04-17 09:22:47 +080012 4 files changed, 103 insertions(+), 69 deletions(-)
developer2324aa22023-04-12 11:30:15 +080013
14diff --git a/dma.c b/dma.c
developer1d9da7d2023-04-15 12:45:34 +080015index df2ca73..c22ea64 100644
developer2324aa22023-04-12 11:30:15 +080016--- a/dma.c
17+++ b/dma.c
18@@ -466,6 +466,9 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
19 struct mt76_queue_buf buf = {};
20 dma_addr_t addr;
21
22+ if (test_bit(MT76_MCU_RESET, &dev->phy.state))
23+ goto error;
24+
25 if (q->queued + 1 >= q->ndesc - 1)
26 goto error;
27
28@@ -507,6 +510,9 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
29 dma_addr_t addr;
30 u8 *txwi;
31
32+ if (test_bit(MT76_RESET, &dev->phy.state))
33+ goto free_skb;
34+
35 t = mt76_get_txwi(dev);
36 if (!t)
37 goto free_skb;
38diff --git a/mt7915/dma.c b/mt7915/dma.c
developer20bb2202023-04-17 09:22:47 +080039index 43a5456..9f19609 100644
developer2324aa22023-04-12 11:30:15 +080040--- a/mt7915/dma.c
41+++ b/mt7915/dma.c
developer20bb2202023-04-17 09:22:47 +080042@@ -250,12 +250,90 @@ static void mt7915_dma_disable(struct mt7915_dev *dev, bool rst)
developer2324aa22023-04-12 11:30:15 +080043 }
44 }
45
46-static int mt7915_dma_enable(struct mt7915_dev *dev)
developer20bb2202023-04-17 09:22:47 +080047+int __mt7915_dma_enable(struct mt7915_dev *dev, bool reset, bool wed_reset)
developer2324aa22023-04-12 11:30:15 +080048 {
49 struct mt76_dev *mdev = &dev->mt76;
50 u32 hif1_ofs = 0;
51 u32 irq_mask;
52
53+ if (dev->hif2)
54+ hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
55+
56+ /* enable wpdma tx/rx */
57+ if (!reset) {
58+ mt76_set(dev, MT_WFDMA0_GLO_CFG,
59+ MT_WFDMA0_GLO_CFG_TX_DMA_EN |
60+ MT_WFDMA0_GLO_CFG_RX_DMA_EN |
61+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
62+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
63+
64+ if (is_mt7915(mdev))
65+ mt76_set(dev, MT_WFDMA1_GLO_CFG,
66+ MT_WFDMA1_GLO_CFG_TX_DMA_EN |
67+ MT_WFDMA1_GLO_CFG_RX_DMA_EN |
68+ MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
69+ MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
70+
71+ if (dev->hif2) {
72+ mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
73+ MT_WFDMA0_GLO_CFG_TX_DMA_EN |
74+ MT_WFDMA0_GLO_CFG_RX_DMA_EN |
75+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
76+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
77+
78+ if (is_mt7915(mdev))
79+ mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
80+ MT_WFDMA1_GLO_CFG_TX_DMA_EN |
81+ MT_WFDMA1_GLO_CFG_RX_DMA_EN |
82+ MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
83+ MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
84+
85+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
86+ MT_WFDMA_HOST_CONFIG_PDMA_BAND);
87+ }
88+ }
89+
90+ /* enable interrupts for TX/RX rings */
91+ irq_mask = MT_INT_RX_DONE_MCU |
92+ MT_INT_TX_DONE_MCU |
93+ MT_INT_MCU_CMD;
94+
95+ if (!dev->phy.mt76->band_idx)
96+ irq_mask |= MT_INT_BAND0_RX_DONE;
97+
98+ if (dev->dbdc_support || dev->phy.mt76->band_idx)
99+ irq_mask |= MT_INT_BAND1_RX_DONE;
100+
101+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) && wed_reset) {
102+ u32 wed_irq_mask = irq_mask;
103+ int ret;
104+
105+ wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
106+ if (!is_mt7986(&dev->mt76))
107+ mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
108+ else
109+ mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
110+
111+ ret = mt7915_mcu_wed_enable_rx_stats(dev);
112+ if (ret)
113+ return ret;
114+
115+ mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
116+ }
117+
118+ irq_mask = reset ? MT_INT_MCU_CMD : irq_mask;
119+
120+ mt7915_irq_enable(dev, irq_mask);
121+ mt7915_irq_disable(dev, 0);
developer20bb2202023-04-17 09:22:47 +0800122+
123+ return 0;
developer2324aa22023-04-12 11:30:15 +0800124+}
125+
126+static int mt7915_dma_enable(struct mt7915_dev *dev, bool reset)
127+{
128+ struct mt76_dev *mdev = &dev->mt76;
129+ u32 hif1_ofs = 0;
130+
131 if (dev->hif2)
132 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
133
developer20bb2202023-04-17 09:22:47 +0800134@@ -322,69 +400,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
developer2324aa22023-04-12 11:30:15 +0800135 mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
136 MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
137
138- /* set WFDMA Tx/Rx */
139- mt76_set(dev, MT_WFDMA0_GLO_CFG,
140- MT_WFDMA0_GLO_CFG_TX_DMA_EN |
141- MT_WFDMA0_GLO_CFG_RX_DMA_EN |
142- MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
143- MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
144-
145- if (is_mt7915(mdev))
146- mt76_set(dev, MT_WFDMA1_GLO_CFG,
147- MT_WFDMA1_GLO_CFG_TX_DMA_EN |
148- MT_WFDMA1_GLO_CFG_RX_DMA_EN |
149- MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
150- MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
151-
152- if (dev->hif2) {
153- mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
154- MT_WFDMA0_GLO_CFG_TX_DMA_EN |
155- MT_WFDMA0_GLO_CFG_RX_DMA_EN |
156- MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
157- MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
158-
159- if (is_mt7915(mdev))
160- mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
161- MT_WFDMA1_GLO_CFG_TX_DMA_EN |
162- MT_WFDMA1_GLO_CFG_RX_DMA_EN |
163- MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
164- MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
165-
166- mt76_set(dev, MT_WFDMA_HOST_CONFIG,
167- MT_WFDMA_HOST_CONFIG_PDMA_BAND);
168- }
169-
170- /* enable interrupts for TX/RX rings */
171- irq_mask = MT_INT_RX_DONE_MCU |
172- MT_INT_TX_DONE_MCU |
173- MT_INT_MCU_CMD;
174-
175- if (!dev->phy.mt76->band_idx)
176- irq_mask |= MT_INT_BAND0_RX_DONE;
177-
178- if (dev->dbdc_support || dev->phy.mt76->band_idx)
179- irq_mask |= MT_INT_BAND1_RX_DONE;
180-
181- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
182- u32 wed_irq_mask = irq_mask;
183- int ret;
184-
185- wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
186- if (!is_mt7986(&dev->mt76))
187- mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
188- else
189- mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
190-
191- ret = mt7915_mcu_wed_enable_rx_stats(dev);
192- if (ret)
193- return ret;
194-
195- mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
196- }
197-
198- mt7915_irq_enable(dev, irq_mask);
developer20bb2202023-04-17 09:22:47 +0800199-
200- return 0;
201+ return __mt7915_dma_enable(dev, reset, true);
developer2324aa22023-04-12 11:30:15 +0800202 }
developer20bb2202023-04-17 09:22:47 +0800203
204 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer2324aa22023-04-12 11:30:15 +0800205@@ -560,7 +576,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
206 mt7915_poll_tx);
207 napi_enable(&dev->mt76.tx_napi);
208
209- mt7915_dma_enable(dev);
210+ mt7915_dma_enable(dev, false);
211
212 return 0;
213 }
214@@ -642,7 +658,7 @@ int mt7915_dma_reset(struct mt7915_dev *dev, bool force)
215 mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
216 MT_WFDMA0_EXT0_RXWB_KEEP);
217
218- mt7915_dma_enable(dev);
219+ mt7915_dma_enable(dev, !force);
220
221 return 0;
222 }
223diff --git a/mt7915/mac.c b/mt7915/mac.c
developer1d9da7d2023-04-15 12:45:34 +0800224index 97ca55d..f1fdcfd 100644
developer2324aa22023-04-12 11:30:15 +0800225--- a/mt7915/mac.c
226+++ b/mt7915/mac.c
227@@ -1578,6 +1578,8 @@ void mt7915_mac_reset_work(struct work_struct *work)
228 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA))
229 return;
230
231+ dev_info(dev->mt76.dev,"%s L1 SER recovery start.\n",
232+ wiphy_name(dev->mt76.hw->wiphy));
233 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
234 mtk_wed_device_stop(&dev->mt76.mmio.wed);
235 if (!is_mt7986(&dev->mt76))
236@@ -1615,6 +1617,12 @@ void mt7915_mac_reset_work(struct work_struct *work)
237 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
238 }
239
240+ mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
241+ mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
242+
243+ /* enable dma tx/rx and interrupt */
244+ __mt7915_dma_enable(dev, false, false);
245+
246 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
247 clear_bit(MT76_RESET, &dev->mphy.state);
248 if (phy2)
249@@ -1629,9 +1637,6 @@ void mt7915_mac_reset_work(struct work_struct *work)
250
251 tasklet_schedule(&dev->irq_tasklet);
252
253- mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
254- mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
255-
256 mt76_worker_enable(&dev->mt76.tx_worker);
257
258 local_bh_disable();
259@@ -1653,6 +1658,8 @@ void mt7915_mac_reset_work(struct work_struct *work)
260 ieee80211_queue_delayed_work(ext_phy->hw,
261 &phy2->mt76->mac_work,
262 MT7915_WATCHDOG_TIME);
263+ dev_info(dev->mt76.dev,"%s L1 SER recovery completed.\n",
264+ wiphy_name(dev->mt76.hw->wiphy));
265 }
266
267 /* firmware coredump */
268@@ -1727,6 +1734,10 @@ skip_coredump:
269
270 void mt7915_reset(struct mt7915_dev *dev)
271 {
272+ dev_info(dev->mt76.dev, "%s SER recovery state: 0x%08x\n",
273+ wiphy_name(dev->mt76.hw->wiphy),
274+ READ_ONCE(dev->recovery.state));
275+
276 if (!dev->recovery.hw_init_done)
277 return;
278
279diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer20bb2202023-04-17 09:22:47 +0800280index b66938b..6c40108 100644
developer2324aa22023-04-12 11:30:15 +0800281--- a/mt7915/mt7915.h
282+++ b/mt7915/mt7915.h
283@@ -481,6 +481,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2);
284 void mt7915_dma_prefetch(struct mt7915_dev *dev);
285 void mt7915_dma_cleanup(struct mt7915_dev *dev);
286 int mt7915_dma_reset(struct mt7915_dev *dev, bool force);
developer20bb2202023-04-17 09:22:47 +0800287+int __mt7915_dma_enable(struct mt7915_dev *dev, bool reset, bool wed_reset);
developer2324aa22023-04-12 11:30:15 +0800288 int mt7915_txbf_init(struct mt7915_dev *dev);
289 void mt7915_init_txpower(struct mt7915_dev *dev,
290 struct ieee80211_supported_band *sband);
291--
2922.18.0
293