developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2018 MediaTek Inc. |
| 4 | * Author: Zhanguo Ju <zhanguo.ju@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/kernel.h> |
| 8 | #include <linux/delay.h> |
| 9 | #include <linux/hrtimer.h> |
| 10 | |
| 11 | #include "mt753x.h" |
| 12 | #include "mt753x_regs.h" |
| 13 | |
| 14 | /* MT7531 registers */ |
| 15 | #define SGMII_REG_BASE 0x5000 |
| 16 | #define SGMII_REG_PORT_BASE 0x1000 |
| 17 | #define SGMII_REG(p, r) (SGMII_REG_BASE + \ |
| 18 | (p) * SGMII_REG_PORT_BASE + (r)) |
| 19 | #define PCS_CONTROL_1(p) SGMII_REG(p, 0x00) |
| 20 | #define SGMII_MODE(p) SGMII_REG(p, 0x20) |
| 21 | #define QPHY_PWR_STATE_CTRL(p) SGMII_REG(p, 0xe8) |
| 22 | #define ANA_CKBG(p) SGMII_REG(p, 0x100) |
| 23 | #define ANA_DA_FORCE_MODE1(p) SGMII_REG(p, 0x110) |
| 24 | #define PHYA_CTRL_SIGNAL3(p) SGMII_REG(p, 0x128) |
| 25 | #define PHYA_ANA_SYSPLL(p) SGMII_REG(p, 0x158) |
| 26 | |
| 27 | /* Fields of PCS_CONTROL_1 */ |
| 28 | #define SGMII_LINK_STATUS BIT(18) |
| 29 | #define SGMII_AN_ENABLE BIT(12) |
| 30 | #define SGMII_AN_RESTART BIT(9) |
| 31 | |
| 32 | /* Fields of SGMII_MODE */ |
| 33 | #define SGMII_REMOTE_FAULT_DIS BIT(8) |
| 34 | #define SGMII_IF_MODE_FORCE_DUPLEX BIT(4) |
| 35 | #define SGMII_IF_MODE_FORCE_SPEED_S 0x2 |
| 36 | #define SGMII_IF_MODE_FORCE_SPEED_M 0x0c |
| 37 | #define SGMII_IF_MODE_ADVERT_AN BIT(1) |
| 38 | |
| 39 | /* Values of SGMII_IF_MODE_FORCE_SPEED */ |
| 40 | #define SGMII_IF_MODE_FORCE_SPEED_10 0 |
| 41 | #define SGMII_IF_MODE_FORCE_SPEED_100 1 |
| 42 | #define SGMII_IF_MODE_FORCE_SPEED_1000 2 |
| 43 | |
| 44 | /* Fields of QPHY_PWR_STATE_CTRL */ |
| 45 | #define PHYA_PWD BIT(4) |
| 46 | |
| 47 | /* Fields of ANA_CKBG */ |
| 48 | #define SSUSB_PLL_SSC_EN BIT(21) |
| 49 | |
| 50 | /* Fields of ANA_DA_FORCE_MODE1 */ |
| 51 | #define FORCE_PLL_SSC_EN BIT(30) |
| 52 | |
| 53 | /* Fields of PHYA_CTRL_SIGNAL3 */ |
| 54 | #define RG_TPHY_SPEED_S 2 |
| 55 | #define RG_TPHY_SPEED_M 0x0c |
| 56 | |
| 57 | /* Values of RG_TPHY_SPEED */ |
| 58 | #define RG_TPHY_SPEED_1000 0 |
| 59 | #define RG_TPHY_SPEED_2500 1 |
| 60 | |
| 61 | /* Fields of PHYA_ANA_SYSPLL */ |
| 62 | #define RG_VUSB10_ON BIT(29) |
| 63 | |
| 64 | /* Unique fields of (M)HWSTRAP for MT7531 */ |
| 65 | #define XTAL_FSEL_S 7 |
| 66 | #define XTAL_FSEL_M BIT(7) |
| 67 | #define PHY_EN BIT(6) |
| 68 | #define CHG_STRAP BIT(8) |
| 69 | |
| 70 | /* Efuse Register Define */ |
| 71 | #define GBE_EFUSE 0x7bc8 |
| 72 | #define GBE_SEL_EFUSE_EN BIT(0) |
| 73 | |
| 74 | /* PHY ENABLE Register bitmap define */ |
| 75 | #define PHY_DEV1F 0x1f |
| 76 | #define PHY_DEV1F_REG_44 0x44 |
| 77 | #define PHY_DEV1F_REG_104 0x104 |
| 78 | #define PHY_DEV1F_REG_10A 0x10a |
| 79 | #define PHY_DEV1F_REG_10B 0x10b |
| 80 | #define PHY_DEV1F_REG_10C 0x10c |
| 81 | #define PHY_DEV1F_REG_10D 0x10d |
| 82 | #define PHY_DEV1F_REG_268 0x268 |
| 83 | #define PHY_DEV1F_REG_269 0x269 |
| 84 | #define PHY_DEV1F_REG_26A 0x26A |
| 85 | #define PHY_DEV1F_REG_403 0x403 |
| 86 | |
| 87 | /* Fields of PHY_DEV1F_REG_403 */ |
| 88 | #define GBE_EFUSE_SETTING BIT(3) |
| 89 | #define PHY_EN_BYPASS_MODE BIT(4) |
| 90 | #define POWER_ON_OFF BIT(5) |
| 91 | #define PHY_PLL_M GENMASK(9, 8) |
| 92 | #define PHY_PLL_SEL(x) (((x) << 8) & GENMASK(9, 8)) |
| 93 | |
| 94 | /* PHY EEE Register bitmap of define */ |
| 95 | #define PHY_DEV07 0x07 |
| 96 | #define PHY_DEV07_REG_03C 0x3c |
| 97 | |
| 98 | /* PHY Extend Register 0x14 bitmap of define */ |
| 99 | #define PHY_EXT_REG_14 0x14 |
| 100 | |
| 101 | /* Fields of PHY_EXT_REG_14 */ |
| 102 | #define PHY_EN_DOWN_SHFIT BIT(4) |
| 103 | |
| 104 | /* PHY Extend Register 0x17 bitmap of define */ |
| 105 | #define PHY_EXT_REG_17 0x17 |
| 106 | |
| 107 | /* Fields of PHY_EXT_REG_17 */ |
| 108 | #define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) |
| 109 | |
| 110 | /* PHY PMA Register 0x17 bitmap of define */ |
| 111 | #define SLV_DSP_READY_TIME_S 15 |
| 112 | #define SLV_DSP_READY_TIME_M (0xff << SLV_DSP_READY_TIME_S) |
| 113 | |
| 114 | /* PHY PMA Register 0x18 bitmap of define */ |
| 115 | #define ENABLE_RANDOM_UPDATE_TRIGGER BIT(8) |
| 116 | |
| 117 | /* PHY DEV 0x1e Register bitmap of define */ |
| 118 | #define PHY_DEV1E 0x1e |
| 119 | #define PHY_TX_MLT3_BASE 0x0 |
| 120 | #define PHY_DEV1E_REG_13 0x13 |
| 121 | #define PHY_DEV1E_REG_14 0x14 |
| 122 | #define PHY_DEV1E_REG_41 0x41 |
| 123 | #define PHY_DEV1E_REG_A6 0xa6 |
| 124 | #define PHY_DEV1E_REG_0C6 0x0c6 |
| 125 | #define PHY_DEV1E_REG_0FE 0x0fe |
| 126 | #define PHY_DEV1E_REG_123 0x123 |
| 127 | #define PHY_DEV1E_REG_141 0x141 |
| 128 | #define PHY_DEV1E_REG_189 0x189 |
| 129 | #define PHY_DEV1E_REG_234 0x234 |
| 130 | |
| 131 | /* Fields of PHY_DEV1E_REG_0C6 */ |
| 132 | #define PHY_POWER_SAVING_S 8 |
| 133 | #define PHY_POWER_SAVING_M 0x300 |
| 134 | #define PHY_POWER_SAVING_TX 0x0 |
| 135 | |
| 136 | /* Fields of PHY_DEV1E_REG_189 */ |
| 137 | #define DESCRAMBLER_CLEAR_EN 0x1 |
| 138 | |
| 139 | /* Fields of PHY_DEV1E_REG_234 */ |
| 140 | #define TR_OPEN_LOOP_EN BIT(0) |
| 141 | |
| 142 | /* Port debug count register */ |
| 143 | #define DBG_CNT_BASE 0x3018 |
| 144 | #define DBG_CNT_PORT_BASE 0x100 |
| 145 | #define DBG_CNT(p) (DBG_CNT_BASE + \ |
| 146 | (p) * DBG_CNT_PORT_BASE) |
| 147 | #define DIS_CLR BIT(31) |
| 148 | |
| 149 | /* Values of XTAL_FSEL_S */ |
| 150 | #define XTAL_40MHZ 0 |
| 151 | #define XTAL_25MHZ 1 |
| 152 | |
| 153 | #define PLLGP_EN 0x7820 |
| 154 | #define EN_COREPLL BIT(2) |
| 155 | #define SW_CLKSW BIT(1) |
| 156 | #define SW_PLLGP BIT(0) |
| 157 | |
| 158 | #define PLLGP_CR0 0x78a8 |
| 159 | #define RG_COREPLL_EN BIT(22) |
| 160 | #define RG_COREPLL_POSDIV_S 23 |
| 161 | #define RG_COREPLL_POSDIV_M 0x3800000 |
| 162 | #define RG_COREPLL_SDM_PCW_S 1 |
| 163 | #define RG_COREPLL_SDM_PCW_M 0x3ffffe |
| 164 | #define RG_COREPLL_SDM_PCW_CHG BIT(0) |
| 165 | |
| 166 | /* TOP Signals Status Register */ |
| 167 | #define TOP_SIG_SR 0x780c |
| 168 | #define PAD_MCM_SMI_EN BIT(0) |
| 169 | #define PAD_DUAL_SGMII_EN BIT(1) |
| 170 | |
| 171 | /* RGMII and SGMII PLL clock */ |
| 172 | #define ANA_PLLGP_CR2 0x78b0 |
| 173 | #define ANA_PLLGP_CR5 0x78bc |
| 174 | |
| 175 | /* GPIO mode define */ |
| 176 | #define GPIO_MODE_REGS(x) (0x7c0c + (((x) / 8) * 4)) |
| 177 | #define GPIO_MODE_S 4 |
| 178 | |
| 179 | /* GPIO GROUP IOLB SMT0 Control */ |
| 180 | #define SMT0_IOLB 0x7f04 |
| 181 | #define SMT_IOLB_5_SMI_MDC_EN BIT(5) |
| 182 | |
| 183 | /* Unique fields of PMCR for MT7531 */ |
| 184 | #define FORCE_MODE_EEE1G BIT(25) |
| 185 | #define FORCE_MODE_EEE100 BIT(26) |
| 186 | #define FORCE_MODE_TX_FC BIT(27) |
| 187 | #define FORCE_MODE_RX_FC BIT(28) |
| 188 | #define FORCE_MODE_DPX BIT(29) |
| 189 | #define FORCE_MODE_SPD BIT(30) |
| 190 | #define FORCE_MODE_LNK BIT(31) |
| 191 | #define FORCE_MODE BIT(15) |
| 192 | |
| 193 | #define CHIP_REV 0x781C |
| 194 | #define CHIP_NAME_S 16 |
| 195 | #define CHIP_NAME_M 0xffff0000 |
| 196 | #define CHIP_REV_S 0 |
| 197 | #define CHIP_REV_M 0x0f |
| 198 | #define CHIP_REV_E1 0x0 |
| 199 | |
| 200 | #define CLKGEN_CTRL 0x7500 |
| 201 | #define CLK_SKEW_OUT_S 8 |
| 202 | #define CLK_SKEW_OUT_M 0x300 |
| 203 | #define CLK_SKEW_IN_S 6 |
| 204 | #define CLK_SKEW_IN_M 0xc0 |
| 205 | #define RXCLK_NO_DELAY BIT(5) |
| 206 | #define TXCLK_NO_REVERSE BIT(4) |
| 207 | #define GP_MODE_S 1 |
| 208 | #define GP_MODE_M 0x06 |
| 209 | #define GP_CLK_EN BIT(0) |
| 210 | |
| 211 | #define CPGC_CTRL 0xB0 |
| 212 | #define COL_EN BIT(0) |
| 213 | #define COL_CLK_EN BIT(1) |
| 214 | #define COL_RST_N BIT(2) |
| 215 | #define COL_BUSY BIT(3) |
| 216 | |
| 217 | /* Values of GP_MODE */ |
| 218 | #define GP_MODE_RGMII 0 |
| 219 | #define GP_MODE_MII 1 |
| 220 | #define GP_MODE_REV_MII 2 |
| 221 | |
| 222 | /* Values of CLK_SKEW_IN */ |
| 223 | #define CLK_SKEW_IN_NO_CHANGE 0 |
| 224 | #define CLK_SKEW_IN_DELAY_100PPS 1 |
| 225 | #define CLK_SKEW_IN_DELAY_200PPS 2 |
| 226 | #define CLK_SKEW_IN_REVERSE 3 |
| 227 | |
| 228 | /* Values of CLK_SKEW_OUT */ |
| 229 | #define CLK_SKEW_OUT_NO_CHANGE 0 |
| 230 | #define CLK_SKEW_OUT_DELAY_100PPS 1 |
| 231 | #define CLK_SKEW_OUT_DELAY_200PPS 2 |
| 232 | #define CLK_SKEW_OUT_REVERSE 3 |
| 233 | |
| 234 | /* Proprietory Control Register of Internal Phy device 0x1e */ |
| 235 | #define RXADC_CONTROL_3 0xc2 |
| 236 | #define RXADC_LDO_CONTROL_2 0xd3 |
| 237 | |
| 238 | /* Proprietory Control Register of Internal Phy device 0x1f */ |
| 239 | #define TXVLD_DA_271 0x271 |
| 240 | #define TXVLD_DA_272 0x272 |
| 241 | #define TXVLD_DA_273 0x273 |
| 242 | |
| 243 | /* gpio pinmux pins and functions define */ |
| 244 | static int gpio_int_pins[] = {0}; |
| 245 | static int gpio_int_funcs[] = {1}; |
| 246 | static int gpio_mdc_pins[] = {11, 20}; |
| 247 | static int gpio_mdc_funcs[] = {2, 2}; |
| 248 | static int gpio_mdio_pins[] = {12, 21}; |
| 249 | static int gpio_mdio_funcs[] = {2, 2}; |
| 250 | |
| 251 | static int mt7531_set_port_sgmii_force_mode(struct gsw_mt753x *gsw, u32 port, |
| 252 | struct mt753x_port_cfg *port_cfg) |
| 253 | { |
| 254 | u32 speed, port_base, val; |
| 255 | ktime_t timeout; |
| 256 | u32 timeout_us; |
| 257 | |
| 258 | if (port < 5 || port >= MT753X_NUM_PORTS) { |
| 259 | dev_info(gsw->dev, "port %d is not a SGMII port\n", port); |
| 260 | return -EINVAL; |
| 261 | } |
| 262 | |
| 263 | port_base = port - 5; |
| 264 | |
| 265 | switch (port_cfg->speed) { |
| 266 | case MAC_SPD_1000: |
| 267 | speed = RG_TPHY_SPEED_1000; |
| 268 | break; |
| 269 | case MAC_SPD_2500: |
| 270 | speed = RG_TPHY_SPEED_2500; |
| 271 | break; |
| 272 | default: |
| 273 | dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n", |
| 274 | port_cfg->speed, port); |
| 275 | |
| 276 | speed = RG_TPHY_SPEED_1000; |
| 277 | } |
| 278 | |
| 279 | /* Step 1: Speed select register setting */ |
| 280 | val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base)); |
| 281 | val &= ~RG_TPHY_SPEED_M; |
| 282 | val |= speed << RG_TPHY_SPEED_S; |
| 283 | mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val); |
| 284 | |
| 285 | /* Step 2 : Disable AN */ |
| 286 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); |
| 287 | val &= ~SGMII_AN_ENABLE; |
| 288 | mt753x_reg_write(gsw, PCS_CONTROL_1(port_base), val); |
| 289 | |
| 290 | /* Step 3: SGMII force mode setting */ |
| 291 | val = mt753x_reg_read(gsw, SGMII_MODE(port_base)); |
| 292 | val &= ~SGMII_IF_MODE_ADVERT_AN; |
| 293 | val &= ~SGMII_IF_MODE_FORCE_SPEED_M; |
| 294 | val |= SGMII_IF_MODE_FORCE_SPEED_1000 << SGMII_IF_MODE_FORCE_SPEED_S; |
| 295 | val |= SGMII_IF_MODE_FORCE_DUPLEX; |
| 296 | /* For sgmii force mode, 0 is full duplex and 1 is half duplex */ |
| 297 | if (port_cfg->duplex) |
| 298 | val &= ~SGMII_IF_MODE_FORCE_DUPLEX; |
| 299 | |
| 300 | mt753x_reg_write(gsw, SGMII_MODE(port_base), val); |
| 301 | |
| 302 | /* Step 4: XXX: Disable Link partner's AN and set force mode */ |
| 303 | |
| 304 | /* Step 5: XXX: Special setting for PHYA ==> reserved for flexible */ |
| 305 | |
| 306 | /* Step 6 : Release PHYA power down state */ |
| 307 | val = mt753x_reg_read(gsw, QPHY_PWR_STATE_CTRL(port_base)); |
| 308 | val &= ~PHYA_PWD; |
| 309 | mt753x_reg_write(gsw, QPHY_PWR_STATE_CTRL(port_base), val); |
| 310 | |
| 311 | /* Step 7 : Polling SGMII_LINK_STATUS */ |
| 312 | timeout_us = 2000000; |
| 313 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 314 | while (1) { |
| 315 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); |
| 316 | val &= SGMII_LINK_STATUS; |
| 317 | |
| 318 | if (val) |
| 319 | break; |
| 320 | |
| 321 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 322 | return -ETIMEDOUT; |
| 323 | } |
| 324 | |
| 325 | return 0; |
| 326 | } |
| 327 | |
| 328 | static int mt7531_set_port_sgmii_an_mode(struct gsw_mt753x *gsw, u32 port, |
| 329 | struct mt753x_port_cfg *port_cfg) |
| 330 | { |
| 331 | u32 speed, port_base, val; |
| 332 | ktime_t timeout; |
| 333 | u32 timeout_us; |
| 334 | |
| 335 | if (port < 5 || port >= MT753X_NUM_PORTS) { |
| 336 | dev_info(gsw->dev, "port %d is not a SGMII port\n", port); |
| 337 | return -EINVAL; |
| 338 | } |
| 339 | |
| 340 | port_base = port - 5; |
| 341 | |
| 342 | switch (port_cfg->speed) { |
| 343 | case MAC_SPD_1000: |
| 344 | speed = RG_TPHY_SPEED_1000; |
| 345 | break; |
| 346 | case MAC_SPD_2500: |
| 347 | speed = RG_TPHY_SPEED_2500; |
| 348 | break; |
| 349 | default: |
| 350 | dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n", |
| 351 | port_cfg->speed, port); |
| 352 | |
| 353 | speed = RG_TPHY_SPEED_1000; |
| 354 | } |
| 355 | |
| 356 | /* Step 1: Speed select register setting */ |
| 357 | val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base)); |
| 358 | val &= ~RG_TPHY_SPEED_M; |
| 359 | val |= speed << RG_TPHY_SPEED_S; |
| 360 | mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val); |
| 361 | |
| 362 | /* Step 2: Remote fault disable */ |
| 363 | val = mt753x_reg_read(gsw, SGMII_MODE(port)); |
| 364 | val |= SGMII_REMOTE_FAULT_DIS; |
| 365 | mt753x_reg_write(gsw, SGMII_MODE(port), val); |
| 366 | |
| 367 | /* Step 3: Setting Link partner's AN enable = 1 */ |
| 368 | |
| 369 | /* Step 4: Setting Link partner's device ability for speed/duplex */ |
| 370 | |
| 371 | /* Step 5: AN re-start */ |
| 372 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port)); |
| 373 | val |= SGMII_AN_RESTART; |
| 374 | mt753x_reg_write(gsw, PCS_CONTROL_1(port), val); |
| 375 | |
| 376 | /* Step 6: Special setting for PHYA ==> reserved for flexible */ |
| 377 | |
| 378 | /* Step 7 : Polling SGMII_LINK_STATUS */ |
| 379 | timeout_us = 2000000; |
| 380 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 381 | while (1) { |
| 382 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); |
| 383 | val &= SGMII_LINK_STATUS; |
| 384 | |
| 385 | if (val) |
| 386 | break; |
| 387 | |
| 388 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 389 | return -ETIMEDOUT; |
| 390 | } |
| 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | static void mt7531_sgmii_ssc(struct gsw_mt753x *gsw, u32 port, int enable) |
| 396 | { |
| 397 | u32 val; |
| 398 | u32 port_base = port - 5; |
| 399 | |
| 400 | if (enable) { |
| 401 | val = mt753x_reg_read(gsw, ANA_CKBG(port_base)); |
| 402 | val |= SSUSB_PLL_SSC_EN; |
| 403 | mt753x_reg_write(gsw, ANA_CKBG(port_base), val); |
| 404 | |
| 405 | val = mt753x_reg_read(gsw, ANA_DA_FORCE_MODE1(port_base)); |
| 406 | val |= FORCE_PLL_SSC_EN; |
| 407 | mt753x_reg_write(gsw, ANA_DA_FORCE_MODE1(port_base), val); |
| 408 | } else { |
| 409 | val = mt753x_reg_read(gsw, ANA_CKBG(port_base)); |
| 410 | val &= ~SSUSB_PLL_SSC_EN; |
| 411 | mt753x_reg_write(gsw, ANA_CKBG(port_base), val); |
| 412 | |
| 413 | val = mt753x_reg_read(gsw, ANA_DA_FORCE_MODE1(port_base)); |
| 414 | val &= ~FORCE_PLL_SSC_EN; |
| 415 | mt753x_reg_write(gsw, ANA_DA_FORCE_MODE1(port_base), val); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | static int mt7531_set_port_rgmii(struct gsw_mt753x *gsw, u32 port) |
| 420 | { |
| 421 | u32 val; |
| 422 | |
| 423 | if (port != 5) { |
| 424 | dev_info(gsw->dev, "RGMII mode is not available for port %d\n", |
| 425 | port); |
| 426 | return -EINVAL; |
| 427 | } |
| 428 | |
| 429 | val = mt753x_reg_read(gsw, CLKGEN_CTRL); |
| 430 | val |= GP_CLK_EN; |
| 431 | val &= ~GP_MODE_M; |
| 432 | val |= GP_MODE_RGMII << GP_MODE_S; |
| 433 | val |= TXCLK_NO_REVERSE; |
| 434 | val |= RXCLK_NO_DELAY; |
| 435 | val &= ~CLK_SKEW_IN_M; |
| 436 | val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; |
| 437 | val &= ~CLK_SKEW_OUT_M; |
| 438 | val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; |
| 439 | mt753x_reg_write(gsw, CLKGEN_CTRL, val); |
| 440 | |
| 441 | return 0; |
| 442 | } |
| 443 | |
| 444 | static int mt7531_mac_port_setup(struct gsw_mt753x *gsw, u32 port, |
| 445 | struct mt753x_port_cfg *port_cfg) |
| 446 | { |
| 447 | u32 pmcr; |
| 448 | u32 speed; |
| 449 | |
| 450 | if (port < 5 || port >= MT753X_NUM_PORTS) { |
| 451 | dev_info(gsw->dev, "port %d is not a MAC port\n", port); |
| 452 | return -EINVAL; |
| 453 | } |
| 454 | |
| 455 | if (port_cfg->enabled) { |
| 456 | pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | |
| 457 | MAC_MODE | MAC_TX_EN | MAC_RX_EN | |
| 458 | BKOFF_EN | BACKPR_EN; |
| 459 | |
| 460 | if (port_cfg->force_link) { |
| 461 | /* PMCR's speed field 0x11 is reserved, |
| 462 | * sw should set 0x10 |
| 463 | */ |
| 464 | speed = port_cfg->speed; |
| 465 | if (port_cfg->speed == MAC_SPD_2500) |
| 466 | speed = MAC_SPD_1000; |
| 467 | |
| 468 | pmcr |= FORCE_MODE_LNK | FORCE_LINK | |
| 469 | FORCE_MODE_SPD | FORCE_MODE_DPX | |
| 470 | FORCE_MODE_RX_FC | FORCE_MODE_TX_FC | |
| 471 | FORCE_RX_FC | FORCE_TX_FC | |
| 472 | (speed << FORCE_SPD_S); |
| 473 | |
| 474 | if (port_cfg->duplex) |
| 475 | pmcr |= FORCE_DPX; |
| 476 | } |
| 477 | } else { |
| 478 | pmcr = FORCE_MODE_LNK; |
| 479 | } |
| 480 | |
| 481 | switch (port_cfg->phy_mode) { |
| 482 | case PHY_INTERFACE_MODE_RGMII: |
| 483 | mt7531_set_port_rgmii(gsw, port); |
| 484 | break; |
| 485 | case PHY_INTERFACE_MODE_SGMII: |
| 486 | if (port_cfg->force_link) |
| 487 | mt7531_set_port_sgmii_force_mode(gsw, port, port_cfg); |
| 488 | else |
| 489 | mt7531_set_port_sgmii_an_mode(gsw, port, port_cfg); |
| 490 | |
| 491 | mt7531_sgmii_ssc(gsw, port, port_cfg->ssc_on); |
| 492 | break; |
| 493 | default: |
| 494 | if (port_cfg->enabled) |
| 495 | dev_info(gsw->dev, "%s is not supported by port %d\n", |
| 496 | phy_modes(port_cfg->phy_mode), port); |
| 497 | |
| 498 | pmcr = FORCE_MODE_LNK; |
| 499 | } |
| 500 | |
| 501 | mt753x_reg_write(gsw, PMCR(port), pmcr); |
| 502 | |
| 503 | return 0; |
| 504 | } |
| 505 | |
| 506 | static void mt7531_core_pll_setup(struct gsw_mt753x *gsw) |
| 507 | { |
| 508 | u32 val; |
| 509 | u32 top_sig; |
| 510 | u32 hwstrap; |
| 511 | u32 xtal; |
| 512 | |
| 513 | val = mt753x_reg_read(gsw, CHIP_REV); |
| 514 | top_sig = mt753x_reg_read(gsw, TOP_SIG_SR); |
| 515 | hwstrap = mt753x_reg_read(gsw, HWSTRAP); |
| 516 | if ((val & CHIP_REV_M) > 0) |
| 517 | xtal = (top_sig & PAD_MCM_SMI_EN) ? XTAL_40MHZ : XTAL_25MHZ; |
| 518 | else |
| 519 | xtal = (hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S; |
| 520 | |
| 521 | /* dump HW strap and XTAL */ |
| 522 | dev_info(gsw->dev, "HWSTRAP=0x%x XTAL=%dMHz\n", hwstrap, |
| 523 | (xtal == XTAL_25MHZ) ? 25 : 40); |
| 524 | |
| 525 | /* Only BE needs additional setting */ |
| 526 | if (top_sig & PAD_DUAL_SGMII_EN) |
| 527 | return; |
| 528 | |
| 529 | /* Disable Port5 SGMII clearly */ |
| 530 | val = mt753x_reg_read(gsw, PHYA_ANA_SYSPLL(0)); |
| 531 | val &= ~RG_VUSB10_ON; |
| 532 | mt753x_reg_write(gsw, PHYA_ANA_SYSPLL(0), val); |
| 533 | |
| 534 | switch (xtal) { |
| 535 | case XTAL_25MHZ: |
| 536 | /* Step 1 : Disable MT7531 COREPLL */ |
| 537 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 538 | val &= ~EN_COREPLL; |
| 539 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 540 | |
| 541 | /* Step 2: switch to XTAL output */ |
| 542 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 543 | val |= SW_CLKSW; |
| 544 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 545 | |
| 546 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 547 | val &= ~RG_COREPLL_EN; |
| 548 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 549 | |
| 550 | /* Step 3: disable PLLGP and enable program PLLGP */ |
| 551 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 552 | val |= SW_PLLGP; |
| 553 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 554 | |
| 555 | /* Step 4: program COREPLL output frequency to 500MHz */ |
| 556 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 557 | val &= ~RG_COREPLL_POSDIV_M; |
| 558 | val |= 2 << RG_COREPLL_POSDIV_S; |
| 559 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 560 | usleep_range(25, 35); |
| 561 | |
| 562 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 563 | val &= ~RG_COREPLL_SDM_PCW_M; |
| 564 | val |= 0x140000 << RG_COREPLL_SDM_PCW_S; |
| 565 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 566 | |
| 567 | /* Set feedback divide ratio update signal to high */ |
| 568 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 569 | val |= RG_COREPLL_SDM_PCW_CHG; |
| 570 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 571 | /* Wait for at least 16 XTAL clocks */ |
| 572 | usleep_range(10, 20); |
| 573 | |
| 574 | /* Step 5: set feedback divide ratio update signal to low */ |
| 575 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 576 | val &= ~RG_COREPLL_SDM_PCW_CHG; |
| 577 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 578 | |
| 579 | /* Enable 325M clock for SGMII */ |
| 580 | mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000); |
| 581 | |
| 582 | /* Enable 250SSC clock for RGMII */ |
| 583 | mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000); |
| 584 | |
| 585 | /* Step 6: Enable MT7531 PLL */ |
| 586 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 587 | val |= RG_COREPLL_EN; |
| 588 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 589 | |
| 590 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 591 | val |= EN_COREPLL; |
| 592 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 593 | usleep_range(25, 35); |
| 594 | |
| 595 | break; |
| 596 | case XTAL_40MHZ: |
| 597 | /* Step 1 : Disable MT7531 COREPLL */ |
| 598 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 599 | val &= ~EN_COREPLL; |
| 600 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 601 | |
| 602 | /* Step 2: switch to XTAL output */ |
| 603 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 604 | val |= SW_CLKSW; |
| 605 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 606 | |
| 607 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 608 | val &= ~RG_COREPLL_EN; |
| 609 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 610 | |
| 611 | /* Step 3: disable PLLGP and enable program PLLGP */ |
| 612 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 613 | val |= SW_PLLGP; |
| 614 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 615 | |
| 616 | /* Step 4: program COREPLL output frequency to 500MHz */ |
| 617 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 618 | val &= ~RG_COREPLL_POSDIV_M; |
| 619 | val |= 2 << RG_COREPLL_POSDIV_S; |
| 620 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 621 | usleep_range(25, 35); |
| 622 | |
| 623 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 624 | val &= ~RG_COREPLL_SDM_PCW_M; |
| 625 | val |= 0x190000 << RG_COREPLL_SDM_PCW_S; |
| 626 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 627 | |
| 628 | /* Set feedback divide ratio update signal to high */ |
| 629 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 630 | val |= RG_COREPLL_SDM_PCW_CHG; |
| 631 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 632 | /* Wait for at least 16 XTAL clocks */ |
| 633 | usleep_range(10, 20); |
| 634 | |
| 635 | /* Step 5: set feedback divide ratio update signal to low */ |
| 636 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 637 | val &= ~RG_COREPLL_SDM_PCW_CHG; |
| 638 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 639 | |
| 640 | /* Enable 325M clock for SGMII */ |
| 641 | mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000); |
| 642 | |
| 643 | /* Enable 250SSC clock for RGMII */ |
| 644 | mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000); |
| 645 | |
| 646 | /* Step 6: Enable MT7531 PLL */ |
| 647 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 648 | val |= RG_COREPLL_EN; |
| 649 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 650 | |
| 651 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 652 | val |= EN_COREPLL; |
| 653 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 654 | usleep_range(25, 35); |
| 655 | break; |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw) |
| 660 | { |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | static int mt7531_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev) |
| 665 | { |
| 666 | u32 rev, topsig; |
| 667 | |
| 668 | rev = mt753x_reg_read(gsw, CHIP_REV); |
| 669 | |
| 670 | if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7531) { |
| 671 | if (crev) { |
| 672 | topsig = mt753x_reg_read(gsw, TOP_SIG_SR); |
| 673 | |
| 674 | crev->rev = rev & CHIP_REV_M; |
| 675 | crev->name = topsig & PAD_DUAL_SGMII_EN ? |
| 676 | "MT7531AE" : "MT7531BE"; |
| 677 | } |
| 678 | |
| 679 | return 0; |
| 680 | } |
| 681 | |
| 682 | return -ENODEV; |
| 683 | } |
| 684 | |
| 685 | static void pinmux_set_mux_7531(struct gsw_mt753x *gsw, u32 pin, u32 mode) |
| 686 | { |
| 687 | u32 val; |
| 688 | |
| 689 | val = mt753x_reg_read(gsw, GPIO_MODE_REGS(pin)); |
| 690 | val &= ~(0xf << (pin & 7) * GPIO_MODE_S); |
| 691 | val |= mode << (pin & 7) * GPIO_MODE_S; |
| 692 | mt753x_reg_write(gsw, GPIO_MODE_REGS(pin), val); |
| 693 | } |
| 694 | |
| 695 | static int mt7531_set_gpio_pinmux(struct gsw_mt753x *gsw) |
| 696 | { |
| 697 | u32 group = 0; |
| 698 | struct device_node *np = gsw->dev->of_node; |
| 699 | |
| 700 | /* Set GPIO 0 interrupt mode */ |
| 701 | pinmux_set_mux_7531(gsw, gpio_int_pins[0], gpio_int_funcs[0]); |
| 702 | |
| 703 | of_property_read_u32(np, "mediatek,mdio_master_pinmux", &group); |
| 704 | |
| 705 | /* group = 0: do nothing, 1: 1st group (AE), 2: 2nd group (BE) */ |
| 706 | if (group > 0 && group <= 2) { |
| 707 | group--; |
| 708 | pinmux_set_mux_7531(gsw, gpio_mdc_pins[group], |
| 709 | gpio_mdc_funcs[group]); |
| 710 | pinmux_set_mux_7531(gsw, gpio_mdio_pins[group], |
| 711 | gpio_mdio_funcs[group]); |
| 712 | } |
| 713 | |
| 714 | return 0; |
| 715 | } |
| 716 | |
| 717 | static void mt7531_phy_pll_setup(struct gsw_mt753x *gsw) |
| 718 | { |
| 719 | u32 hwstrap; |
| 720 | u32 val; |
| 721 | |
| 722 | val = mt753x_reg_read(gsw, CHIP_REV); |
| 723 | if ((val & CHIP_REV_M) > 0) |
| 724 | return; |
| 725 | |
| 726 | hwstrap = mt753x_reg_read(gsw, HWSTRAP); |
| 727 | |
| 728 | switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) { |
| 729 | case XTAL_25MHZ: |
| 730 | /* disable pll auto calibration */ |
| 731 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608); |
| 732 | |
| 733 | /* change pll sel */ |
| 734 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, |
| 735 | PHY_DEV1F_REG_403); |
| 736 | val &= ~(PHY_PLL_M); |
| 737 | val |= PHY_PLL_SEL(3); |
| 738 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 739 | |
| 740 | /* set divider ratio */ |
| 741 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 742 | PHY_DEV1F_REG_10A, 0x1009); |
| 743 | |
| 744 | /* set divider ratio */ |
| 745 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0x7c6); |
| 746 | |
| 747 | /* capacitance and resistance adjustment */ |
| 748 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 749 | PHY_DEV1F_REG_10C, 0xa8be); |
| 750 | |
| 751 | break; |
| 752 | case XTAL_40MHZ: |
| 753 | /* disable pll auto calibration */ |
| 754 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608); |
| 755 | |
| 756 | /* change pll sel */ |
| 757 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, |
| 758 | PHY_DEV1F_REG_403); |
| 759 | val &= ~(PHY_PLL_M); |
| 760 | val |= PHY_PLL_SEL(3); |
| 761 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 762 | |
| 763 | /* set divider ratio */ |
| 764 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 765 | PHY_DEV1F_REG_10A, 0x1018); |
| 766 | |
| 767 | /* set divider ratio */ |
| 768 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0xc676); |
| 769 | |
| 770 | /* capacitance and resistance adjustment */ |
| 771 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 772 | PHY_DEV1F_REG_10C, 0xd8be); |
| 773 | break; |
| 774 | } |
| 775 | |
| 776 | /* power down pll. additional delay is not required via mdio access */ |
| 777 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x10); |
| 778 | |
| 779 | /* power up pll */ |
| 780 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x14); |
| 781 | } |
| 782 | |
| 783 | /* 12 registers for TX_MLT3 waveform tuning. |
| 784 | * 012 345 678 9ab |
| 785 | * 1 __ |
| 786 | * _/ \_ |
| 787 | * 0_/ \ |
| 788 | * \_ _/ |
| 789 | * -1 \__/ |
| 790 | */ |
| 791 | static void mt7531_phy_100m_eye_diag_setting(struct gsw_mt753x *gsw, u32 port) |
| 792 | { |
| 793 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x0, 0x187); |
| 794 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x1, 0x1c9); |
| 795 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x2, 0x1c6); |
| 796 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x3, 0x182); |
| 797 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x4, 0x208); |
| 798 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x5, 0x205); |
| 799 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x6, 0x384); |
| 800 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x7, 0x3cb); |
| 801 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x8, 0x3c4); |
| 802 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x9, 0x30a); |
| 803 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0xa, 0x00b); |
| 804 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0xb, 0x002); |
| 805 | } |
| 806 | |
| 807 | static void mt7531_phy_setting(struct gsw_mt753x *gsw) |
| 808 | { |
| 809 | int i; |
| 810 | u32 val; |
| 811 | |
| 812 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 813 | mt7531_phy_100m_eye_diag_setting(gsw, i); |
| 814 | |
| 815 | /* Enable HW auto downshift */ |
| 816 | gsw->mii_write(gsw, i, 0x1f, 0x1); |
| 817 | val = gsw->mii_read(gsw, i, PHY_EXT_REG_14); |
| 818 | val |= PHY_EN_DOWN_SHFIT; |
| 819 | gsw->mii_write(gsw, i, PHY_EXT_REG_14, val); |
| 820 | |
| 821 | /* Decrease SlvDPSready time */ |
| 822 | val = mt753x_tr_read(gsw, i, PMA_CH, PMA_NOD, PMA_17); |
| 823 | val &= ~SLV_DSP_READY_TIME_M; |
| 824 | val |= 0xc << SLV_DSP_READY_TIME_S; |
| 825 | mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_17, val); |
| 826 | |
| 827 | /* Enable Random Update Mechanism */ |
| 828 | val = mt753x_tr_read(gsw, i, PMA_CH, PMA_NOD, PMA_18); |
| 829 | val |= ENABLE_RANDOM_UPDATE_TRIGGER; |
| 830 | mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_18, val); |
| 831 | |
| 832 | /* PHY link down power saving enable */ |
| 833 | val = gsw->mii_read(gsw, i, PHY_EXT_REG_17); |
| 834 | val |= PHY_LINKDOWN_POWER_SAVING_EN; |
| 835 | gsw->mii_write(gsw, i, PHY_EXT_REG_17, val); |
| 836 | |
| 837 | val = gsw->mmd_read(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6); |
| 838 | val &= ~PHY_POWER_SAVING_M; |
| 839 | val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; |
| 840 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6, val); |
| 841 | |
| 842 | /* Timing Recovery for GbE slave mode */ |
| 843 | mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_01, 0x6fb90a); |
| 844 | mt753x_tr_write(gsw, i, DSP_CH, DSP_NOD, DSP_06, 0x2ebaef); |
| 845 | val = gsw->mmd_read(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_234); |
| 846 | val |= TR_OPEN_LOOP_EN; |
| 847 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_234, val); |
| 848 | |
| 849 | /* Enable Asymmetric Pause Capability */ |
| 850 | val = gsw->mii_read(gsw, i, MII_ADVERTISE); |
| 851 | val |= ADVERTISE_PAUSE_ASYM; |
| 852 | gsw->mii_write(gsw, i, MII_ADVERTISE, val); |
| 853 | } |
| 854 | } |
| 855 | |
| 856 | static void mt7531_adjust_line_driving(struct gsw_mt753x *gsw, u32 port) |
| 857 | { |
| 858 | /* For ADC timing margin window for LDO calibration */ |
| 859 | gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_LDO_CONTROL_2, 0x2222); |
| 860 | |
| 861 | /* Adjust AD sample timing */ |
| 862 | gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_CONTROL_3, 0x4444); |
| 863 | |
| 864 | /* Adjust Line driver current for different mode */ |
| 865 | gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_271, 0x2ca5); |
| 866 | |
| 867 | /* Adjust Line driver current for different mode */ |
| 868 | gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_272, 0xc6b); |
| 869 | |
| 870 | /* Adjust Line driver gain for 10BT from 1000BT calibration result */ |
| 871 | gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_273, 0x3000); |
| 872 | |
| 873 | /* Adjust RX Echo path filter */ |
| 874 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2); |
| 875 | |
| 876 | /* Adjust RX HVGA bias current */ |
| 877 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_41, 0x3333); |
| 878 | |
| 879 | /* Adjust TX class AB driver 1 */ |
| 880 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_268, 0x384); |
| 881 | |
| 882 | /* Adjust TX class AB driver 2 */ |
| 883 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_269, 0x1114); |
| 884 | |
| 885 | /* Adjust DAC delay for TX Pairs */ |
| 886 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_13, 0x404); |
| 887 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_14, 0x404); |
| 888 | |
| 889 | /* Adjust DAC digital delay for TX Delay */ |
| 890 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_44, 0xc0); |
| 891 | |
| 892 | /* Adjust Line driver compensation cap for stability concern due to |
| 893 | * increase current. |
| 894 | */ |
| 895 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_26A, 0x3333); |
| 896 | } |
| 897 | |
| 898 | static void mt7531_eee_setting(struct gsw_mt753x *gsw, u32 port) |
| 899 | { |
| 900 | u32 val; |
| 901 | |
| 902 | /* Disable EEE */ |
| 903 | gsw->mmd_write(gsw, port, PHY_DEV07, PHY_DEV07_REG_03C, 0); |
| 904 | |
| 905 | /* Disable generate signal to clear the scramble_lock when lpi mode */ |
| 906 | val = gsw->mmd_read(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189); |
| 907 | val &= ~DESCRAMBLER_CLEAR_EN; |
| 908 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189, val); |
| 909 | |
| 910 | /* Roll back EEE Slave Mode */ |
| 911 | gsw->mmd_write(gsw, port, 0x1e, 0x2d1, 0); |
| 912 | mt753x_tr_write(gsw, port, DSP_CH, DSP_NOD, DSP_08, 0x1b); |
| 913 | mt753x_tr_write(gsw, port, DSP_CH, DSP_NOD, DSP_0f, 0); |
| 914 | mt753x_tr_write(gsw, port, DSP_CH, DSP_NOD, DSP_10, 0x5000); |
| 915 | |
| 916 | /* Adjust 100_mse_threshold */ |
| 917 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff); |
| 918 | |
| 919 | /* Disable mcc */ |
| 920 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300); |
| 921 | } |
| 922 | |
| 923 | static void mt7531_afifo_reset(struct gsw_mt753x *gsw, int enable) |
| 924 | { |
| 925 | int p; |
| 926 | u32 val; |
| 927 | |
| 928 | if (enable) { |
| 929 | for (p = 0; p < MT753X_NUM_PORTS; p++) { |
| 930 | val = mt753x_reg_read(gsw, DBG_CNT(p)); |
| 931 | val &= ~DIS_CLR; |
| 932 | mt753x_reg_write(gsw, DBG_CNT(p), val); |
| 933 | } |
| 934 | } else { |
| 935 | for (p = 0; p < MT753X_NUM_PORTS; p++) { |
| 936 | val = mt753x_reg_read(gsw, DBG_CNT(p)); |
| 937 | val |= DIS_CLR; |
| 938 | mt753x_reg_write(gsw, DBG_CNT(p), val); |
| 939 | } |
| 940 | } |
| 941 | } |
| 942 | |
| 943 | static int mt7531_sw_init(struct gsw_mt753x *gsw) |
| 944 | { |
| 945 | int i; |
| 946 | u32 val; |
| 947 | |
| 948 | gsw->phy_base = (gsw->smi_addr + 1) & MT753X_SMI_ADDR_MASK; |
| 949 | |
| 950 | gsw->mii_read = mt753x_mii_read; |
| 951 | gsw->mii_write = mt753x_mii_write; |
| 952 | gsw->mmd_read = mt753x_mmd_read; |
| 953 | gsw->mmd_write = mt753x_mmd_write; |
| 954 | |
| 955 | gsw->hw_phy_cal = of_property_read_bool(gsw->dev->of_node, "mediatek,hw_phy_cal"); |
| 956 | |
| 957 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 958 | val = gsw->mii_read(gsw, i, MII_BMCR); |
| 959 | val |= BMCR_ISOLATE; |
| 960 | gsw->mii_write(gsw, i, MII_BMCR, val); |
| 961 | } |
| 962 | |
| 963 | /* Force MAC link down before reset */ |
| 964 | mt753x_reg_write(gsw, PMCR(5), FORCE_MODE_LNK); |
| 965 | mt753x_reg_write(gsw, PMCR(6), FORCE_MODE_LNK); |
| 966 | |
| 967 | /* Switch soft reset */ |
| 968 | mt753x_reg_write(gsw, SYS_CTRL, SW_SYS_RST | SW_REG_RST); |
| 969 | usleep_range(10, 20); |
| 970 | |
| 971 | /* Enable MDC input Schmitt Trigger */ |
| 972 | val = mt753x_reg_read(gsw, SMT0_IOLB); |
| 973 | mt753x_reg_write(gsw, SMT0_IOLB, val | SMT_IOLB_5_SMI_MDC_EN); |
| 974 | |
| 975 | /* Set 7531 gpio pinmux */ |
| 976 | mt7531_set_gpio_pinmux(gsw); |
| 977 | |
| 978 | mt7531_core_pll_setup(gsw); |
| 979 | mt7531_mac_port_setup(gsw, 5, &gsw->port5_cfg); |
| 980 | mt7531_mac_port_setup(gsw, 6, &gsw->port6_cfg); |
| 981 | |
| 982 | /* Global mac control settings */ |
| 983 | mt753x_reg_write(gsw, GMACCR, |
| 984 | (15 << MTCC_LMT_S) | (15 << MAX_RX_JUMBO_S) | |
| 985 | RX_PKT_LEN_MAX_JUMBO); |
| 986 | |
| 987 | /* Enable Collision Poll */ |
| 988 | val = mt753x_reg_read(gsw, CPGC_CTRL); |
| 989 | val |= COL_CLK_EN; |
| 990 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 991 | val |= COL_RST_N; |
| 992 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 993 | val |= COL_EN; |
| 994 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 995 | |
| 996 | /* Disable AFIFO reset for extra short IPG */ |
| 997 | mt7531_afifo_reset(gsw, 0); |
| 998 | |
| 999 | return 0; |
| 1000 | } |
| 1001 | |
| 1002 | static int mt7531_sw_post_init(struct gsw_mt753x *gsw) |
| 1003 | { |
| 1004 | int i; |
| 1005 | u32 val; |
| 1006 | |
| 1007 | /* Let internal PHYs only Tx constant data in configure stage. */ |
| 1008 | for (i = 0; i < MT753X_NUM_PHYS; i++) |
| 1009 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_141, 0x200); |
| 1010 | |
| 1011 | /* Internal PHYs might be enabled by HW Bootstrapping, or bootloader. |
| 1012 | * Turn off PHYs before setup PHY PLL. |
| 1013 | */ |
| 1014 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403); |
| 1015 | val |= PHY_EN_BYPASS_MODE; |
| 1016 | val |= POWER_ON_OFF; |
| 1017 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 1018 | |
| 1019 | mt7531_phy_pll_setup(gsw); |
| 1020 | |
| 1021 | /* Enable Internal PHYs before phy setting */ |
| 1022 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403); |
| 1023 | val |= PHY_EN_BYPASS_MODE; |
| 1024 | val &= ~POWER_ON_OFF; |
| 1025 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 1026 | |
| 1027 | mt7531_phy_setting(gsw); |
| 1028 | |
| 1029 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 1030 | val = gsw->mii_read(gsw, i, MII_BMCR); |
| 1031 | val &= ~BMCR_ISOLATE; |
| 1032 | gsw->mii_write(gsw, i, MII_BMCR, val); |
| 1033 | } |
| 1034 | |
| 1035 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 1036 | mt7531_adjust_line_driving(gsw, i); |
| 1037 | mt7531_eee_setting(gsw, i); |
| 1038 | } |
| 1039 | |
| 1040 | /* Restore internal PHYs normal Tx function after configure stage. */ |
| 1041 | for (i = 0; i < MT753X_NUM_PHYS; i++) |
| 1042 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_141, 0x0); |
| 1043 | |
| 1044 | mt7531_internal_phy_calibration(gsw); |
| 1045 | |
| 1046 | return 0; |
| 1047 | } |
| 1048 | |
| 1049 | struct mt753x_sw_id mt7531_id = { |
| 1050 | .model = MT7531, |
| 1051 | .detect = mt7531_sw_detect, |
| 1052 | .init = mt7531_sw_init, |
| 1053 | .post_init = mt7531_sw_post_init |
| 1054 | }; |
| 1055 | |
| 1056 | MODULE_LICENSE("GPL"); |
| 1057 | MODULE_AUTHOR("Zhanguo Ju <zhanguo.ju@mediatek.com>"); |
| 1058 | MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch"); |