developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From ac7be09336555cf993d904bd9e42c05d1769288a Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:12 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [spi-and-storage][999-2323-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch] |
developer | 41370d5 | 2022-03-16 16:01:59 +0800 | [diff] [blame] | 6 | |
developer | 41370d5 | 2022-03-16 16:01:59 +0800 | [diff] [blame] | 7 | --- |
| 8 | drivers/mtd/nand/spi/micron.c | 58 +++++++++++++++++++++++++++++++++++ |
| 9 | 1 file changed, 58 insertions(+) |
| 10 | |
| 11 | diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 12 | index d6fd63008..5d370cfcd 100644 |
developer | 41370d5 | 2022-03-16 16:01:59 +0800 | [diff] [blame] | 13 | --- a/drivers/mtd/nand/spi/micron.c |
| 14 | +++ b/drivers/mtd/nand/spi/micron.c |
| 15 | @@ -20,6 +20,14 @@ |
| 16 | |
| 17 | #define MICRON_CFG_CR BIT(0) |
| 18 | |
| 19 | +/* |
| 20 | + * As per datasheet, die selection is done by the 6th bit of Die |
| 21 | + * Select Register (Address 0xD0). |
| 22 | + */ |
| 23 | +#define MICRON_DIE_SELECT_REG 0xD0 |
| 24 | + |
| 25 | +#define MICRON_SELECT_DIE(x) ((x) << 6) |
| 26 | + |
| 27 | static SPINAND_OP_VARIANTS(read_cache_variants, |
| 28 | SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| 29 | SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| 30 | @@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = { |
| 31 | .free = micron_8_ooblayout_free, |
| 32 | }; |
| 33 | |
| 34 | +static int micron_select_target(struct spinand_device *spinand, |
| 35 | + unsigned int target) |
| 36 | +{ |
| 37 | + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG, |
| 38 | + spinand->scratchbuf); |
| 39 | + |
| 40 | + if (target > 1) |
| 41 | + return -EINVAL; |
| 42 | + |
| 43 | + *spinand->scratchbuf = MICRON_SELECT_DIE(target); |
| 44 | + |
| 45 | + return spi_mem_exec_op(spinand->spimem, &op); |
| 46 | +} |
| 47 | + |
| 48 | static int micron_8_ecc_get_status(struct spinand_device *spinand, |
| 49 | u8 status) |
| 50 | { |
| 51 | @@ -137,6 +159,18 @@ static const struct spinand_info micron_spinand_table[] = { |
| 52 | 0, |
| 53 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 54 | micron_8_ecc_get_status)), |
| 55 | + /* M79A 4Gb 3.3V */ |
| 56 | + SPINAND_INFO("MT29F4G01ADAGD", |
| 57 | + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), |
| 58 | + NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2), |
| 59 | + NAND_ECCREQ(8, 512), |
| 60 | + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 61 | + &write_cache_variants, |
| 62 | + &update_cache_variants), |
| 63 | + 0, |
| 64 | + SPINAND_ECCINFO(µn_8_ooblayout, |
| 65 | + micron_8_ecc_get_status), |
| 66 | + SPINAND_SELECT_TARGET(micron_select_target)), |
| 67 | /* M70A 4Gb 3.3V */ |
| 68 | SPINAND_INFO("MT29F4G01ABAFD", |
| 69 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), |
| 70 | @@ -159,6 +193,30 @@ static const struct spinand_info micron_spinand_table[] = { |
| 71 | SPINAND_HAS_CR_FEAT_BIT, |
| 72 | SPINAND_ECCINFO(µn_8_ooblayout, |
| 73 | micron_8_ecc_get_status)), |
| 74 | + /* M70A 8Gb 3.3V */ |
| 75 | + SPINAND_INFO("MT29F8G01ADAFD", |
| 76 | + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), |
| 77 | + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), |
| 78 | + NAND_ECCREQ(8, 512), |
| 79 | + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 80 | + &write_cache_variants, |
| 81 | + &update_cache_variants), |
| 82 | + SPINAND_HAS_CR_FEAT_BIT, |
| 83 | + SPINAND_ECCINFO(µn_8_ooblayout, |
| 84 | + micron_8_ecc_get_status), |
| 85 | + SPINAND_SELECT_TARGET(micron_select_target)), |
| 86 | + /* M70A 8Gb 1.8V */ |
| 87 | + SPINAND_INFO("MT29F8G01ADBFD", |
| 88 | + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), |
| 89 | + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), |
| 90 | + NAND_ECCREQ(8, 512), |
| 91 | + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 92 | + &write_cache_variants, |
| 93 | + &update_cache_variants), |
| 94 | + SPINAND_HAS_CR_FEAT_BIT, |
| 95 | + SPINAND_ECCINFO(µn_8_ooblayout, |
| 96 | + micron_8_ecc_get_status), |
| 97 | + SPINAND_SELECT_TARGET(micron_select_target)), |
| 98 | }; |
| 99 | |
| 100 | static int micron_spinand_init(struct spinand_device *spinand) |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 101 | -- |
| 102 | 2.34.1 |
| 103 | |