[][backport: mtd: spinand: Add newest SPINAND devices & 2nd deivce ID support]
[Description]
Add newest SPI NAND device support.
Support 2nd device ID.
[Release-log]
N/A
Change-Id: Idfb461ebf8931d531eb1f2427342b41ab4400a29
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5746844
diff --git a/target/linux/generic/backport-5.4/455-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch b/target/linux/generic/backport-5.4/455-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch
new file mode 100644
index 0000000..8f8f1da
--- /dev/null
+++ b/target/linux/generic/backport-5.4/455-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch
@@ -0,0 +1,109 @@
+From 9f9ae0c253c1e058fbc845e26c4a32a7d777f0dc Mon Sep 17 00:00:00 2001
+From: Shivamurthy Shastri <sshivamurthy@micron.com>
+Date: Wed, 11 Mar 2020 18:57:35 +0100
+Subject: [PATCH] mtd: spinand: micron: Add new Micron SPI NAND devices with
+ multiple dies
+
+Add device table for new Micron SPI NAND devices, which have multiple
+dies.
+
+Also, enable support to select the dies.
+
+Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
+Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200311175735.2007-7-sshivamurthy@micron.com
+---
+ drivers/mtd/nand/spi/micron.c | 58 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
+index d6fd630087822c..5d370cfcdaaaa9 100644
+--- a/drivers/mtd/nand/spi/micron.c
++++ b/drivers/mtd/nand/spi/micron.c
+@@ -20,6 +20,14 @@
+
+ #define MICRON_CFG_CR BIT(0)
+
++/*
++ * As per datasheet, die selection is done by the 6th bit of Die
++ * Select Register (Address 0xD0).
++ */
++#define MICRON_DIE_SELECT_REG 0xD0
++
++#define MICRON_SELECT_DIE(x) ((x) << 6)
++
+ static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+@@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = {
+ .free = micron_8_ooblayout_free,
+ };
+
++static int micron_select_target(struct spinand_device *spinand,
++ unsigned int target)
++{
++ struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
++ spinand->scratchbuf);
++
++ if (target > 1)
++ return -EINVAL;
++
++ *spinand->scratchbuf = MICRON_SELECT_DIE(target);
++
++ return spi_mem_exec_op(spinand->spimem, &op);
++}
++
+ static int micron_8_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+ {
+@@ -137,6 +159,18 @@ static const struct spinand_info micron_spinand_table[] = {
+ 0,
+ SPINAND_ECCINFO(µn_8_ooblayout,
+ micron_8_ecc_get_status)),
++ /* M79A 4Gb 3.3V */
++ SPINAND_INFO("MT29F4G01ADAGD",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
++ NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_variants,
++ &update_cache_variants),
++ 0,
++ SPINAND_ECCINFO(µn_8_ooblayout,
++ micron_8_ecc_get_status),
++ SPINAND_SELECT_TARGET(micron_select_target)),
+ /* M70A 4Gb 3.3V */
+ SPINAND_INFO("MT29F4G01ABAFD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
+@@ -159,6 +193,30 @@ static const struct spinand_info micron_spinand_table[] = {
+ SPINAND_HAS_CR_FEAT_BIT,
+ SPINAND_ECCINFO(µn_8_ooblayout,
+ micron_8_ecc_get_status)),
++ /* M70A 8Gb 3.3V */
++ SPINAND_INFO("MT29F8G01ADAFD",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_variants,
++ &update_cache_variants),
++ SPINAND_HAS_CR_FEAT_BIT,
++ SPINAND_ECCINFO(µn_8_ooblayout,
++ micron_8_ecc_get_status),
++ SPINAND_SELECT_TARGET(micron_select_target)),
++ /* M70A 8Gb 1.8V */
++ SPINAND_INFO("MT29F8G01ADBFD",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_variants,
++ &update_cache_variants),
++ SPINAND_HAS_CR_FEAT_BIT,
++ SPINAND_ECCINFO(µn_8_ooblayout,
++ micron_8_ecc_get_status),
++ SPINAND_SELECT_TARGET(micron_select_target)),
+ };
+
+ static int micron_spinand_init(struct spinand_device *spinand)