developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 MediaTek Inc. |
| 4 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _MT753X_H_ |
| 8 | #define _MT753X_H_ |
| 9 | |
| 10 | #include <linux/list.h> |
| 11 | #include <linux/mutex.h> |
| 12 | #include <linux/netdevice.h> |
| 13 | #include <linux/of_mdio.h> |
| 14 | #include <linux/workqueue.h> |
| 15 | #include <linux/gpio/consumer.h> |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 16 | #include <linux/phy.h> |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 17 | |
| 18 | #ifdef CONFIG_SWCONFIG |
| 19 | #include <linux/switch.h> |
| 20 | #endif |
| 21 | |
| 22 | #include "mt753x_vlan.h" |
| 23 | |
| 24 | #define MT753X_DFL_CPU_PORT 6 |
| 25 | #define MT753X_NUM_PHYS 5 |
| 26 | |
| 27 | #define MT753X_DFL_SMI_ADDR 0x1f |
| 28 | #define MT753X_SMI_ADDR_MASK 0x1f |
| 29 | |
| 30 | struct gsw_mt753x; |
| 31 | |
| 32 | enum mt753x_model { |
| 33 | MT7530 = 0x7530, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 34 | MT7531 = 0x7531, |
| 35 | MT7988 = 0x7988, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 36 | }; |
| 37 | |
| 38 | struct mt753x_port_cfg { |
| 39 | struct device_node *np; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 40 | phy_interface_t phy_mode; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 41 | u32 enabled: 1; |
| 42 | u32 force_link: 1; |
| 43 | u32 speed: 2; |
| 44 | u32 duplex: 1; |
| 45 | bool ssc_on; |
| 46 | bool stag_on; |
| 47 | }; |
| 48 | |
| 49 | struct mt753x_phy { |
| 50 | struct gsw_mt753x *gsw; |
| 51 | struct net_device netdev; |
| 52 | struct phy_device *phydev; |
| 53 | }; |
| 54 | |
| 55 | struct gsw_mt753x { |
| 56 | u32 id; |
| 57 | |
| 58 | struct device *dev; |
| 59 | struct mii_bus *host_bus; |
| 60 | struct mii_bus *gphy_bus; |
| 61 | struct mutex mii_lock; /* MII access lock */ |
| 62 | u32 smi_addr; |
| 63 | u32 phy_base; |
| 64 | int direct_phy_access; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 65 | bool direct_access; |
| 66 | |
| 67 | void __iomem *base; |
| 68 | struct regmap *sysctrl_base; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 69 | |
| 70 | enum mt753x_model model; |
| 71 | const char *name; |
| 72 | |
| 73 | struct mt753x_port_cfg port5_cfg; |
| 74 | struct mt753x_port_cfg port6_cfg; |
| 75 | |
| 76 | bool hw_phy_cal; |
| 77 | bool phy_status_poll; |
| 78 | struct mt753x_phy phys[MT753X_NUM_PHYS]; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 79 | // int phy_irqs[PHY_MAX_ADDR]; //FIXME |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 80 | |
| 81 | int phy_link_sts; |
| 82 | |
| 83 | int irq; |
| 84 | int reset_pin; |
| 85 | struct work_struct irq_worker; |
| 86 | |
| 87 | #ifdef CONFIG_SWCONFIG |
| 88 | struct switch_dev swdev; |
| 89 | u32 cpu_port; |
| 90 | #endif |
| 91 | |
| 92 | int global_vlan_enable; |
| 93 | struct mt753x_vlan_entry vlan_entries[MT753X_NUM_VLANS]; |
| 94 | struct mt753x_port_entry port_entries[MT753X_NUM_PORTS]; |
| 95 | |
| 96 | int (*mii_read)(struct gsw_mt753x *gsw, int phy, int reg); |
| 97 | void (*mii_write)(struct gsw_mt753x *gsw, int phy, int reg, u16 val); |
| 98 | |
| 99 | int (*mmd_read)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg); |
| 100 | void (*mmd_write)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, |
| 101 | u16 val); |
| 102 | |
| 103 | struct list_head list; |
| 104 | }; |
| 105 | |
| 106 | struct chip_rev { |
| 107 | const char *name; |
| 108 | u32 rev; |
| 109 | }; |
| 110 | |
| 111 | struct mt753x_sw_id { |
| 112 | enum mt753x_model model; |
| 113 | int (*detect)(struct gsw_mt753x *gsw, struct chip_rev *crev); |
| 114 | int (*init)(struct gsw_mt753x *gsw); |
| 115 | int (*post_init)(struct gsw_mt753x *gsw); |
| 116 | }; |
| 117 | |
| 118 | extern struct list_head mt753x_devs; |
| 119 | |
| 120 | struct gsw_mt753x *mt753x_get_gsw(u32 id); |
| 121 | struct gsw_mt753x *mt753x_get_first_gsw(void); |
| 122 | void mt753x_put_gsw(void); |
| 123 | void mt753x_lock_gsw(void); |
| 124 | |
| 125 | u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg); |
| 126 | void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val); |
| 127 | |
| 128 | int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg); |
| 129 | void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val); |
| 130 | |
| 131 | int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg); |
| 132 | void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, |
| 133 | u16 val); |
| 134 | |
| 135 | int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg); |
| 136 | void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, |
| 137 | u16 val); |
| 138 | |
| 139 | int mt753x_tr_read(struct gsw_mt753x *gsw, int addr, u8 ch, u8 node, u8 daddr); |
| 140 | void mt753x_tr_write(struct gsw_mt753x *gsw, int addr, u8 ch, u8 node, u8 daddr, |
| 141 | u32 data); |
| 142 | |
| 143 | void mt753x_irq_worker(struct work_struct *work); |
| 144 | void mt753x_irq_enable(struct gsw_mt753x *gsw); |
| 145 | |
| 146 | int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr); |
| 147 | int extphy_init(struct gsw_mt753x *gsw, int addr); |
| 148 | |
| 149 | /* MDIO Indirect Access Registers */ |
| 150 | #define MII_MMD_ACC_CTL_REG 0x0d |
| 151 | #define MMD_CMD_S 14 |
| 152 | #define MMD_CMD_M 0xc000 |
| 153 | #define MMD_DEVAD_S 0 |
| 154 | #define MMD_DEVAD_M 0x1f |
| 155 | |
| 156 | /* MMD_CMD: MMD commands */ |
| 157 | #define MMD_ADDR 0 |
| 158 | #define MMD_DATA 1 |
| 159 | |
| 160 | #define MII_MMD_ADDR_DATA_REG 0x0e |
| 161 | |
| 162 | /* Procedure of MT753x Internal Register Access |
| 163 | * |
| 164 | * 1. Internal Register Address |
| 165 | * |
| 166 | * The MT753x has a 16-bit register address and each register is 32-bit. |
| 167 | * This means the lowest two bits are not used as the register address is |
| 168 | * 4-byte aligned. |
| 169 | * |
| 170 | * Rest of the valid bits are divided into two parts: |
| 171 | * Bit 15..6 is the Page address |
| 172 | * Bit 5..2 is the low address |
| 173 | * |
| 174 | * ------------------------------------------------------------------- |
| 175 | * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | |
| 176 | * |----------------------------------------|---------------|--------| |
| 177 | * | Page Address | Address | Unused | |
| 178 | * ------------------------------------------------------------------- |
| 179 | * |
| 180 | * 2. MDIO access timing |
| 181 | * |
| 182 | * The MT753x uses the following MDIO timing for a single register read |
| 183 | * |
| 184 | * Phase 1: Write Page Address |
| 185 | * ------------------------------------------------------------------- |
| 186 | * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | RSVD | PAGE_ADDR | |
| 187 | * ------------------------------------------------------------------- |
| 188 | * | 01 | 01 | 11111 | 1 | 1111 | xx | 00000 | REG_ADDR[15..6] | |
| 189 | * ------------------------------------------------------------------- |
| 190 | * |
| 191 | * Phase 2: Write low Address & Read low word |
| 192 | * ------------------------------------------------------------------- |
| 193 | * | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA | |
| 194 | * ------------------------------------------------------------------- |
| 195 | * | 01 | 10 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] | |
| 196 | * ------------------------------------------------------------------- |
| 197 | * |
| 198 | * Phase 3: Read high word |
| 199 | * ------------------------------------------------------------------- |
| 200 | * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA | |
| 201 | * ------------------------------------------------------------------- |
| 202 | * | 01 | 10 | 11111 | 1 | 0000 | xx | DATA[31..16] | |
| 203 | * ------------------------------------------------------------------- |
| 204 | * |
| 205 | * The MT753x uses the following MDIO timing for a single register write |
| 206 | * |
| 207 | * Phase 1: Write Page Address (The same as read) |
| 208 | * |
| 209 | * Phase 2: Write low Address and low word |
| 210 | * ------------------------------------------------------------------- |
| 211 | * | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA | |
| 212 | * ------------------------------------------------------------------- |
| 213 | * | 01 | 01 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] | |
| 214 | * ------------------------------------------------------------------- |
| 215 | * |
| 216 | * Phase 3: write high word |
| 217 | * ------------------------------------------------------------------- |
| 218 | * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA | |
| 219 | * ------------------------------------------------------------------- |
| 220 | * | 01 | 01 | 11111 | 1 | 0000 | xx | DATA[31..16] | |
| 221 | * ------------------------------------------------------------------- |
| 222 | * |
| 223 | */ |
| 224 | |
| 225 | /* Internal Register Address fields */ |
| 226 | #define MT753X_REG_PAGE_ADDR_S 6 |
| 227 | #define MT753X_REG_PAGE_ADDR_M 0xffc0 |
| 228 | #define MT753X_REG_ADDR_S 2 |
| 229 | #define MT753X_REG_ADDR_M 0x3c |
| 230 | #endif /* _MT753X_H_ */ |