| developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * mt79xx-reg.h -- Mediatek 79xx audio driver reg definition |
| 4 | * |
| 5 | * Copyright (c) 2021 MediaTek Inc. |
| 6 | * Author: Vic Wu <vic.wu@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef _MT79XX_REG_H_ |
| 10 | #define _MT79XX_REG_H_ |
| 11 | |
| 12 | #define AUDIO_TOP_CON2 0x0008 |
| 13 | #define AUDIO_TOP_CON4 0x0010 |
| 14 | #define AUDIO_ENGEN_CON0 0x0014 |
| 15 | #define AFE_IRQ_MCU_EN 0x0100 |
| 16 | #define AFE_IRQ_MCU_STATUS 0x0120 |
| 17 | #define AFE_IRQ_MCU_CLR 0x0128 |
| 18 | #define AFE_IRQ0_MCU_CFG0 0x0140 |
| 19 | #define AFE_IRQ0_MCU_CFG1 0x0144 |
| 20 | #define AFE_IRQ1_MCU_CFG0 0x0148 |
| 21 | #define AFE_IRQ1_MCU_CFG1 0x014c |
| developer | 0426ed2 | 2022-01-07 10:49:03 +0800 | [diff] [blame] | 22 | #define AFE_IRQ2_MCU_CFG0 0x0150 |
| 23 | #define AFE_IRQ2_MCU_CFG1 0x0154 |
| developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 24 | #define ETDM_IN5_CON0 0x13f0 |
| 25 | #define ETDM_IN5_CON1 0x13f4 |
| 26 | #define ETDM_IN5_CON2 0x13f8 |
| 27 | #define ETDM_IN5_CON3 0x13fc |
| 28 | #define ETDM_IN5_CON4 0x1400 |
| 29 | #define ETDM_OUT5_CON0 0x1570 |
| 30 | #define ETDM_OUT5_CON4 0x1580 |
| 31 | #define ETDM_OUT5_CON5 0x1584 |
| 32 | #define ETDM_4_7_COWORK_CON0 0x15e0 |
| 33 | #define ETDM_4_7_COWORK_CON1 0x15e4 |
| 34 | #define AFE_CONN018_1 0x1b44 |
| 35 | #define AFE_CONN018_4 0x1b50 |
| 36 | #define AFE_CONN019_1 0x1b64 |
| 37 | #define AFE_CONN019_4 0x1b70 |
| 38 | #define AFE_CONN124_1 0x2884 |
| 39 | #define AFE_CONN124_4 0x2890 |
| 40 | #define AFE_CONN125_1 0x28a4 |
| 41 | #define AFE_CONN125_4 0x28b0 |
| 42 | #define AFE_CONN_RS_0 0x3920 |
| 43 | #define AFE_CONN_RS_3 0x392c |
| 44 | #define AFE_CONN_16BIT_0 0x3960 |
| 45 | #define AFE_CONN_16BIT_3 0x396c |
| 46 | #define AFE_CONN_24BIT_0 0x3980 |
| 47 | #define AFE_CONN_24BIT_3 0x398c |
| 48 | #define AFE_MEMIF_CON0 0x3d98 |
| 49 | #define AFE_MEMIF_RD_MON 0x3da0 |
| 50 | #define AFE_MEMIF_WR_MON 0x3da4 |
| 51 | #define AFE_DL0_BASE_MSB 0x3e40 |
| 52 | #define AFE_DL0_BASE 0x3e44 |
| 53 | #define AFE_DL0_CUR_MSB 0x3e48 |
| 54 | #define AFE_DL0_CUR 0x3e4c |
| 55 | #define AFE_DL0_END_MSB 0x3e50 |
| 56 | #define AFE_DL0_END 0x3e54 |
| 57 | #define AFE_DL0_RCH_MON 0x3e58 |
| 58 | #define AFE_DL0_LCH_MON 0x3e5c |
| 59 | #define AFE_DL0_CON0 0x3e60 |
| 60 | #define AFE_VUL0_BASE_MSB 0x4220 |
| 61 | #define AFE_VUL0_BASE 0x4224 |
| 62 | #define AFE_VUL0_CUR_MSB 0x4228 |
| 63 | #define AFE_VUL0_CUR 0x422c |
| 64 | #define AFE_VUL0_END_MSB 0x4230 |
| 65 | #define AFE_VUL0_END 0x4234 |
| 66 | #define AFE_VUL0_CON0 0x4238 |
| 67 | |
| 68 | #define AFE_MAX_REGISTER AFE_VUL0_CON0 |
| developer | 0426ed2 | 2022-01-07 10:49:03 +0800 | [diff] [blame] | 69 | #define AFE_IRQ_STATUS_BITS 0x7 |
| developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 70 | #define AFE_IRQ_CNT_SHIFT 0 |
| 71 | #define AFE_IRQ_CNT_MASK 0xffffff |
| 72 | |
| 73 | /* AUDIO_TOP_CON2 */ |
| 74 | #define CLK_OUT5_PDN BIT(14) |
| 75 | #define CLK_OUT5_PDN_MASK BIT(14) |
| 76 | #define CLK_IN5_PDN BIT(7) |
| 77 | #define CLK_IN5_PDN_MASK BIT(7) |
| 78 | |
| 79 | /* AUDIO_TOP_CON4 */ |
| 80 | #define PDN_APLL_TUNER2 BIT(12) |
| 81 | #define PDN_APLL_TUNER2_MASK BIT(12) |
| 82 | |
| 83 | /* AUDIO_ENGEN_CON0 */ |
| 84 | #define AUD_APLL2_EN BIT(3) |
| 85 | #define AUD_APLL2_EN_MASK BIT(3) |
| 86 | #define AUD_26M_EN BIT(0) |
| 87 | #define AUD_26M_EN_MASK BIT(0) |
| 88 | |
| 89 | /* AFE_DL0_CON0 */ |
| 90 | #define DL0_ON_SFT 28 |
| 91 | #define DL0_ON_MASK 0x1 |
| 92 | #define DL0_ON_MASK_SFT BIT(28) |
| 93 | #define DL0_MINLEN_SFT 20 |
| 94 | #define DL0_MINLEN_MASK 0xf |
| 95 | #define DL0_MINLEN_MASK_SFT (0xf << 20) |
| 96 | #define DL0_MODE_SFT 8 |
| 97 | #define DL0_MODE_MASK 0x1f |
| 98 | #define DL0_MODE_MASK_SFT (0x1f << 8) |
| 99 | #define DL0_PBUF_SIZE_SFT 5 |
| 100 | #define DL0_PBUF_SIZE_MASK 0x3 |
| 101 | #define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5) |
| 102 | #define DL0_MONO_SFT 4 |
| 103 | #define DL0_MONO_MASK 0x1 |
| 104 | #define DL0_MONO_MASK_SFT BIT(4) |
| 105 | #define DL0_HALIGN_SFT 2 |
| 106 | #define DL0_HALIGN_MASK 0x1 |
| 107 | #define DL0_HALIGN_MASK_SFT BIT(2) |
| 108 | #define DL0_HD_MODE_SFT 0 |
| 109 | #define DL0_HD_MODE_MASK 0x3 |
| 110 | #define DL0_HD_MODE_MASK_SFT (0x3 << 0) |
| 111 | |
| 112 | /* AFE_VUL0_CON0 */ |
| 113 | #define VUL0_ON_SFT 28 |
| 114 | #define VUL0_ON_MASK 0x1 |
| 115 | #define VUL0_ON_MASK_SFT BIT(28) |
| 116 | #define VUL0_MODE_SFT 8 |
| 117 | #define VUL0_MODE_MASK 0x1f |
| 118 | #define VUL0_MODE_MASK_SFT (0x1f << 8) |
| 119 | #define VUL0_MONO_SFT 4 |
| 120 | #define VUL0_MONO_MASK 0x1 |
| 121 | #define VUL0_MONO_MASK_SFT BIT(4) |
| 122 | #define VUL0_HALIGN_SFT 2 |
| 123 | #define VUL0_HALIGN_MASK 0x1 |
| 124 | #define VUL0_HALIGN_MASK_SFT BIT(2) |
| 125 | #define VUL0_HD_MODE_SFT 0 |
| 126 | #define VUL0_HD_MODE_MASK 0x3 |
| 127 | #define VUL0_HD_MODE_MASK_SFT (0x3 << 0) |
| 128 | |
| 129 | /* AFE_IRQ_MCU_CON */ |
| 130 | #define IRQ_MCU_MODE_SFT 4 |
| 131 | #define IRQ_MCU_MODE_MASK 0x1f |
| 132 | #define IRQ_MCU_MODE_MASK_SFT (0x1f << 4) |
| 133 | #define IRQ_MCU_ON_SFT 0 |
| 134 | #define IRQ_MCU_ON_MASK 0x1 |
| 135 | #define IRQ_MCU_ON_MASK_SFT BIT(0) |
| developer | 0426ed2 | 2022-01-07 10:49:03 +0800 | [diff] [blame] | 136 | #define IRQ0_MCU_CLR_SFT 0 |
| 137 | #define IRQ0_MCU_CLR_MASK 0x1 |
| 138 | #define IRQ0_MCU_CLR_MASK_SFT BIT(0) |
| 139 | #define IRQ1_MCU_CLR_SFT 1 |
| 140 | #define IRQ1_MCU_CLR_MASK 0x1 |
| 141 | #define IRQ1_MCU_CLR_MASK_SFT BIT(1) |
| 142 | #define IRQ2_MCU_CLR_SFT 2 |
| 143 | #define IRQ2_MCU_CLR_MASK 0x1 |
| 144 | #define IRQ2_MCU_CLR_MASK_SFT BIT(2) |
| developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 145 | |
| 146 | /* ETDM_IN5_CON2 */ |
| 147 | #define IN_CLK_SRC(x) ((x) << 10) |
| 148 | #define IN_CLK_SRC_SFT 10 |
| 149 | #define IN_CLK_SRC_MASK GENMASK(12, 10) |
| 150 | |
| 151 | /* ETDM_IN5_CON3 */ |
| 152 | #define IN_SEL_FS(x) ((x) << 26) |
| 153 | #define IN_SEL_FS_SFT 26 |
| 154 | #define IN_SEL_FS_MASK GENMASK(30, 26) |
| 155 | |
| 156 | /* ETDM_IN5_CON4 */ |
| 157 | #define IN_RELATCH(x) ((x) << 20) |
| 158 | #define IN_RELATCH_SFT 20 |
| 159 | #define IN_RELATCH_MASK GENMASK(24, 20) |
| 160 | #define IN_CLK_INV BIT(18) |
| 161 | #define IN_CLK_INV_MASK BIT(18) |
| 162 | |
| 163 | /* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */ |
| 164 | #define RELATCH_SRC(x) ((x) << 28) |
| 165 | #define RELATCH_SRC_SFT 28 |
| 166 | #define RELATCH_SRC_MASK GENMASK(30, 28) |
| 167 | #define ETDM_CH_NUM(x) (((x) - 1) << 23) |
| 168 | #define ETDM_CH_NUM_SFT 23 |
| 169 | #define ETDM_CH_NUM_MASK GENMASK(27, 23) |
| 170 | #define ETDM_WRD_LEN(x) (((x) - 1) << 16) |
| 171 | #define ETDM_WRD_LEN_SFT 16 |
| 172 | #define ETDM_WRD_LEN_MASK GENMASK(20, 16) |
| 173 | #define ETDM_BIT_LEN(x) (((x) - 1) << 11) |
| 174 | #define ETDM_BIT_LEN_SFT 11 |
| 175 | #define ETDM_BIT_LEN_MASK GENMASK(15, 11) |
| 176 | #define ETDM_FMT(x) ((x) << 6) |
| 177 | #define ETDM_FMT_SFT 6 |
| 178 | #define ETDM_FMT_MASK GENMASK(8, 6) |
| 179 | #define ETDM_SYNC BIT(1) |
| 180 | #define ETDM_SYNC_MASK BIT(1) |
| 181 | #define ETDM_EN BIT(0) |
| 182 | #define ETDM_EN_MASK BIT(0) |
| 183 | |
| 184 | /* ETDM_OUT5_CON4 */ |
| 185 | #define OUT_RELATCH(x) ((x) << 24) |
| 186 | #define OUT_RELATCH_SFT 24 |
| 187 | #define OUT_RELATCH_MASK GENMASK(28, 24) |
| 188 | #define OUT_CLK_SRC(x) ((x) << 6) |
| 189 | #define OUT_CLK_SRC_SFT 6 |
| 190 | #define OUT_CLK_SRC_MASK GENMASK(8, 6) |
| 191 | #define OUT_SEL_FS(x) ((x) << 0) |
| 192 | #define OUT_SEL_FS_SFT 0 |
| 193 | #define OUT_SEL_FS_MASK GENMASK(4, 0) |
| 194 | |
| 195 | /* ETDM_OUT5_CON5 */ |
| 196 | #define ETDM_CLK_DIV BIT(12) |
| 197 | #define ETDM_CLK_DIV_MASK BIT(12) |
| 198 | #define OUT_CLK_INV BIT(9) |
| 199 | #define OUT_CLK_INV_MASK BIT(9) |
| 200 | |
| 201 | /* ETDM_4_7_COWORK_CON0 */ |
| 202 | #define OUT_SEL(x) ((x) << 12) |
| 203 | #define OUT_SEL_SFT 12 |
| 204 | #define OUT_SEL_MASK GENMASK(15, 12) |
| 205 | #endif |