[][Add mt79xx audio irq support from IRQ0-1 to IRQ0-2]

[Description]
Add mt79xx audio irq support from IRQ0-1 to IRQ0-2 and correct IRQ status.
Without this patch, it cannot support aplay and arecord simultaneously.

[Release-log]
N/A

Change-Id: I32837087e755d126e35836807730998025bfd296
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5483284
diff --git a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h
index d55bd28..b8d2d56 100644
--- a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h
+++ b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h
@@ -19,6 +19,8 @@
 #define AFE_IRQ0_MCU_CFG1               0x0144
 #define AFE_IRQ1_MCU_CFG0               0x0148
 #define AFE_IRQ1_MCU_CFG1               0x014c
+#define AFE_IRQ2_MCU_CFG0               0x0150
+#define AFE_IRQ2_MCU_CFG1               0x0154
 #define ETDM_IN5_CON0                   0x13f0
 #define ETDM_IN5_CON1                   0x13f4
 #define ETDM_IN5_CON2                   0x13f8
@@ -64,7 +66,7 @@
 #define AFE_VUL0_CON0                   0x4238
 
 #define AFE_MAX_REGISTER AFE_VUL0_CON0
-#define AFE_IRQ_STATUS_BITS             0x1
+#define AFE_IRQ_STATUS_BITS             0x7
 #define AFE_IRQ_CNT_SHIFT               0
 #define AFE_IRQ_CNT_MASK	        0xffffff
 
@@ -131,9 +133,15 @@
 #define IRQ_MCU_ON_SFT                  0
 #define IRQ_MCU_ON_MASK                 0x1
 #define IRQ_MCU_ON_MASK_SFT             BIT(0)
-#define IRQ_MCU_CLR_SFT                 0
-#define IRQ_MCU_CLR_MASK                0x1
-#define IRQ_MCU_CLR_MASK_SFT            BIT(0)
+#define IRQ0_MCU_CLR_SFT                0
+#define IRQ0_MCU_CLR_MASK               0x1
+#define IRQ0_MCU_CLR_MASK_SFT           BIT(0)
+#define IRQ1_MCU_CLR_SFT                1
+#define IRQ1_MCU_CLR_MASK               0x1
+#define IRQ1_MCU_CLR_MASK_SFT           BIT(1)
+#define IRQ2_MCU_CLR_SFT                2
+#define IRQ2_MCU_CLR_MASK               0x1
+#define IRQ2_MCU_CLR_MASK_SFT           BIT(2)
 
 /* ETDM_IN5_CON2 */
 #define IN_CLK_SRC(x)                   ((x) << 10)