developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7981.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7981 RFB"; |
| 5 | compatible = "mediatek,mt7981-spim-nor-rfb"; |
| 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000"; |
| 9 | }; |
| 10 | |
| 11 | memory { |
| 12 | // fpga ddr2: 128MB*2 |
| 13 | reg = <0 0x40000000 0 0x10000000>; |
| 14 | }; |
| 15 | }; |
| 16 | |
| 17 | &uart0 { |
| 18 | status = "okay"; |
| 19 | }; |
| 20 | |
| 21 | &watchdog { |
| 22 | status = "okay"; |
| 23 | }; |
| 24 | |
| 25 | ð { |
| 26 | status = "okay"; |
| 27 | |
| 28 | gmac0: mac@0 { |
| 29 | compatible = "mediatek,eth-mac"; |
| 30 | reg = <0>; |
| 31 | phy-mode = "2500base-x"; |
| 32 | |
| 33 | fixed-link { |
| 34 | speed = <2500>; |
| 35 | full-duplex; |
| 36 | pause; |
| 37 | }; |
| 38 | }; |
| 39 | |
| 40 | gmac1: mac@1 { |
| 41 | compatible = "mediatek,eth-mac"; |
| 42 | reg = <1>; |
| 43 | phy-mode = "gmii"; |
| 44 | phy-handle = <&phy0>; |
| 45 | }; |
| 46 | |
| 47 | mdio: mdio-bus { |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <0>; |
| 50 | |
| 51 | phy0: ethernet-phy@0 { |
developer | a7de8be | 2021-11-15 21:14:31 +0800 | [diff] [blame] | 52 | compatible = "ethernet-phy-id03a2.9461"; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 53 | reg = <0>; |
developer | a7de8be | 2021-11-15 21:14:31 +0800 | [diff] [blame] | 54 | phy-mode = "gmii"; |
developer | a7de8be | 2021-11-15 21:14:31 +0800 | [diff] [blame] | 55 | nvmem-cells = <&phy_calibration>; |
| 56 | nvmem-cell-names = "phy-cal-data"; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | switch@0 { |
| 60 | compatible = "mediatek,mt7531"; |
| 61 | reg = <31>; |
| 62 | reset-gpios = <&pio 39 0>; |
| 63 | |
| 64 | ports { |
| 65 | #address-cells = <1>; |
| 66 | #size-cells = <0>; |
| 67 | |
| 68 | port@0 { |
| 69 | reg = <0>; |
| 70 | label = "lan1"; |
| 71 | }; |
| 72 | |
| 73 | port@1 { |
| 74 | reg = <1>; |
| 75 | label = "lan2"; |
| 76 | }; |
| 77 | |
| 78 | port@2 { |
| 79 | reg = <2>; |
| 80 | label = "lan3"; |
| 81 | }; |
| 82 | |
| 83 | port@3 { |
| 84 | reg = <3>; |
| 85 | label = "lan4"; |
| 86 | }; |
| 87 | |
| 88 | port@6 { |
| 89 | reg = <6>; |
| 90 | label = "cpu"; |
| 91 | ethernet = <&gmac0>; |
| 92 | phy-mode = "2500base-x"; |
| 93 | |
| 94 | fixed-link { |
| 95 | speed = <2500>; |
| 96 | full-duplex; |
| 97 | pause; |
| 98 | }; |
| 99 | }; |
| 100 | }; |
| 101 | }; |
| 102 | }; |
| 103 | }; |
| 104 | |
| 105 | &hnat { |
| 106 | mtketh-wan = "eth1"; |
| 107 | mtketh-lan = "lan"; |
| 108 | mtketh-max-gmac = <2>; |
| 109 | status = "okay"; |
| 110 | }; |
| 111 | |
| 112 | &spi1 { |
| 113 | pinctrl-names = "default"; |
| 114 | pinctrl-0 = <&spic_pins>; |
| 115 | status = "disabled"; |
| 116 | }; |
| 117 | |
| 118 | &spi2 { |
| 119 | pinctrl-names = "default"; |
| 120 | pinctrl-0 = <&spi2_flash_pins>; |
| 121 | status = "okay"; |
| 122 | spi_nor@0 { |
| 123 | #address-cells = <1>; |
| 124 | #size-cells = <1>; |
| 125 | compatible = "jedec,spi-nor"; |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame^] | 126 | spi-cal-enable; |
| 127 | spi-cal-mode = "read-data"; |
| 128 | spi-cal-datalen = <7>; |
| 129 | spi-cal-data = /bits/ 8 < |
| 130 | 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ |
| 131 | spi-cal-addrlen = <1>; |
| 132 | spi-cal-addr = /bits/ 32 <0x0>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 133 | reg = <0>; |
| 134 | spi-max-frequency = <52000000>; |
| 135 | spi-tx-buswidth = <4>; |
| 136 | spi-rx-buswidth = <4>; |
| 137 | |
| 138 | partition@00000 { |
| 139 | label = "BL2"; |
| 140 | reg = <0x00000 0x0040000>; |
| 141 | }; |
| 142 | partition@40000 { |
| 143 | label = "u-boot-env"; |
| 144 | reg = <0x40000 0x0010000>; |
| 145 | }; |
| 146 | partition@50000 { |
| 147 | label = "Factory"; |
| 148 | reg = <0x50000 0x00B0000>; |
| 149 | }; |
| 150 | partition@100000 { |
| 151 | label = "FIP"; |
| 152 | reg = <0x100000 0x0080000>; |
| 153 | }; |
| 154 | partition@180000 { |
| 155 | label = "firmware"; |
| 156 | reg = <0x180000 0xE00000>; |
| 157 | }; |
| 158 | }; |
| 159 | }; |
| 160 | |
| 161 | &pio { |
| 162 | spic_pins: spi1-pins { |
| 163 | mux { |
| 164 | function = "spi"; |
| 165 | groups = "spi1_1"; |
| 166 | }; |
| 167 | }; |
| 168 | |
| 169 | spi2_flash_pins: spi2-pins { |
| 170 | mux { |
| 171 | function = "spi"; |
| 172 | groups = "spi2", "spi2_wp_hold"; |
| 173 | }; |
developer | 66b31fc | 2021-12-27 17:12:45 +0800 | [diff] [blame] | 174 | |
| 175 | conf-pu { |
| 176 | pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; |
| 177 | drive-strength = <MTK_DRIVE_8mA>; |
developer | b5a819c | 2022-05-16 19:16:07 +0800 | [diff] [blame] | 178 | bias-pull-up = <MTK_PUPD_SET_R1R0_11>; |
developer | 66b31fc | 2021-12-27 17:12:45 +0800 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | conf-pd { |
| 182 | pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; |
| 183 | drive-strength = <MTK_DRIVE_8mA>; |
developer | b5a819c | 2022-05-16 19:16:07 +0800 | [diff] [blame] | 184 | bias-pull-down = <MTK_PUPD_SET_R1R0_11>; |
developer | 66b31fc | 2021-12-27 17:12:45 +0800 | [diff] [blame] | 185 | }; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 186 | }; |
| 187 | }; |
| 188 | |
| 189 | &xhci { |
| 190 | status = "okay"; |
| 191 | }; |
| 192 | |
| 193 | &wed { |
| 194 | dy_txbm_enable = "true"; |
developer | 4d45508 | 2021-11-22 16:00:28 +0800 | [diff] [blame] | 195 | dy_txbm_budget = <8>; |
| 196 | txbm_init_sz = <8>; |
| 197 | txbm_max_sz = <32>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 198 | status = "okay"; |
| 199 | }; |