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developer58aa0682023-09-18 14:02:26 +08001From be48305fd2e3ecd9a9853f2ae11fb9432e40b299 Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Bo Jiao <Bo.Jiao@mediatek.com>
developer58aa0682023-09-18 14:02:26 +08003Date: Mon, 18 Sep 2023 10:55:08 +0800
4Subject: [PATCH 03/22] dts mt7986 wed changes
developer8cb3ac72022-07-04 10:55:14 +08005
6---
7 arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 33 ++++++++---------------
8 arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 33 ++++++++---------------
9 2 files changed, 22 insertions(+), 44 deletions(-)
10
11diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
developer58aa0682023-09-18 14:02:26 +080012index e43c306..e5d4e12 100644
developer8cb3ac72022-07-04 10:55:14 +080013--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
14+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
15@@ -58,32 +58,20 @@
16 };
17 };
18
19- wed: wed@15010000 {
20- compatible = "mediatek,wed";
21- wed_num = <2>;
22- /* add this property for wed get the pci slot number. */
23- pci_slot_map = <0>, <1>;
24- reg = <0 0x15010000 0 0x1000>,
25- <0 0x15011000 0 0x1000>;
26+ wed0: wed@15010000 {
27+ compatible = "mediatek,mt7986-wed",
28+ "syscon";
29+ reg = <0 0x15010000 0 0x1000>;
30 interrupt-parent = <&gic>;
31- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
32- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
33+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
34 };
35
36- wed2: wed2@15011000 {
37- compatible = "mediatek,wed2";
38- wed_num = <2>;
39- reg = <0 0x15010000 0 0x1000>,
40- <0 0x15011000 0 0x1000>;
41+ wed1: wed@15011000 {
42+ compatible = "mediatek,mt7986-wed",
43+ "syscon";
44+ reg = <0 0x15011000 0 0x1000>;
45 interrupt-parent = <&gic>;
46- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
47- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
48- };
49-
50- wdma: wdma@15104800 {
51- compatible = "mediatek,wed-wdma";
52- reg = <0 0x15104800 0 0x400>,
53- <0 0x15104c00 0 0x400>;
54+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
55 };
56
57 ap2woccif: ap2woccif@151A5000 {
developer58aa0682023-09-18 14:02:26 +080058@@ -507,6 +495,7 @@
developer8cb3ac72022-07-04 10:55:14 +080059 <&topckgen CK_TOP_CB_SGM_325M>;
60 mediatek,ethsys = <&ethsys>;
61 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
62+ mediatek,wed = <&wed0>, <&wed1>;
63 #reset-cells = <1>;
64 #address-cells = <1>;
65 #size-cells = <0>;
66diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
developer58aa0682023-09-18 14:02:26 +080067index 21d8357..2d2207f 100644
developer8cb3ac72022-07-04 10:55:14 +080068--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
69+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
70@@ -58,32 +58,20 @@
71 };
72 };
73
74- wed: wed@15010000 {
75- compatible = "mediatek,wed";
76- wed_num = <2>;
77- /* add this property for wed get the pci slot number. */
78- pci_slot_map = <0>, <1>;
79- reg = <0 0x15010000 0 0x1000>,
80- <0 0x15011000 0 0x1000>;
81+ wed0: wed@15010000 {
82+ compatible = "mediatek,mt7986-wed",
83+ "syscon";
84+ reg = <0 0x15010000 0 0x1000>;
85 interrupt-parent = <&gic>;
86- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
87- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
88+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
91- wed2: wed2@15011000 {
92- compatible = "mediatek,wed2";
93- wed_num = <2>;
94- reg = <0 0x15010000 0 0x1000>,
95- <0 0x15011000 0 0x1000>;
96+ wed1: wed@15011000 {
97+ compatible = "mediatek,mt7986-wed",
98+ "syscon";
99+ reg = <0 0x15011000 0 0x1000>;
100 interrupt-parent = <&gic>;
101- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
102- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
103- };
104-
105- wdma: wdma@15104800 {
106- compatible = "mediatek,wed-wdma";
107- reg = <0 0x15104800 0 0x400>,
108- <0 0x15104c00 0 0x400>;
109+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
110 };
111
112 ap2woccif: ap2woccif@151A5000 {
developer58aa0682023-09-18 14:02:26 +0800113@@ -409,6 +397,7 @@
developer8cb3ac72022-07-04 10:55:14 +0800114 <&topckgen CK_TOP_CB_SGM_325M>;
115 mediatek,ethsys = <&ethsys>;
116 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
117+ mediatek,wed = <&wed0>, <&wed1>;
118 #reset-cells = <1>;
119 #address-cells = <1>;
120 #size-cells = <0>;
developer428eaaa2023-10-06 15:48:21 +0800121diff --git a/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/arch/arm64/boot/dts/mediatek/mt7981.dtsi
122index ccaf0ad0..b2f53b13 100644
123--- a/arch/arm64/boot/dts/mediatek/mt7981.dtsi
124+++ b/arch/arm64/boot/dts/mediatek/mt7981.dtsi
125@@ -90,22 +90,12 @@
126 #io-channel-cells = <1>;
127 };
128
129- wed: wed@15010000 {
130- compatible = "mediatek,wed";
131- wed_num = <2>;
132- /* add this property for wed get the pci slot number. */
133- pci_slot_map = <0>, <1>;
134- reg = <0 0x15010000 0 0x1000>,
135- <0 0x15011000 0 0x1000>;
136+ wed0: wed@15010000 {
137+ compatible = "mediatek,mt7981-wed",
138+ "syscon";
139+ reg = <0 0x15010000 0 0x1000>;
140 interrupt-parent = <&gic>;
141- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
142- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
143- };
144-
145- wdma: wdma@15104800 {
146- compatible = "mediatek,wed-wdma";
147- reg = <0 0x15104800 0 0x400>,
148- <0 0x15104c00 0 0x400>;
149+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 ap2woccif: ap2woccif@151A5000 {
153@@ -423,6 +413,7 @@
154 mediatek,ethsys = <&ethsys>;
155 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
156 mediatek,infracfg = <&topmisc>;
157+ mediatek,wed = <&wed0>;
158 #reset-cells = <1>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161diff --git a/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts
162index 3fa55a07..f5c70a4e 100755
163--- a/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts
164+++ b/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts
165@@ -211,11 +211,3 @@
166 &xhci {
167 status = "okay";
168 };
169-
170-&wed {
171- dy_txbm_enable = "true";
172- dy_txbm_budget = <8>;
173- txbm_init_sz = <8>;
174- txbm_max_sz = <32>;
175- status = "okay";
176-};
developer8cb3ac72022-07-04 10:55:14 +0800177--
1782.18.0
179