blob: eedc6de137a3d77363e07fb8c27557c346c5ef47 [file] [log] [blame]
developerd0527512023-11-07 09:54:54 +08001From abf253c784db9cb42cf14ca7b825227ef982c3cd Mon Sep 17 00:00:00 2001
developer1346ce52022-12-15 21:36:14 +08002From: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
3Date: Thu, 15 Dec 2022 19:45:18 +0800
developerb3cb52e2023-10-27 15:16:48 +08004Subject: [PATCH] wifi: mt76: testmode: add iBF/eBF cal and cert commands with
5 golden
developer1346ce52022-12-15 21:36:14 +08006
7Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
8---
9 mt76.h | 4 +
10 mt76_connac_mcu.c | 3 +
11 mt7915/mac.c | 4 +-
12 mt7915/main.c | 54 ++---
13 mt7915/mcu.c | 29 ++-
14 mt7915/mcu.h | 172 ++++++++++++++++
15 mt7915/mmio.c | 2 +
16 mt7915/mt7915.h | 14 +-
17 mt7915/mtk_debugfs.c | 35 ++++
developerd0527512023-11-07 09:54:54 +080018 mt7915/mtk_mcu.c | 247 ++++++++++++++++++++++-
developer1346ce52022-12-15 21:36:14 +080019 mt7915/regs.h | 4 +
developere8045132023-08-04 14:40:12 +080020 mt7915/testmode.c | 461 ++++++++++++++++++++++++++++---------------
developer1346ce52022-12-15 21:36:14 +080021 mt7915/testmode.h | 134 +------------
22 testmode.c | 1 +
23 testmode.h | 9 +
24 tools/fields.c | 9 +
developerd0527512023-11-07 09:54:54 +080025 16 files changed, 858 insertions(+), 324 deletions(-)
developer1346ce52022-12-15 21:36:14 +080026
27diff --git a/mt76.h b/mt76.h
developerb3cb52e2023-10-27 15:16:48 +080028index 7ae061d..d16accd 100644
developer1346ce52022-12-15 21:36:14 +080029--- a/mt76.h
30+++ b/mt76.h
developerb3cb52e2023-10-27 15:16:48 +080031@@ -718,6 +718,7 @@ struct mt76_testmode_data {
developer1346ce52022-12-15 21:36:14 +080032
33 struct list_head tm_entry_list;
34 struct mt76_wcid *cur_entry;
35+ struct ieee80211_vif *second_vif;
36 u8 entry_num;
37 union {
38 struct mt76_testmode_entry_data ed;
developerb3cb52e2023-10-27 15:16:48 +080039@@ -746,6 +747,9 @@ struct mt76_testmode_data {
developer1346ce52022-12-15 21:36:14 +080040
41 u8 txbf_act;
42 u16 txbf_param[8];
43+ bool is_txbf_dut;
44+ bool bf_en;
45+ bool ebf;
46
47 u32 tx_pending;
48 u32 tx_queued;
49diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developer0443cd32023-09-19 14:11:49 +080050index 60e159c..07bd57b 100644
developer1346ce52022-12-15 21:36:14 +080051--- a/mt76_connac_mcu.c
52+++ b/mt76_connac_mcu.c
developer0443cd32023-09-19 14:11:49 +080053@@ -2796,6 +2796,7 @@ int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
developer1346ce52022-12-15 21:36:14 +080054 u32 type = vif->p2p ? NETWORK_P2P : NETWORK_INFRA;
55 struct bss_info_basic *bss;
56 struct tlv *tlv;
57+ struct mt76_testmode_data *td = &phy->test;
58
59 tlv = mt76_connac_mcu_add_tlv(skb, BSS_INFO_BASIC, sizeof(*bss));
60 bss = (struct bss_info_basic *)tlv;
developer0443cd32023-09-19 14:11:49 +080061@@ -2855,6 +2856,8 @@ int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
developer1346ce52022-12-15 21:36:14 +080062 bss->dtim_period = vif->bss_conf.dtim_period;
63 bss->phy_mode = mt76_connac_get_phy_mode(phy, vif,
64 chandef->chan->band, NULL);
65+ } else if (td->bf_en) {
66+ memcpy(bss->bssid, vif->addr, ETH_ALEN);
67 } else {
68 memcpy(bss->bssid, phy->macaddr, ETH_ALEN);
69 }
70diff --git a/mt7915/mac.c b/mt7915/mac.c
developerb3cb52e2023-10-27 15:16:48 +080071index 06a5fb1..948f07b 100644
developer1346ce52022-12-15 21:36:14 +080072--- a/mt7915/mac.c
73+++ b/mt7915/mac.c
developerb3cb52e2023-10-27 15:16:48 +080074@@ -730,8 +730,10 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer1346ce52022-12-15 21:36:14 +080075 val |= MT_TXD6_LDPC;
76
77 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
78- if (phy->test.bf_en)
79+ if (td->bf_en && !td->ebf)
80 val |= MT_TXD6_TX_IBF | MT_TXD6_TX_EBF;
81+ else if (td->bf_en && td->ebf)
82+ val |= MT_TXD6_TX_EBF;
83
84 txwi[6] |= cpu_to_le32(val);
85 #endif
86diff --git a/mt7915/main.c b/mt7915/main.c
developerd0527512023-11-07 09:54:54 +080087index 44a1b21..8c9b0b2 100644
developer1346ce52022-12-15 21:36:14 +080088--- a/mt7915/main.c
89+++ b/mt7915/main.c
90@@ -205,46 +205,37 @@ static void mt7915_init_bitrate_mask(struct ieee80211_vif *vif)
91 }
92 }
93
94-static int mt7915_add_interface(struct ieee80211_hw *hw,
95- struct ieee80211_vif *vif)
96+int mt7915_init_vif(struct mt7915_phy *phy, struct ieee80211_vif *vif, bool bf_en)
97 {
98 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
99- struct mt7915_dev *dev = mt7915_hw_dev(hw);
100- struct mt7915_phy *phy = mt7915_hw_phy(hw);
101+ struct mt7915_dev *dev = phy->dev;
102 struct mt76_txq *mtxq;
103 bool ext_phy = phy != &dev->phy;
104 int idx, ret = 0;
105
106- mutex_lock(&dev->mt76.mutex);
107-
108- mt76_testmode_reset(phy->mt76, true);
109-
110- if (vif->type == NL80211_IFTYPE_MONITOR &&
111- is_zero_ether_addr(vif->addr))
112- phy->monitor_vif = vif;
113+ /* To differentiate the mac address of TXD and TXCMD interface */
114+ vif->addr[0] |= bf_en;
115
116 mvif->mt76.idx = __ffs64(~dev->mt76.vif_mask);
117- if (mvif->mt76.idx >= (MT7915_MAX_INTERFACES << dev->dbdc_support)) {
118- ret = -ENOSPC;
119- goto out;
120- }
121+ if (mvif->mt76.idx >= (MT7915_MAX_INTERFACES << dev->dbdc_support))
122+ return -ENOSPC;
123
124 idx = get_omac_idx(vif->type, phy->omac_mask);
125- if (idx < 0) {
126- ret = -ENOSPC;
127- goto out;
128- }
129+ if (idx < 0)
130+ return -ENOSPC;
131+
132 mvif->mt76.omac_idx = idx;
133 mvif->phy = phy;
134 mvif->mt76.band_idx = phy->mt76->band_idx;
135
136- mvif->mt76.wmm_idx = (vif->type != NL80211_IFTYPE_AP && vif->type != NL80211_IFTYPE_MONITOR);
137+ mvif->mt76.wmm_idx = (vif->type != NL80211_IFTYPE_AP &&
138+ vif->type != NL80211_IFTYPE_MONITOR) || bf_en;
139 if (ext_phy)
140 mvif->mt76.wmm_idx += 2;
141
142 ret = mt7915_mcu_add_dev_info(phy, vif, true);
143 if (ret)
144- goto out;
145+ return ret;
146
147 dev->mt76.vif_mask |= BIT_ULL(mvif->mt76.idx);
148 phy->omac_mask |= BIT_ULL(mvif->mt76.omac_idx);
developerb3cb52e2023-10-27 15:16:48 +0800149@@ -280,7 +271,26 @@ static int mt7915_add_interface(struct ieee80211_hw *hw,
developer1346ce52022-12-15 21:36:14 +0800150 mt7915_mcu_add_sta(dev, vif, NULL, true);
151 rcu_assign_pointer(dev->mt76.wcid[idx], &mvif->sta.wcid);
152
153-out:
154+ return ret;
155+}
156+
157+static int mt7915_add_interface(struct ieee80211_hw *hw,
158+ struct ieee80211_vif *vif)
159+{
160+ struct mt7915_dev *dev = mt7915_hw_dev(hw);
161+ struct mt7915_phy *phy = mt7915_hw_phy(hw);
162+ int ret = 0;
163+
164+ mutex_lock(&dev->mt76.mutex);
165+
166+ mt76_testmode_reset(phy->mt76, true);
167+
168+ if (vif->type == NL80211_IFTYPE_MONITOR &&
169+ is_zero_ether_addr(vif->addr))
170+ phy->monitor_vif = vif;
171+
172+ ret = mt7915_init_vif(phy, vif, false);
173+
174 mutex_unlock(&dev->mt76.mutex);
175
176 return ret;
177diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer0443cd32023-09-19 14:11:49 +0800178index 2cd772b..83d974c 100644
developer1346ce52022-12-15 21:36:14 +0800179--- a/mt7915/mcu.c
180+++ b/mt7915/mcu.c
developer2157bf82023-06-26 02:27:49 +0800181@@ -199,6 +199,7 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developer1346ce52022-12-15 21:36:14 +0800182 int ret;
183
184 ret = mt76_connac2_mcu_fill_message(mdev, skb, cmd, wait_seq);
185+
186 if (ret)
187 return ret;
188
developer0443cd32023-09-19 14:11:49 +0800189@@ -391,10 +392,12 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
developer1346ce52022-12-15 21:36:14 +0800190 case MCU_EXT_EVENT_BCC_NOTIFY:
191 mt7915_mcu_rx_bcc_notify(dev, skb);
192 break;
193-#ifdef CONFIG_NL80211_TESTMODE
194+#if defined CONFIG_NL80211_TESTMODE || defined MTK_DEBUG
195 case MCU_EXT_EVENT_BF_STATUS_READ:
196- mt7915_tm_txbf_status_read(dev, skb);
197+ mt7915_mcu_txbf_status_read(dev, skb);
198 break;
199+#endif
200+#ifdef CONFIG_NL80211_TESTMODE
201 case MCU_EXT_EVENT_RF_TEST:
202 mt7915_tm_rf_test_event(dev, skb);
203 break;
developer0443cd32023-09-19 14:11:49 +0800204@@ -683,11 +686,22 @@ int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,
developer1346ce52022-12-15 21:36:14 +0800205 if (enable)
206 mt76_connac_mcu_bss_omac_tlv(skb, vif);
207
208- mt76_connac_mcu_bss_basic_tlv(skb, vif, NULL, phy->mt76,
209- mvif->sta.wcid.idx, enable);
210+ if (vif->type == NL80211_IFTYPE_MONITOR) {
211+ struct mt76_testmode_data *td = &phy->mt76->test;
212+ struct mt76_wcid *wcid;
213+
214+ if (!td->aid || list_empty(&td->tm_entry_list))
215+ wcid = &mvif->sta.wcid;
216+ else
217+ wcid = list_first_entry(&td->tm_entry_list, struct mt76_wcid, list);
218
219- if (vif->type == NL80211_IFTYPE_MONITOR)
220+ mt76_connac_mcu_bss_basic_tlv(skb, vif, NULL, phy->mt76,
221+ wcid->idx, enable);
222 goto out;
223+ }
224+
225+ mt76_connac_mcu_bss_basic_tlv(skb, vif, NULL, phy->mt76,
226+ mvif->sta.wcid.idx, enable);
227
228 if (enable) {
229 mt7915_mcu_bss_rfch_tlv(skb, vif, phy);
developer0443cd32023-09-19 14:11:49 +0800230@@ -3440,6 +3454,7 @@ int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band)
developer1346ce52022-12-15 21:36:14 +0800231
232 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action)
233 {
234+#define MT_BF_PROCESSING 4
235 struct {
236 u8 action;
237 union {
developer0443cd32023-09-19 14:11:49 +0800238@@ -3466,7 +3481,6 @@ int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action)
developer1346ce52022-12-15 21:36:14 +0800239 .action = action,
240 };
241
242-#define MT_BF_PROCESSING 4
243 switch (action) {
244 case MT_BF_SOUNDING_ON:
245 req.snd.snd_mode = MT_BF_PROCESSING;
developer0443cd32023-09-19 14:11:49 +0800246@@ -4601,6 +4615,9 @@ int mt7915_mcu_set_txbf_sound_info(struct mt7915_phy *phy, u8 action,
developer1346ce52022-12-15 21:36:14 +0800247 req.he_opt = v2;
248 req.glo_opt = v3;
249 break;
250+ case BF_SND_CFG_INF:
251+ req.inf = v1;
252+ break;
253 default:
254 return -EINVAL;
255 }
256diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developere8045132023-08-04 14:40:12 +0800257index f4c3bf4..c95d990 100644
developer1346ce52022-12-15 21:36:14 +0800258--- a/mt7915/mcu.h
259+++ b/mt7915/mcu.h
developerbbd45e12023-05-19 08:22:06 +0800260@@ -531,10 +531,12 @@ enum {
developer1346ce52022-12-15 21:36:14 +0800261 };
262
263 enum {
264+ MT_BF_SOUNDING_OFF = 0,
265 MT_BF_SOUNDING_ON = 1,
266 MT_BF_DATA_PACKET_APPLY = 2,
267 MT_BF_PFMU_TAG_READ = 5,
268 MT_BF_PFMU_TAG_WRITE = 6,
269+ MT_BF_STA_REC_READ = 13,
270 MT_BF_PHASE_CAL = 14,
271 MT_BF_IBF_PHASE_COMP = 15,
272 MT_BF_PROFILE_WRITE_ALL = 17,
developerbbd45e12023-05-19 08:22:06 +0800273@@ -542,6 +544,176 @@ enum {
developer1346ce52022-12-15 21:36:14 +0800274 MT_BF_MODULE_UPDATE = 25
275 };
276
277+#if defined CONFIG_NL80211_TESTMODE || defined MTK_DEBUG
278+struct mt7915_pfmu_tag1 {
279+ __le32 pfmu_idx:10;
280+ __le32 ebf:1;
281+ __le32 data_bw:2;
282+ __le32 lm:2;
283+ __le32 is_mu:1;
284+ __le32 nr:3, nc:3;
285+ __le32 codebook:2;
286+ __le32 ngroup:2;
287+ __le32 _rsv:2;
288+ __le32 invalid_prof:1;
289+ __le32 rmsd:3;
290+
291+ __le32 col_id1:6, row_id1:10;
292+ __le32 col_id2:6, row_id2:10;
293+ __le32 col_id3:6, row_id3:10;
294+ __le32 col_id4:6, row_id4:10;
295+
296+ __le32 ru_start_id:7;
297+ __le32 _rsv1:1;
298+ __le32 ru_end_id:7;
299+ __le32 _rsv2:1;
300+ __le32 mob_cal_en:1;
301+ __le32 _rsv3:15;
302+
303+ __le32 snr_sts0:8, snr_sts1:8, snr_sts2:8, snr_sts3:8;
304+ __le32 snr_sts4:8, snr_sts5:8, snr_sts6:8, snr_sts7:8;
305+
306+ __le32 _rsv4;
307+} __packed;
308+
309+struct mt7915_pfmu_tag2 {
310+ __le32 smart_ant:24;
311+ __le32 se_idx:5;
312+ __le32 _rsv:3;
313+
314+ __le32 _rsv1:8;
315+ __le32 rmsd_thres:3;
316+ __le32 _rsv2:5;
317+ __le32 ibf_timeout:8;
318+ __le32 _rsv3:8;
319+
320+ __le32 _rsv4:16;
321+ __le32 ibf_data_bw:2;
322+ __le32 ibf_nc:3;
323+ __le32 ibf_nr:3;
324+ __le32 ibf_ru:8;
325+
326+ __le32 mob_delta_t:8;
327+ __le32 mob_lq_result:7;
328+ __le32 _rsv5:1;
329+ __le32 _rsv6:16;
330+
331+ __le32 _rsv7;
332+} __packed;
333+
334+struct mt7915_pfmu_tag {
335+ struct mt7915_pfmu_tag1 t1;
336+ struct mt7915_pfmu_tag2 t2;
337+};
338+
339+struct mt7915_bf_status_hdr {
340+ u8 format_id;
341+ u8 bw;
342+ u16 subcarrier_idx;
343+ bool bfer;
344+ u8 rsv[3];
345+} __packed;
346+
347+struct mt7915_bf_status {
348+ struct mt7915_bf_status_hdr hdr;
349+ u8 buf[1000];
350+} __packed;
351+
352+struct mt7915_txbf_phase_out {
353+ u8 c0_l;
354+ u8 c1_l;
355+ u8 c2_l;
356+ u8 c3_l;
357+ u8 c0_m;
358+ u8 c1_m;
359+ u8 c2_m;
360+ u8 c3_m;
361+ u8 c0_h;
362+ u8 c1_h;
363+ u8 c2_h;
364+ u8 c3_h;
365+ u8 c0_uh;
366+ u8 c1_uh;
367+ u8 c2_uh;
368+ u8 c3_uh;
369+};
370+
371+struct mt7915_txbf_phase {
372+ u8 status;
373+ struct {
374+ u8 r0_uh;
375+ u8 r0_h;
376+ u8 r0_m;
377+ u8 r0_l;
378+ u8 r0_ul;
379+ u8 r1_uh;
380+ u8 r1_h;
381+ u8 r1_m;
382+ u8 r1_l;
383+ u8 r1_ul;
384+ u8 r2_uh;
385+ u8 r2_h;
386+ u8 r2_m;
387+ u8 r2_l;
388+ u8 r2_ul;
389+ u8 r3_uh;
390+ u8 r3_h;
391+ u8 r3_m;
392+ u8 r3_l;
393+ u8 r3_ul;
394+ u8 r2_uh_sx2;
395+ u8 r2_h_sx2;
396+ u8 r2_m_sx2;
397+ u8 r2_l_sx2;
398+ u8 r2_ul_sx2;
399+ u8 r3_uh_sx2;
400+ u8 r3_h_sx2;
401+ u8 r3_m_sx2;
402+ u8 r3_l_sx2;
403+ u8 r3_ul_sx2;
404+ u8 m_t0_h;
405+ u8 m_t1_h;
406+ u8 m_t2_h;
407+ u8 m_t2_h_sx2;
408+ u8 r0_reserved;
409+ u8 r1_reserved;
410+ u8 r2_reserved;
411+ u8 r3_reserved;
412+ u8 r2_sx2_reserved;
413+ u8 r3_sx2_reserved;
414+ } phase;
415+};
416+
417+struct mt7915_pfmu_data {
418+ __le16 subc_idx;
419+ __le16 phi11;
420+ __le16 phi21;
421+ __le16 phi31;
422+};
423+
424+struct mt7915_ibf_cal_info {
425+ u8 format_id;
426+ u8 group_l_m_n;
427+ u8 group;
428+ bool sx2;
429+ u8 status;
430+ u8 cal_type;
431+ u8 _rsv[2];
432+ u8 buf[1000];
433+} __packed;
434+
435+enum {
436+ IBF_PHASE_CAL_UNSPEC,
437+ IBF_PHASE_CAL_NORMAL,
438+ IBF_PHASE_CAL_VERIFY,
439+ IBF_PHASE_CAL_NORMAL_INSTRUMENT,
440+ IBF_PHASE_CAL_VERIFY_INSTRUMENT,
441+};
442+
443+#define MT7915_TXBF_SUBCAR_NUM 64
444+
445+#endif
446+
447 enum {
448 MURU_SET_ARB_OP_MODE = 14,
449 MURU_SET_PLATFORM_TYPE = 25,
450diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer0443cd32023-09-19 14:11:49 +0800451index 87a5c5c..6dd6eca 100644
developer1346ce52022-12-15 21:36:14 +0800452--- a/mt7915/mmio.c
453+++ b/mt7915/mmio.c
developerc04f5402023-02-03 09:22:26 +0800454@@ -133,6 +133,7 @@ static const u32 mt7915_offs[] = {
developer1346ce52022-12-15 21:36:14 +0800455 [MDP_BNRCFR1] = 0x074,
456 [ARB_DRNGR0] = 0x194,
457 [ARB_SCR] = 0x080,
458+ [ARB_TQSAXM0] = 0x030,
459 [RMAC_MIB_AIRTIME14] = 0x3b8,
460 [AGG_AALCR0] = 0x048,
461 [AGG_AWSCR0] = 0x05c,
developerc04f5402023-02-03 09:22:26 +0800462@@ -209,6 +210,7 @@ static const u32 mt7916_offs[] = {
developer1346ce52022-12-15 21:36:14 +0800463 [MDP_BNRCFR1] = 0x094,
464 [ARB_DRNGR0] = 0x1e0,
465 [ARB_SCR] = 0x000,
466+ [ARB_TQSAXM0] = 0x180,
467 [RMAC_MIB_AIRTIME14] = 0x0398,
468 [AGG_AALCR0] = 0x028,
469 [AGG_AWSCR0] = 0x030,
470diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerb3cb52e2023-10-27 15:16:48 +0800471index 78ddbaf..2ef63a3 100644
developer1346ce52022-12-15 21:36:14 +0800472--- a/mt7915/mt7915.h
473+++ b/mt7915/mt7915.h
developerb3cb52e2023-10-27 15:16:48 +0800474@@ -275,7 +275,6 @@ struct mt7915_phy {
developer1346ce52022-12-15 21:36:14 +0800475
476 u8 spe_idx;
477
478- bool bf_en;
479 bool bf_ever_en;
480 } test;
481 #endif
developerb3cb52e2023-10-27 15:16:48 +0800482@@ -380,7 +379,7 @@ struct mt7915_dev {
developer1346ce52022-12-15 21:36:14 +0800483 void __iomem *dcm;
484 void __iomem *sku;
485
486-#ifdef CONFIG_NL80211_TESTMODE
487+#if defined CONFIG_NL80211_TESTMODE || defined MTK_DEBUG
488 struct {
489 void *txbf_phase_cal;
490 void *txbf_pfmu_data;
developerb3cb52e2023-10-27 15:16:48 +0800491@@ -519,6 +518,7 @@ int mt7915_dma_reset(struct mt7915_dev *dev, bool force);
developer2157bf82023-06-26 02:27:49 +0800492 int mt7915_dma_start(struct mt7915_dev *dev, bool reset, bool wed_reset);
developer1346ce52022-12-15 21:36:14 +0800493 int mt7915_txbf_init(struct mt7915_dev *dev);
developer849549c2023-08-02 17:26:48 +0800494 void mt7915_init_txpower(struct mt7915_phy *phy);
developer1346ce52022-12-15 21:36:14 +0800495+int mt7915_init_vif(struct mt7915_phy *phy, struct ieee80211_vif *vif, bool bf_en);
developer1346ce52022-12-15 21:36:14 +0800496 void mt7915_reset(struct mt7915_dev *dev);
developer849549c2023-08-02 17:26:48 +0800497 int mt7915_run(struct ieee80211_hw *hw);
498 int mt7915_mcu_init(struct mt7915_dev *dev);
developerb3cb52e2023-10-27 15:16:48 +0800499@@ -599,8 +599,10 @@ int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
developer1346ce52022-12-15 21:36:14 +0800500 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
501 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
502 void mt7915_mcu_exit(struct mt7915_dev *dev);
503-int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb);
504+
505+#ifdef CONFIG_NL80211_TESTMODE
506 void mt7915_tm_rf_test_event(struct mt7915_dev *dev, struct sk_buff *skb);
507+#endif
508
509 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
510 {
developerb3cb52e2023-10-27 15:16:48 +0800511@@ -735,4 +737,10 @@ enum {
developer1346ce52022-12-15 21:36:14 +0800512
513 #endif
514
515+#if defined CONFIG_NL80211_TESTMODE || defined MTK_DEBUG
516+int mt7915_mcu_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb);
517+int mt7915_mcu_txbf_profile_tag_read(struct mt7915_phy *phy, u8 pfmu_idx, bool bfer);
518+int mt7915_mcu_txbf_sta_rec_read(struct mt7915_dev *dev, u16 wlan_idx);
519+#endif
520+
521 #endif
522diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
developerb3cb52e2023-10-27 15:16:48 +0800523index 587497b..2ce1837 100644
developer1346ce52022-12-15 21:36:14 +0800524--- a/mt7915/mtk_debugfs.c
525+++ b/mt7915/mtk_debugfs.c
developer0443cd32023-09-19 14:11:49 +0800526@@ -2890,6 +2890,36 @@ mt7915_txpower_level_set(void *data, u64 val)
developer1346ce52022-12-15 21:36:14 +0800527 DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
528 mt7915_txpower_level_set, "%lld\n");
529
530+static int
531+mt7915_txbf_pfmu_tag_read(void *data, u64 val)
532+{
533+ struct mt7915_phy *phy = data;
534+ u8 pfmu_idx = (u8)val;
535+
536+ pr_info("%s: %d pfmu_tag cmd sent out ---\n", __func__, __LINE__);
537+ mt7915_mcu_txbf_profile_tag_read(phy, pfmu_idx, true);
538+
539+ return 0;
540+}
541+
542+DEFINE_DEBUGFS_ATTRIBUTE(fops_txbf_pfmu_tag_idx, NULL,
543+ mt7915_txbf_pfmu_tag_read, "%llx\n");
544+
545+static int
546+mt7915_txbf_sta_rec_read(void *data, u64 val)
547+{
548+ struct mt7915_dev *dev = data;
549+ u16 wlan_idx = (u16)val;
550+
551+ pr_info("%s: %d sta_rec cmd sent out ---\n", __func__, __LINE__);
552+ mt7915_mcu_txbf_sta_rec_read(dev, wlan_idx);
553+
554+ return 0;
555+}
556+
557+DEFINE_DEBUGFS_ATTRIBUTE(fops_txbf_sta_rec, NULL,
558+ mt7915_txbf_sta_rec_read, "%llx\n");
559+
560 /* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
561 static int
562 mt7915_wa_set(void *data, u64 val)
developer0443cd32023-09-19 14:11:49 +0800563@@ -3649,6 +3679,11 @@ int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
developer1346ce52022-12-15 21:36:14 +0800564 debugfs_create_file("txpower_level", 0400, dir, dev,
565 &fops_txpower_level);
566
developerb3cb52e2023-10-27 15:16:48 +0800567+ debugfs_create_file("pfmu_tag_read", 0600, dir, phy,
developer1346ce52022-12-15 21:36:14 +0800568+ &fops_txbf_pfmu_tag_idx);
developerb3cb52e2023-10-27 15:16:48 +0800569+ debugfs_create_file("bf_starec_read", 0600, dir, dev,
developer1346ce52022-12-15 21:36:14 +0800570+ &fops_txbf_sta_rec);
571+
572 debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
573
developer2dec9342023-05-23 16:11:58 +0800574 return 0;
developer1346ce52022-12-15 21:36:14 +0800575diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
developerd0527512023-11-07 09:54:54 +0800576index 143dae2..7a2d28c 100644
developer1346ce52022-12-15 21:36:14 +0800577--- a/mt7915/mtk_mcu.c
578+++ b/mt7915/mtk_mcu.c
579@@ -1,9 +1,10 @@
580 #include <linux/firmware.h>
581 #include <linux/fs.h>
582-#include<linux/inet.h>
583+#include <linux/inet.h>
584 #include "mt7915.h"
585 #include "mcu.h"
586 #include "mac.h"
587+#include "testmode.h"
588
589 int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
590 {
developerd0527512023-11-07 09:54:54 +0800591@@ -49,3 +50,247 @@ int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
developer1346ce52022-12-15 21:36:14 +0800592 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
593 sizeof(req), true);
594 }
595+
596+#if defined CONFIG_NL80211_TESTMODE || defined MTK_DEBUG
597+static void mt7915_txbf_dump_pfmu_tag(struct mt7915_dev *dev, struct mt7915_pfmu_tag *tag)
598+{
599+ u32 *raw_t1 = (u32 *)&tag->t1;
600+ u32 *raw_t2 = (u32 *)&tag->t2;
601+
602+ dev_info(dev->mt76.dev, "=================== TXBf Profile Tag1 Info ==================\n");
603+ dev_info(dev->mt76.dev,
604+ "DW0 = 0x%08x, DW1 = 0x%08x, DW2 = 0x%08x\n",
605+ raw_t1[0], raw_t1[1], raw_t1[2]);
606+ dev_info(dev->mt76.dev,
607+ "DW4 = 0x%08x, DW5 = 0x%08x, DW6 = 0x%08x\n\n",
608+ raw_t1[3], raw_t1[4], raw_t1[5]);
609+ dev_info(dev->mt76.dev, "PFMU ID = %d Invalid status = %d\n",
610+ tag->t1.pfmu_idx, tag->t1.invalid_prof);
611+ dev_info(dev->mt76.dev, "iBf/eBf = %d\n\n", tag->t1.ebf);
612+ dev_info(dev->mt76.dev, "DBW = %d\n", tag->t1.data_bw);
613+ dev_info(dev->mt76.dev, "SU/MU = %d\n", tag->t1.is_mu);
614+ dev_info(dev->mt76.dev, "RMSD = %d\n", tag->t1.rmsd);
615+ dev_info(dev->mt76.dev,
616+ "nrow = %d, ncol = %d, ng = %d, LM = %d, CodeBook = %d MobCalEn = %d\n",
617+ tag->t1.nr, tag->t1.nc, tag->t1.ngroup, tag->t1.lm, tag->t1.codebook,
618+ tag->t1.mob_cal_en);
619+ dev_info(dev->mt76.dev, "RU start = %d, RU end = %d\n",
620+ tag->t1.ru_start_id, tag->t1.ru_end_id);
621+ dev_info(dev->mt76.dev, "Mem Col1 = %d, Mem Row1 = %d, Mem Col2 = %d, Mem Row2 = %d\n",
622+ tag->t1.col_id1, tag->t1.row_id1, tag->t1.col_id2, tag->t1.row_id2);
623+ dev_info(dev->mt76.dev, "Mem Col3 = %d, Mem Row3 = %d, Mem Col4 = %d, Mem Row4 = %d\n\n",
624+ tag->t1.col_id3, tag->t1.row_id3, tag->t1.col_id4, tag->t1.row_id4);
625+ dev_info(dev->mt76.dev,
626+ "STS0_SNR = 0x%02x, STS1_SNR = 0x%02x, STS2_SNR = 0x%02x, STS3_SNR = 0x%02x\n",
627+ tag->t1.snr_sts0, tag->t1.snr_sts1, tag->t1.snr_sts2, tag->t1.snr_sts3);
628+ dev_info(dev->mt76.dev,
629+ "STS4_SNR = 0x%02x, STS5_SNR = 0x%02x, STS6_SNR = 0x%02x, STS7_SNR = 0x%02x\n",
630+ tag->t1.snr_sts4, tag->t1.snr_sts5, tag->t1.snr_sts6, tag->t1.snr_sts7);
631+ dev_info(dev->mt76.dev, "=============================================================\n");
632+
633+ dev_info(dev->mt76.dev, "=================== TXBf Profile Tag2 Info ==================\n");
634+ dev_info(dev->mt76.dev,
635+ "DW0 = 0x%08x, DW1 = 0x%08x, DW2 = 0x%08x\n",
636+ raw_t2[0], raw_t2[1], raw_t2[2]);
637+ dev_info(dev->mt76.dev,
638+ "DW3 = 0x%08x, DW4 = 0x%08x, DW5 = 0x%08x\n\n",
639+ raw_t2[3], raw_t2[4], raw_t2[5]);
640+ dev_info(dev->mt76.dev, "Smart antenna ID = 0x%x, SE index = %d\n",
641+ tag->t2.smart_ant, tag->t2.se_idx);
642+ dev_info(dev->mt76.dev, "RMSD threshold = %d\n", tag->t2.rmsd_thres);
643+ dev_info(dev->mt76.dev, "Timeout = 0x%x\n", tag->t2.ibf_timeout);
644+ dev_info(dev->mt76.dev, "Desired BW = %d, Desired Ncol = %d, Desired Nrow = %d\n",
645+ tag->t2.ibf_data_bw, tag->t2.ibf_nc, tag->t2.ibf_nr);
646+ dev_info(dev->mt76.dev, "Desired RU Allocation = %d\n", tag->t2.ibf_ru);
647+ dev_info(dev->mt76.dev, "Mobility DeltaT = %d, Mobility LQ = %d\n",
648+ tag->t2.mob_delta_t, tag->t2.mob_lq_result);
649+ dev_info(dev->mt76.dev, "=============================================================\n");
650+}
651+
652+static void mt7915_txbf_dump_sta_rec(struct mt7915_dev *dev, struct sta_rec_bf *sta_info)
653+{
654+ dev_info(dev->mt76.dev, "===================== BF Station Record =====================\n");
655+ dev_info(dev->mt76.dev, "pfmu = %d\n", sta_info->pfmu);
656+ dev_info(dev->mt76.dev, "su_mu = %d\n", sta_info->su_mu);
657+ dev_info(dev->mt76.dev, "bf_cap = %d\n", sta_info->bf_cap);
658+ dev_info(dev->mt76.dev, "sounding_phy = %d\n", sta_info->sounding_phy);
659+ dev_info(dev->mt76.dev, "ndpa_rate = %d\n", sta_info->ndpa_rate);
660+ dev_info(dev->mt76.dev, "ndp_rate = %d\n", sta_info->ndp_rate);
661+ dev_info(dev->mt76.dev, "rept_poll_rate = %d\n", sta_info->rept_poll_rate);
662+ dev_info(dev->mt76.dev, "tx_mode = %d\n", sta_info->tx_mode);
663+ dev_info(dev->mt76.dev, "ncol = %d\n", sta_info->ncol);
664+ dev_info(dev->mt76.dev, "nrow = %d\n", sta_info->nrow);
665+ dev_info(dev->mt76.dev, "bw = %d\n", sta_info->bw);
666+ dev_info(dev->mt76.dev, "mem_total = %d\n", sta_info->mem_total);
667+ dev_info(dev->mt76.dev, "mem_20m = %d\n", sta_info->mem_20m);
668+ dev_info(dev->mt76.dev, "mem_row0 = %d\n", sta_info->mem[0].row);
669+ dev_info(dev->mt76.dev, "mem_col0 = %d\n", sta_info->mem[0].col);
670+ dev_info(dev->mt76.dev, "mem_row1 = %d\n", sta_info->mem[1].row);
671+ dev_info(dev->mt76.dev, "mem_col1 = %d\n", sta_info->mem[1].col);
672+ dev_info(dev->mt76.dev, "mem_row2 = %d\n", sta_info->mem[2].row);
673+ dev_info(dev->mt76.dev, "mem_col2 = %d\n", sta_info->mem[2].col);
674+ dev_info(dev->mt76.dev, "mem_row3 = %d\n", sta_info->mem[3].row);
675+ dev_info(dev->mt76.dev, "mem_col3 = %d\n", sta_info->mem[3].col);
676+ dev_info(dev->mt76.dev, "smart_ant = 0x%x\n", sta_info->smart_ant);
677+ dev_info(dev->mt76.dev, "se_idx = %d\n", sta_info->se_idx);
678+ dev_info(dev->mt76.dev, "auto_sounding = %d\n", sta_info->auto_sounding);
679+ dev_info(dev->mt76.dev, "ibf_timeout = 0x%x\n", sta_info->ibf_timeout);
680+ dev_info(dev->mt76.dev, "ibf_dbw = %d\n", sta_info->ibf_dbw);
681+ dev_info(dev->mt76.dev, "ibf_ncol = %d\n", sta_info->ibf_ncol);
682+ dev_info(dev->mt76.dev, "ibf_nrow = %d\n", sta_info->ibf_nrow);
683+ dev_info(dev->mt76.dev, "nrow_gt_bw80 = %d\n", sta_info->nrow_gt_bw80);
684+ dev_info(dev->mt76.dev, "ncol_gt_bw80 = %d\n", sta_info->ncol_gt_bw80);
685+ dev_info(dev->mt76.dev, "ru_start_idx = %d\n", sta_info->ru_start_idx);
686+ dev_info(dev->mt76.dev, "trigger_su = %d\n", sta_info->trigger_su);
687+ dev_info(dev->mt76.dev, "trigger_mu = %d\n", sta_info->trigger_mu);
688+ dev_info(dev->mt76.dev, "ng16_su = %d\n", sta_info->ng16_su);
689+ dev_info(dev->mt76.dev, "ng16_mu = %d\n", sta_info->ng16_mu);
690+ dev_info(dev->mt76.dev, "codebook42_su = %d\n", sta_info->codebook42_su);
691+ dev_info(dev->mt76.dev, "codebook75_mu = %d\n", sta_info->codebook75_mu);
692+ dev_info(dev->mt76.dev, "he_ltf = %d\n", sta_info->he_ltf);
693+ dev_info(dev->mt76.dev, "=============================================================\n");
694+}
695+
696+static void mt7915_txbf_dump_cal_phase(struct mt7915_dev *dev,
697+ struct mt7915_txbf_phase *phase, int group)
698+{
699+ dev_info(dev->mt76.dev, "Group %d and Group M\n", group);
700+ dev_info(dev->mt76.dev, "m_t0_h = %d\n", phase->phase.m_t0_h);
701+ dev_info(dev->mt76.dev, "m_t1_h = %d\n", phase->phase.m_t1_h);
702+ dev_info(dev->mt76.dev, "m_t2_h = %d\n", phase->phase.m_t2_h);
703+
704+ dev_info(dev->mt76.dev, "r0_uh = %d\n", phase->phase.r0_uh);
705+ dev_info(dev->mt76.dev, "r0_h = %d\n", phase->phase.r0_h);
706+ dev_info(dev->mt76.dev, "r0_m = %d\n", phase->phase.r0_m);
707+ dev_info(dev->mt76.dev, "r0_l = %d\n", phase->phase.r0_l);
708+
709+ dev_info(dev->mt76.dev, "r1_uh = %d\n", phase->phase.r1_uh);
710+ dev_info(dev->mt76.dev, "r1_h = %d\n", phase->phase.r1_h);
711+ dev_info(dev->mt76.dev, "r1_m = %d\n", phase->phase.r1_m);
712+ dev_info(dev->mt76.dev, "r1_l = %d\n", phase->phase.r1_l);
713+
714+ dev_info(dev->mt76.dev, "r2_uh = %d\n", phase->phase.r2_uh);
715+ dev_info(dev->mt76.dev, "r2_h = %d\n", phase->phase.r2_h);
716+ dev_info(dev->mt76.dev, "r2_m = %d\n", phase->phase.r2_m);
717+ dev_info(dev->mt76.dev, "r2_l = %d\n", phase->phase.r2_l);
718+
719+ dev_info(dev->mt76.dev, "r3_uh = %d\n", phase->phase.r3_uh);
720+ dev_info(dev->mt76.dev, "r3_h = %d\n", phase->phase.r3_h);
721+ dev_info(dev->mt76.dev, "r3_m = %d\n", phase->phase.r3_m);
722+ dev_info(dev->mt76.dev, "r3_l = %d\n", phase->phase.r3_l);
723+ dev_info(dev->mt76.dev, "r3_ul = %d\n", phase->phase.r3_ul);
724+}
725+
726+int mt7915_mcu_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb)
727+{
728+#define BF_PFMU_TAG 16
729+#define BF_STA_REC 20
730+#define BF_CAL_PHASE 21
731+#define GROUP_M 1
732+ u8 format_id;
733+
734+ skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd));
735+ format_id = *(u8 *)skb->data;
736+
737+ if (format_id == BF_PFMU_TAG) {
738+ struct mt7915_pfmu_tag *pfmu_tag;
739+
740+ skb_pull(skb, 8);
741+ pfmu_tag = (struct mt7915_pfmu_tag *)skb->data;
742+ mt7915_txbf_dump_pfmu_tag(dev, pfmu_tag);
743+ if (dev->test.txbf_pfmu_tag)
744+ memcpy(dev->test.txbf_pfmu_tag, pfmu_tag, sizeof(struct mt7915_pfmu_tag));
745+ } else if (format_id == BF_STA_REC) {
746+ struct sta_rec_bf *sta_rec;
747+
748+ skb_pull(skb, sizeof(struct mt7915_bf_status_hdr));
749+ /* padding 4 byte since bf_status->buf does not contain tag & len */
750+ skb_push(skb, 4);
751+ sta_rec = (struct sta_rec_bf *)skb->data;
752+
753+ mt7915_txbf_dump_sta_rec(dev, sta_rec);
754+ } else if (format_id == BF_CAL_PHASE) {
755+ u8 phase_out_len = sizeof(struct mt7915_txbf_phase_out);
756+ struct mt7915_ibf_cal_info *cal;
757+ struct mt7915_txbf_phase_out phase_out;
758+ struct mt7915_txbf_phase *phase =
759+ (struct mt7915_txbf_phase *)dev->test.txbf_phase_cal;
760+
761+ cal = (struct mt7915_ibf_cal_info *)skb->data;
762+ memcpy(&phase_out, cal->buf, phase_out_len);
763+ switch (cal->cal_type) {
764+ case IBF_PHASE_CAL_NORMAL:
765+ case IBF_PHASE_CAL_NORMAL_INSTRUMENT:
766+ /* Only calibrate group M */
767+ if (cal->group_l_m_n != GROUP_M)
768+ break;
769+ phase = &phase[cal->group];
770+ memcpy(&phase->phase, cal->buf + phase_out_len, sizeof(phase->phase));
771+ phase->status = cal->status;
772+
773+ dev_info(dev->mt76.dev, "Calibrated result = %d\n", phase->status);
774+ mt7915_txbf_dump_cal_phase(dev, phase, cal->group);
775+ break;
776+ case IBF_PHASE_CAL_VERIFY:
777+ case IBF_PHASE_CAL_VERIFY_INSTRUMENT:
778+ dev_info(dev->mt76.dev, "Verification result = %d\n", cal->status);
779+ break;
780+ default:
781+ break;
782+ }
783+
784+ dev_info(dev->mt76.dev, "c0_h = %d, c1_h = %d, c2_h = %d\n",
785+ phase_out.c0_h, phase_out.c1_h, phase_out.c2_h);
786+ dev_info(dev->mt76.dev, "c0_m = %d, c1_m = %d, c2_m = %d\n",
787+ phase_out.c0_m, phase_out.c1_m, phase_out.c2_m);
788+ dev_info(dev->mt76.dev, "c0_l = %d, c1_l = %d, c2_l = %d\n",
789+ phase_out.c0_l, phase_out.c1_l, phase_out.c2_l);
790+ dev_info(dev->mt76.dev, "c3_m = %d, c3_h = %d\n", phase_out.c3_m, phase_out.c3_h);
791+ }
792+
793+ wake_up(&dev->mt76.tx_wait);
794+
795+ return 0;
796+}
797+
798+int mt7915_mcu_txbf_profile_tag_read(struct mt7915_phy *phy, u8 pfmu_idx, bool bfer)
799+{
800+ struct mt7915_dev *dev = phy->dev;
801+ struct {
802+ u8 format_id;
803+ u8 pfmu_idx;
804+ bool bfer;
805+ u8 dbdc_idx;
806+ } __packed req = {
807+ .format_id = MT_BF_PFMU_TAG_READ,
808+ .pfmu_idx = pfmu_idx,
809+ .bfer = bfer,
810+ .dbdc_idx = phy->mt76->band_idx,
811+ };
developerd0527512023-11-07 09:54:54 +0800812+ struct mt7915_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
developer1346ce52022-12-15 21:36:14 +0800813+
814+ /* Reset to 0 for mt7915_tm_txbf_profile_tag_write wait_event */
developerd0527512023-11-07 09:54:54 +0800815+ if (tag)
816+ tag->t1.pfmu_idx = 0;
developer1346ce52022-12-15 21:36:14 +0800817+
818+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
819+ sizeof(req), true);
820+}
821+
822+int mt7915_mcu_txbf_sta_rec_read(struct mt7915_dev *dev, u16 wlan_idx)
823+{
824+ struct {
825+ u8 action;
826+ u8 wlan_idx_lo;
827+ u8 wlan_idx_hi;
828+ u8 rsv[5];
829+ } __packed req = {
830+ .action = MT_BF_STA_REC_READ,
831+ .wlan_idx_lo = to_wcid_lo(wlan_idx),
832+ .wlan_idx_hi = to_wcid_hi(wlan_idx),
833+ };
834+
835+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
836+ sizeof(req), true);
837+}
838+#endif
839diff --git a/mt7915/regs.h b/mt7915/regs.h
developer0443cd32023-09-19 14:11:49 +0800840index 44863e8..1f1f8b9 100644
developer1346ce52022-12-15 21:36:14 +0800841--- a/mt7915/regs.h
842+++ b/mt7915/regs.h
843@@ -61,6 +61,7 @@ enum offs_rev {
844 MDP_BNRCFR1,
845 ARB_DRNGR0,
846 ARB_SCR,
847+ ARB_TQSAXM0,
848 RMAC_MIB_AIRTIME14,
849 AGG_AALCR0,
850 AGG_AWSCR0,
developer0443cd32023-09-19 14:11:49 +0800851@@ -534,6 +535,9 @@ enum offs_rev {
developer1346ce52022-12-15 21:36:14 +0800852 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \
853 (_n) * 4))
854
855+#define MT_ARB_TQSAXM0(_band) MT_WF_ARB(_band, __OFFS(ARB_TQSAXM0))
856+#define MT_ARB_TQSAXM_ALTX_START_MASK GENMASK(12, 8)
857+
858 /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */
859 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
860 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
861diff --git a/mt7915/testmode.c b/mt7915/testmode.c
developerb3cb52e2023-10-27 15:16:48 +0800862index 1e6791e..5e20cb9 100644
developer1346ce52022-12-15 21:36:14 +0800863--- a/mt7915/testmode.c
864+++ b/mt7915/testmode.c
developerb3cb52e2023-10-27 15:16:48 +0800865@@ -55,6 +55,8 @@ struct reg_band {
developer1346ce52022-12-15 21:36:14 +0800866 static struct reg_band reg_backup_list[TM_REG_MAX_ID];
867
868 static void mt7915_tm_update_entry(struct mt7915_phy *phy);
869+static int mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode, bool bf_sounding);
870+static int mt7915_tm_txbf_set_rate(struct mt7915_phy *phy, struct mt76_wcid *wcid);
871
872 static u8 mt7915_tm_chan_bw(enum nl80211_chan_width width)
873 {
developerb3cb52e2023-10-27 15:16:48 +0800874@@ -94,6 +96,25 @@ mt7915_tm_check_antenna(struct mt7915_phy *phy)
developer2157bf82023-06-26 02:27:49 +0800875 return 0;
developer1346ce52022-12-15 21:36:14 +0800876 }
877
878+static u8 mt7915_tm_rate_to_phy(u8 tx_rate_mode)
879+{
880+ static const u8 rate_to_phy[] = {
881+ [MT76_TM_TX_MODE_CCK] = MT_PHY_TYPE_CCK,
882+ [MT76_TM_TX_MODE_OFDM] = MT_PHY_TYPE_OFDM,
883+ [MT76_TM_TX_MODE_HT] = MT_PHY_TYPE_HT,
884+ [MT76_TM_TX_MODE_VHT] = MT_PHY_TYPE_VHT,
885+ [MT76_TM_TX_MODE_HE_SU] = MT_PHY_TYPE_HE_SU,
886+ [MT76_TM_TX_MODE_HE_EXT_SU] = MT_PHY_TYPE_HE_EXT_SU,
887+ [MT76_TM_TX_MODE_HE_TB] = MT_PHY_TYPE_HE_TB,
888+ [MT76_TM_TX_MODE_HE_MU] = MT_PHY_TYPE_HE_MU,
889+ };
890+
891+ if (tx_rate_mode > MT76_TM_TX_MODE_MAX)
892+ return -EINVAL;
893+
894+ return rate_to_phy[tx_rate_mode];
895+}
896+
897 static void
898 mt7915_tm_update_channel(struct mt7915_phy *phy)
899 {
developerb3cb52e2023-10-27 15:16:48 +0800900@@ -294,17 +315,33 @@ mt7915_tm_add_txbf(struct mt7915_phy *phy, struct ieee80211_vif *vif,
developer1346ce52022-12-15 21:36:14 +0800901 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
902 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
903 struct mt7915_dev *dev = phy->dev;
904+ struct mt76_testmode_data *td = &phy->mt76->test;
905 struct sk_buff *skb;
906 struct sta_rec_bf *bf;
907 struct tlv *tlv;
908- u8 ndp_rate;
909+ u8 ndp_rate, ndpa_rate, rept_poll_rate, bf_bw;
910+
911+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_SU) {
912+ rept_poll_rate = 0x49;
913+ ndpa_rate = 0x49;
914+ ndp_rate = 0;
915+ } else if (td->tx_rate_mode == MT76_TM_TX_MODE_VHT) {
916+ rept_poll_rate = 0x9;
917+ ndpa_rate = 0x9;
918+ ndp_rate = 0;
919+ } else {
920+ rept_poll_rate = 0;
921+ ndpa_rate = 0;
922+ if (nr == 1)
923+ ndp_rate = 8;
924+ else if (nr == 2)
925+ ndp_rate = 16;
926+ else
927+ ndp_rate = 24;
928+ }
929
930- if (nr == 1)
931- ndp_rate = 8;
932- else if (nr == 2)
933- ndp_rate = 16;
934- else
935- ndp_rate = 24;
developer78911262022-12-21 20:28:18 +0800936+ /* BF use CMD_CBW instead of TM_CBW */
937+ bf_bw = mt76_connac_chan_bw(&phy->mt76->chandef);
developer1346ce52022-12-15 21:36:14 +0800938
939 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
940 &msta->wcid);
developerb3cb52e2023-10-27 15:16:48 +0800941@@ -320,8 +357,11 @@ mt7915_tm_add_txbf(struct mt7915_phy *phy, struct ieee80211_vif *vif,
developer1346ce52022-12-15 21:36:14 +0800942 bf->ncol = nc;
943 bf->nrow = nr;
944 bf->ndp_rate = ndp_rate;
945+ bf->ndpa_rate = ndpa_rate;
946+ bf->rept_poll_rate = rept_poll_rate;
947+ bf->bw = bf_bw;
948 bf->ibf_timeout = 0xff;
949- bf->tx_mode = MT_PHY_TYPE_HT;
950+ bf->tx_mode = mt7915_tm_rate_to_phy(td->tx_rate_mode);
951
952 if (ebf) {
953 bf->mem[0].row = 0;
developerb3cb52e2023-10-27 15:16:48 +0800954@@ -374,11 +414,8 @@ mt7915_tm_entry_add(struct mt7915_phy *phy, u8 aid)
developer1346ce52022-12-15 21:36:14 +0800955 }
956
957 memcpy(sta->addr, ed->addr[0], ETH_ALEN);
958- if (phy->test.bf_en) {
959- u8 addr[ETH_ALEN] = {0x00, 0x11, 0x11, 0x11, 0x11, 0x11};
960-
961- memcpy(sta->addr, addr, ETH_ALEN);
962- }
963+ if (td->bf_en)
964+ memcpy(sta->addr, td->addr[0], ETH_ALEN);
965
966 if (td->tx_rate_mode >= MT76_TM_TX_MODE_HT)
developer6100db22023-04-05 13:22:26 +0800967 memcpy(&sta->deflink.ht_cap, &sband->ht_cap, sizeof(sta->deflink.ht_cap));
developerb3cb52e2023-10-27 15:16:48 +0800968@@ -403,6 +440,14 @@ mt7915_tm_entry_add(struct mt7915_phy *phy, u8 aid)
developer1346ce52022-12-15 21:36:14 +0800969 list_add_tail(&msta->wcid.list, &td->tm_entry_list);
970 td->entry_num++;
971
972+ mt7915_mcu_add_bss_info(phy, phy->monitor_vif, true);
973+
974+ if (td->bf_en) {
975+ mt7915_tm_set_ipg_params(phy, td->tx_ipg, td->tx_rate_mode, true);
976+ mt7915_tm_set_tam_arb(phy, td->bf_en, 0);
977+ mt7915_tm_txbf_set_rate(phy, &msta->wcid);
978+ }
979+
980 return 0;
981 }
982
developerb3cb52e2023-10-27 15:16:48 +0800983@@ -472,7 +517,7 @@ mt7915_tm_update_entry(struct mt7915_phy *phy)
developer1346ce52022-12-15 21:36:14 +0800984 struct mt76_testmode_entry_data *ed, tmp;
985 struct mt76_wcid *wcid, *last;
986
987- if (!td->aid || phy->test.bf_en)
988+ if (!td->aid || td->bf_en)
989 return;
990
991 memcpy(&tmp, &td->ed, sizeof(tmp));
developerb3cb52e2023-10-27 15:16:48 +0800992@@ -493,20 +538,30 @@ mt7915_tm_update_entry(struct mt7915_phy *phy)
developer1346ce52022-12-15 21:36:14 +0800993 static int
994 mt7915_tm_txbf_init(struct mt7915_phy *phy, u16 *val)
995 {
996+#define EBF_BBP_RX_OFFSET 0x10280
997+#define EBF_BBP_RX_ENABLE (BIT(0) | BIT(15))
developer78911262022-12-21 20:28:18 +0800998+#define WF1 1
999+#define WF2 2
developer1346ce52022-12-15 21:36:14 +08001000 struct mt76_testmode_data *td = &phy->mt76->test;
1001 struct mt7915_dev *dev = phy->dev;
1002+ struct mt76_phy *mphy = phy->mt76;
1003 bool enable = val[0];
1004 void *phase_cal, *pfmu_data, *pfmu_tag;
1005- u8 addr[ETH_ALEN] = {0x00, 0x22, 0x22, 0x22, 0x22, 0x22};
1006+ u8 sub_addr = td->is_txbf_dut ? TXBF_DUT_MAC_SUBADDR : TXBF_GOLDEN_MAC_SUBADDR;
1007+ u8 peer_addr = td->is_txbf_dut ? TXBF_GOLDEN_MAC_SUBADDR : TXBF_DUT_MAC_SUBADDR;
1008+ u8 bss_addr = TXBF_DUT_MAC_SUBADDR;
1009+ u8 addr[ETH_ALEN] = {0x00, sub_addr, sub_addr, sub_addr, sub_addr, sub_addr};
1010+ u8 bssid[ETH_ALEN] = {0x00, bss_addr, bss_addr, bss_addr, bss_addr, bss_addr};
1011+ u8 peer_addrs[ETH_ALEN] = {0x00, peer_addr, peer_addr, peer_addr, peer_addr, peer_addr};
1012
1013 if (!enable) {
1014- phy->test.bf_en = 0;
1015+ td->bf_en = 0;
1016 return 0;
1017 }
1018
1019 if (!dev->test.txbf_phase_cal) {
1020 phase_cal = devm_kzalloc(dev->mt76.dev,
1021- sizeof(struct mt7915_tm_txbf_phase) *
1022+ sizeof(struct mt7915_txbf_phase) *
1023 MAX_PHASE_GROUP_NUM,
1024 GFP_KERNEL);
1025 if (!phase_cal)
developerb3cb52e2023-10-27 15:16:48 +08001026@@ -516,7 +571,10 @@ mt7915_tm_txbf_init(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001027 }
1028
1029 if (!dev->test.txbf_pfmu_data) {
1030- pfmu_data = devm_kzalloc(dev->mt76.dev, 512, GFP_KERNEL);
1031+ pfmu_data = devm_kzalloc(dev->mt76.dev,
1032+ sizeof(struct mt7915_pfmu_data) *
1033+ MT7915_TXBF_SUBCAR_NUM,
1034+ GFP_KERNEL);
1035 if (!pfmu_data)
1036 return -ENOMEM;
1037
developerb3cb52e2023-10-27 15:16:48 +08001038@@ -525,21 +583,77 @@ mt7915_tm_txbf_init(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001039
1040 if (!dev->test.txbf_pfmu_tag) {
1041 pfmu_tag = devm_kzalloc(dev->mt76.dev,
1042- sizeof(struct mt7915_tm_pfmu_tag), GFP_KERNEL);
1043+ sizeof(struct mt7915_pfmu_tag), GFP_KERNEL);
1044 if (!pfmu_tag)
1045 return -ENOMEM;
1046
1047 dev->test.txbf_pfmu_tag = pfmu_tag;
1048 }
1049
1050+ td->bf_en = 1;
1051+ memcpy(td->addr[0], peer_addrs, ETH_ALEN);
1052+ memcpy(td->addr[1], addr, ETH_ALEN);
1053+ memcpy(td->addr[2], bssid, ETH_ALEN);
1054 memcpy(phy->monitor_vif->addr, addr, ETH_ALEN);
1055 mt7915_mcu_add_dev_info(phy, phy->monitor_vif, true);
1056
1057- td->tx_rate_mode = MT76_TM_TX_MODE_HT;
1058- td->tx_mpdu_len = 1024;
1059- td->tx_rate_sgi = 0;
1060- td->tx_ipg = 100;
1061- phy->test.bf_en = 1;
1062+ /* Add second interface in wtbl for using TXCMD to transmit sounding */
1063+ td->second_vif = kzalloc(sizeof(*td->second_vif) + sizeof(struct mt7915_vif), GFP_KERNEL);
1064+ memcpy(td->second_vif, phy->monitor_vif, sizeof(*td->second_vif));
1065+ mt7915_init_vif(phy, td->second_vif, td->bf_en);
1066+
1067+ if (td->ebf && !td->is_txbf_dut) {
developer78911262022-12-21 20:28:18 +08001068+ u8 is_160hz = val[1];
developer1346ce52022-12-15 21:36:14 +08001069+
1070+ /* Turn On BBP CR for RX */
1071+ mt76_set(dev, EBF_BBP_RX_OFFSET, EBF_BBP_RX_ENABLE);
1072+ dev_info(dev->mt76.dev, "Set BBP RX CR = %x\n", mt76_rr(dev, EBF_BBP_RX_OFFSET));
1073+
1074+ /* Set TX antenna mask of golden: default use WF0 only */
1075+ td->tx_antenna_mask = 1;
1076+ if (is_mt7915(&dev->mt76)) {
1077+ /* Add WF1/WF2 for dbdc/single band in BW 160 */
developer78911262022-12-21 20:28:18 +08001078+ td->tx_antenna_mask |= is_160hz << (dev->dbdc_support ? WF1 : WF2);
developer1346ce52022-12-15 21:36:14 +08001079+ /* Shift to WF2/WF3 for dbdc band 1 */
1080+ td->tx_antenna_mask <<= 2 * phy->mt76->band_idx;
1081+ }
1082+ } else if (td->ebf && td->is_txbf_dut) {
1083+ /* Enable ETxBF Capability */
1084+ dev->ibf = false;
1085+ mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
1086+ /* Set TX antenna mask of DUT */
1087+ td->tx_antenna_mask = mphy->chainmask >> (dev->chainshift * phy->mt76->band_idx);
1088+ td->tx_spe_idx = phy->mt76->band_idx ? 25 : 24;
1089+ /* Shift to WF2/WF3 for dbdc band 1, Nss = 2 */
1090+ if ((hweight8(td->tx_antenna_mask) == 2) && phy->mt76->band_idx)
1091+ td->tx_antenna_mask <<= 2;
1092+ } else {
1093+ if (td->is_txbf_dut) {
1094+ int nss;
1095+
1096+ /* Enable ITxBF Capability */
1097+ dev->ibf = true;
1098+ mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
1099+ td->tx_antenna_mask = mphy->chainmask >> (dev->chainshift *
1100+ phy->mt76->band_idx);
1101+ nss = hweight8(td->tx_antenna_mask);
1102+ if (nss > 1 && nss <= 4)
1103+ td->tx_rate_idx = 15 + 8 * (nss - 2);
1104+ else
1105+ td->tx_rate_idx = 31;
1106+ } else {
1107+ td->tx_antenna_mask = 1;
1108+ mt76_set(dev, EBF_BBP_RX_OFFSET, EBF_BBP_RX_ENABLE);
1109+ dev_info(dev->mt76.dev, "Set BBP RX CR = %x\n",
1110+ mt76_rr(dev, EBF_BBP_RX_OFFSET));
1111+ }
1112+ td->tx_rate_mode = MT76_TM_TX_MODE_HT;
1113+ td->tx_mpdu_len = 1024;
1114+ td->tx_rate_sgi = 0;
1115+ td->tx_ipg = 100;
1116+ }
1117+
1118+ mt7915_mcu_add_bss_info(phy, phy->monitor_vif, true);
1119
1120 return mt7915_tm_set_trx(phy, TM_MAC_TX, true);
1121 }
developerb3cb52e2023-10-27 15:16:48 +08001122@@ -566,8 +680,7 @@ mt7915_tm_txbf_phase_comp(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001123 .read_from_e2p = val[3],
1124 .disable = val[4],
1125 };
1126- struct mt7915_tm_txbf_phase *phase =
1127- (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1128+ struct mt7915_txbf_phase *phase = (struct mt7915_txbf_phase *)dev->test.txbf_phase_cal;
1129
1130 wait_event_timeout(dev->mt76.tx_wait, phase[val[2]].status != 0, HZ);
1131 memcpy(req.buf, &phase[val[2]].phase, sizeof(req.buf));
developerb3cb52e2023-10-27 15:16:48 +08001132@@ -580,32 +693,9 @@ mt7915_tm_txbf_phase_comp(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001133 sizeof(req), true);
1134 }
1135
1136-static int
1137-mt7915_tm_txbf_profile_tag_read(struct mt7915_phy *phy, u8 pfmu_idx)
1138-{
1139- struct mt7915_dev *dev = phy->dev;
1140- struct {
1141- u8 format_id;
1142- u8 pfmu_idx;
1143- bool bfer;
1144- u8 dbdc_idx;
1145- } __packed req = {
1146- .format_id = MT_BF_PFMU_TAG_READ,
1147- .pfmu_idx = pfmu_idx,
1148- .bfer = 1,
1149- .dbdc_idx = phy != &dev->phy,
1150- };
1151- struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1152-
1153- tag->t1.pfmu_idx = 0;
1154-
1155- return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1156- sizeof(req), true);
1157-}
1158-
1159 static int
1160 mt7915_tm_txbf_profile_tag_write(struct mt7915_phy *phy, u8 pfmu_idx,
1161- struct mt7915_tm_pfmu_tag *tag)
1162+ struct mt7915_pfmu_tag *tag)
1163 {
1164 struct mt7915_dev *dev = phy->dev;
1165 struct {
developerb3cb52e2023-10-27 15:16:48 +08001166@@ -632,8 +722,6 @@ static int
developer1346ce52022-12-15 21:36:14 +08001167 mt7915_tm_txbf_apply_tx(struct mt7915_phy *phy, u16 wlan_idx, bool ebf,
1168 bool ibf, bool phase_cal)
1169 {
1170-#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1171-#define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1172 struct mt7915_dev *dev = phy->dev;
1173 struct {
1174 u8 category;
developerb3cb52e2023-10-27 15:16:48 +08001175@@ -662,14 +750,15 @@ static int mt7915_tm_txbf_set_rate(struct mt7915_phy *phy,
developer1346ce52022-12-15 21:36:14 +08001176 {
1177 struct mt7915_dev *dev = phy->dev;
1178 struct mt76_testmode_entry_data *ed = mt76_testmode_entry_data(phy->mt76, wcid);
1179+ struct mt76_testmode_data *td = &phy->mt76->test;
1180 struct ieee80211_sta *sta = wcid_to_sta(wcid);
1181 struct sta_phy rate = {};
1182
1183 if (!sta)
1184 return 0;
1185
1186- rate.type = MT_PHY_TYPE_HT;
1187- rate.bw = mt7915_tm_chan_bw(phy->mt76->chandef.width);
1188+ rate.type = mt7915_tm_rate_to_phy(td->tx_rate_mode);
developer78911262022-12-21 20:28:18 +08001189+ rate.bw = mt76_connac_chan_bw(&phy->mt76->chandef);
developer1346ce52022-12-15 21:36:14 +08001190 rate.nss = ed->tx_rate_nss;
1191 rate.mcs = ed->tx_rate_idx;
1192 rate.ldpc = (rate.bw || ed->tx_rate_ldpc) * GENMASK(2, 0);
developerb3cb52e2023-10-27 15:16:48 +08001193@@ -683,13 +772,14 @@ mt7915_tm_txbf_set_tx(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001194 {
1195 bool bf_on = val[0], update = val[3];
1196 /* u16 wlan_idx = val[2]; */
1197- struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1198+ struct mt7915_dev *dev = phy->dev;
1199+ struct mt7915_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
1200 struct mt76_testmode_data *td = &phy->mt76->test;
1201 struct mt76_wcid *wcid;
1202
1203 if (bf_on) {
1204 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1205- mt7915_tm_txbf_profile_tag_read(phy, 2);
1206+ mt7915_mcu_txbf_profile_tag_read(phy, 2, true);
1207 tag->t1.invalid_prof = false;
1208 mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1209
developerb3cb52e2023-10-27 15:16:48 +08001210@@ -704,7 +794,7 @@ mt7915_tm_txbf_set_tx(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001211 } else {
1212 phy->test.bf_ever_en = false;
1213
1214- mt7915_tm_txbf_profile_tag_read(phy, 2);
1215+ mt7915_mcu_txbf_profile_tag_read(phy, 2, true);
1216 tag->t1.invalid_prof = true;
1217 mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1218 }
developerb3cb52e2023-10-27 15:16:48 +08001219@@ -719,6 +809,7 @@ mt7915_tm_txbf_set_tx(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001220 static int
1221 mt7915_tm_txbf_profile_update(struct mt7915_phy *phy, u16 *val, bool ebf)
1222 {
1223+#define MT_ARB_IBF_ENABLE (BIT(0) | GENMASK(9, 8))
1224 static const u8 mode_to_lm[] = {
1225 [MT76_TM_TX_MODE_CCK] = 0,
1226 [MT76_TM_TX_MODE_OFDM] = 0,
developerb3cb52e2023-10-27 15:16:48 +08001227@@ -732,7 +823,8 @@ mt7915_tm_txbf_profile_update(struct mt7915_phy *phy, u16 *val, bool ebf)
developer1346ce52022-12-15 21:36:14 +08001228 struct mt76_testmode_data *td = &phy->mt76->test;
1229 struct mt76_wcid *wcid;
1230 struct ieee80211_vif *vif = phy->monitor_vif;
1231- struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1232+ struct mt7915_dev *dev = phy->dev;
1233+ struct mt7915_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
1234 u8 pfmu_idx = val[0], nc = val[2], nr;
1235 bool is_atenl = val[6];
1236 int ret;
developerb3cb52e2023-10-27 15:16:48 +08001237@@ -750,18 +842,22 @@ mt7915_tm_txbf_profile_update(struct mt7915_phy *phy, u16 *val, bool ebf)
developer1346ce52022-12-15 21:36:14 +08001238 tag->t1.nr = nr;
1239 tag->t1.nc = nc;
1240 tag->t1.invalid_prof = true;
1241-
1242- tag->t1.snr_sts4 = 0xc0;
1243- tag->t1.snr_sts5 = 0xff;
1244- tag->t1.snr_sts6 = 0xff;
1245- tag->t1.snr_sts7 = 0xff;
developer78911262022-12-21 20:28:18 +08001246+ tag->t1.data_bw = mt76_connac_chan_bw(&phy->mt76->chandef);
developer1346ce52022-12-15 21:36:14 +08001247+ tag->t2.se_idx = td->tx_spe_idx;
1248+
1249+ if (is_atenl) {
1250+ tag->t1.snr_sts4 = 0xc0;
1251+ tag->t1.snr_sts5 = 0xff;
1252+ tag->t1.snr_sts6 = 0xff;
1253+ tag->t1.snr_sts7 = 0xff;
1254+ }
1255
1256 if (ebf) {
1257 tag->t1.row_id1 = 0;
developer78911262022-12-21 20:28:18 +08001258 tag->t1.row_id2 = 1;
1259 tag->t1.row_id3 = 2;
1260 tag->t1.row_id4 = 3;
1261- tag->t1.lm = mode_to_lm[MT76_TM_TX_MODE_HT];
1262+ tag->t1.lm = mode_to_lm[td->tx_rate_mode];
1263 } else {
1264 tag->t1.row_id1 = 4;
1265 tag->t1.row_id2 = 5;
developerb3cb52e2023-10-27 15:16:48 +08001266@@ -782,6 +878,20 @@ mt7915_tm_txbf_profile_update(struct mt7915_phy *phy, u16 *val, bool ebf)
developer1346ce52022-12-15 21:36:14 +08001267 if (ret)
1268 return ret;
1269
1270+ if (td->ebf) {
1271+ mt76_set(dev, MT_ARB_TQSAXM0(phy->mt76->band_idx), MT_ARB_TQSAXM_ALTX_START_MASK);
1272+ dev_info(dev->mt76.dev, "Set TX queue start CR for AX management (0x%x) = 0x%x\n",
1273+ MT_ARB_TQSAXM0(phy->mt76->band_idx),
1274+ mt76_rr(dev, MT_ARB_TQSAXM0(phy->mt76->band_idx)));
1275+ } else if (!td->ebf && ebf) {
1276+ /* iBF's ebf profile update */
developere8045132023-08-04 14:40:12 +08001277+ if (!is_mt7915(&dev->mt76) || !dev->dbdc_support)
1278+ mt76_set(dev, MT_ARB_TQSAXM0(phy->mt76->band_idx), MT_ARB_IBF_ENABLE);
developer1346ce52022-12-15 21:36:14 +08001279+ dev_info(dev->mt76.dev, "Set TX queue start CR for AX management (0x%x) = 0x%x\n",
1280+ MT_ARB_TQSAXM0(phy->mt76->band_idx),
1281+ mt76_rr(dev, MT_ARB_TQSAXM0(phy->mt76->band_idx)));
1282+ }
1283+
1284 if (!ebf && is_atenl)
1285 return mt7915_tm_txbf_apply_tx(phy, 1, false, true, true);
1286
developerb3cb52e2023-10-27 15:16:48 +08001287@@ -799,7 +909,7 @@ mt7915_tm_txbf_phase_cal(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001288 u8 category;
1289 u8 group_l_m_n;
1290 u8 group;
1291- bool sx2;
1292+ bool dbdc_idx;
1293 u8 cal_type;
1294 u8 lna_gain_level;
1295 u8 _rsv[2];
developerb3cb52e2023-10-27 15:16:48 +08001296@@ -807,12 +917,12 @@ mt7915_tm_txbf_phase_cal(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001297 .category = MT_BF_PHASE_CAL,
1298 .group = val[0],
1299 .group_l_m_n = val[1],
1300- .sx2 = val[2],
1301+ .dbdc_idx = phy->mt76->band_idx,
1302 .cal_type = val[3],
1303 .lna_gain_level = val[4],
1304 };
1305- struct mt7915_tm_txbf_phase *phase =
1306- (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1307+ struct mt7915_txbf_phase *phase =
1308+ (struct mt7915_txbf_phase *)dev->test.txbf_phase_cal;
1309
1310 phase[req.group].status = 0;
1311
developerb3cb52e2023-10-27 15:16:48 +08001312@@ -820,53 +930,10 @@ mt7915_tm_txbf_phase_cal(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001313 sizeof(req), true);
1314 }
1315
1316-int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb)
1317-{
1318-#define BF_PFMU_TAG 16
1319-#define BF_CAL_PHASE 21
1320- u8 format_id;
1321-
1322- skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd));
1323- format_id = *(u8 *)skb->data;
1324-
1325- if (format_id == BF_PFMU_TAG) {
1326- struct mt7915_tm_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
1327-
1328- skb_pull(skb, 8);
1329- memcpy(tag, skb->data, sizeof(struct mt7915_tm_pfmu_tag));
1330- } else if (format_id == BF_CAL_PHASE) {
1331- struct mt7915_tm_ibf_cal_info *cal;
1332- struct mt7915_tm_txbf_phase *phase =
1333- (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1334-
1335- cal = (struct mt7915_tm_ibf_cal_info *)skb->data;
1336- switch (cal->cal_type) {
1337- case IBF_PHASE_CAL_NORMAL:
1338- case IBF_PHASE_CAL_NORMAL_INSTRUMENT:
1339- if (cal->group_l_m_n != GROUP_M)
1340- break;
1341- phase = &phase[cal->group];
1342- memcpy(&phase->phase, cal->buf + 16, sizeof(phase->phase));
1343- phase->status = cal->status;
1344- /* for passing iTest script */
1345- dev_info(dev->mt76.dev, "Calibrated result = %d\n", phase->status);
1346- break;
1347- case IBF_PHASE_CAL_VERIFY:
1348- case IBF_PHASE_CAL_VERIFY_INSTRUMENT:
1349- break;
1350- default:
1351- break;
1352- }
1353- }
1354-
1355- wake_up(&dev->mt76.tx_wait);
1356-
1357- return 0;
1358-}
1359-
1360 static int
1361 mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
1362 {
1363+#define MT7915_TXBF_PFMU_DATA_LEN (MT7915_TXBF_SUBCAR_NUM * sizeof(struct mt7915_pfmu_data))
1364 struct mt76_testmode_data *td = &phy->mt76->test;
developere8045132023-08-04 14:40:12 +08001365 u8 nss = hweight8(td->tx_antenna_mask);
developer1346ce52022-12-15 21:36:14 +08001366 u16 pfmu_idx = val[0];
developerb3cb52e2023-10-27 15:16:48 +08001367@@ -876,9 +943,9 @@ mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001368 u16 angle31 = val[4];
1369 u16 angle41 = val[5];
1370 s16 phi11 = 0, phi21 = 0, phi31 = 0;
1371- struct mt7915_tm_pfmu_data *pfmu_data;
1372+ struct mt7915_pfmu_data *pfmu_data;
1373
1374- if (subc_id > 63)
1375+ if (subc_id > MT7915_TXBF_SUBCAR_NUM - 1)
1376 return -EINVAL;
1377
developere8045132023-08-04 14:40:12 +08001378 if (nss == 2) {
developerb3cb52e2023-10-27 15:16:48 +08001379@@ -892,7 +959,7 @@ mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001380 phi31 = (s16)(angle41 - angle31);
1381 }
1382
1383- pfmu_data = (struct mt7915_tm_pfmu_data *)phy->dev->test.txbf_pfmu_data;
1384+ pfmu_data = (struct mt7915_pfmu_data *)phy->dev->test.txbf_pfmu_data;
1385 pfmu_data = &pfmu_data[subc_id];
1386
1387 if (subc_id < 32)
developerb3cb52e2023-10-27 15:16:48 +08001388@@ -902,21 +969,21 @@ mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001389 pfmu_data->phi11 = cpu_to_le16(phi11);
1390 pfmu_data->phi21 = cpu_to_le16(phi21);
1391 pfmu_data->phi31 = cpu_to_le16(phi31);
1392- if (subc_id == 63) {
1393+ if (subc_id == MT7915_TXBF_SUBCAR_NUM - 1) {
1394 struct mt7915_dev *dev = phy->dev;
1395 struct {
1396 u8 format_id;
1397 u8 pfmu_idx;
1398 u8 dbdc_idx;
1399 u8 _rsv;
1400- u8 buf[512];
1401+ u8 buf[MT7915_TXBF_PFMU_DATA_LEN];
1402 } __packed req = {
1403 .format_id = MT_BF_PROFILE_WRITE_ALL,
1404 .pfmu_idx = pfmu_idx,
1405 .dbdc_idx = phy != &dev->phy,
1406 };
1407
1408- memcpy(req.buf, dev->test.txbf_pfmu_data, 512);
1409+ memcpy(req.buf, dev->test.txbf_pfmu_data, MT7915_TXBF_PFMU_DATA_LEN);
1410
1411 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION),
1412 &req, sizeof(req), true);
developerb3cb52e2023-10-27 15:16:48 +08001413@@ -928,7 +995,7 @@ mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
developer1346ce52022-12-15 21:36:14 +08001414 static int
1415 mt7915_tm_txbf_e2p_update(struct mt7915_phy *phy)
1416 {
1417- struct mt7915_tm_txbf_phase *phase, *p;
1418+ struct mt7915_txbf_phase *phase, *p;
1419 struct mt7915_dev *dev = phy->dev;
1420 u8 *eeprom = dev->mt76.eeprom.data;
1421 u16 offset;
developerb3cb52e2023-10-27 15:16:48 +08001422@@ -938,7 +1005,7 @@ mt7915_tm_txbf_e2p_update(struct mt7915_phy *phy)
developer1346ce52022-12-15 21:36:14 +08001423 is_7976 = mt7915_check_adie(dev, false) || is_mt7916(&dev->mt76);
1424 offset = is_7976 ? 0x60a : 0x651;
1425
1426- phase = (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1427+ phase = (struct mt7915_txbf_phase *)dev->test.txbf_phase_cal;
1428 for (i = 0; i < MAX_PHASE_GROUP_NUM; i++) {
1429 p = &phase[i];
1430
developerb3cb52e2023-10-27 15:16:48 +08001431@@ -953,17 +1020,75 @@ mt7915_tm_txbf_e2p_update(struct mt7915_phy *phy)
developer1346ce52022-12-15 21:36:14 +08001432 return 0;
1433 }
1434
1435+static int
1436+mt7915_tm_trigger_sounding(struct mt7915_phy *phy, u16 *val, bool en)
1437+{
1438+ struct mt7915_dev *dev = phy->dev;
1439+ u8 sounding_mode = val[0];
1440+ u8 MU_num = val[1];
1441+ u32 sounding_interval = (u32)val[2] << 2; /* input unit: 4ms */
1442+ enum sounding_mode {
1443+ SU_SOUNDING,
1444+ MU_SOUNDING,
1445+ SU_PERIODIC_SOUNDING,
1446+ MU_PERIODIC_SOUNDING,
1447+ BF_PROCESSING,
1448+ TXCMD_NONTB_SU_SOUNDING,
1449+ TXCMD_VHT_MU_SOUNDING,
1450+ TXCMD_TB_PER_BRP_SOUNDING,
1451+ TXCMD_TB_SOUNDING,
1452+
1453+ /* keep last */
1454+ NUM_SOUNDING_MODE,
1455+ SOUNDING_MODE_MAX = NUM_SOUNDING_MODE - 1,
1456+ };
1457+ struct {
1458+ u8 cmd_category_id;
1459+ u8 sounding_mode;
1460+ u8 MU_num;
1461+ u8 rsv;
1462+ u8 wlan_idx[4];
1463+ u32 sounding_interval; /* unit: ms */
1464+ } __packed req = {
1465+ .cmd_category_id = en ? MT_BF_SOUNDING_ON : MT_BF_SOUNDING_OFF,
1466+ .sounding_mode = sounding_mode,
1467+ .MU_num = MU_num,
1468+ .sounding_interval = cpu_to_le32(sounding_interval),
1469+ .wlan_idx[0] = val[3],
1470+ .wlan_idx[1] = val[4],
1471+ .wlan_idx[2] = val[5],
1472+ .wlan_idx[3] = val[6],
1473+ };
1474+
1475+ if (sounding_mode > SOUNDING_MODE_MAX)
1476+ return -EINVAL;
1477+
1478+ /* Enable Tx MAC HW before trigger sounding */
1479+ if (en)
1480+ mt7915_tm_set_trx(phy, TM_MAC_TX, true);
1481+
1482+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION),
1483+ &req, sizeof(req), true);
1484+}
1485+
1486 static int
1487 mt7915_tm_set_txbf(struct mt7915_phy *phy)
1488 {
1489+#define TXBF_IS_DUT_MASK BIT(0)
1490+#define TXBF_EBF_MASK BIT(1)
1491 struct mt76_testmode_data *td = &phy->mt76->test;
1492 u16 *val = td->txbf_param;
1493
1494- pr_info("ibf cal process: act = %u, val = %u, %u, %u, %u, %u, %u\n",
1495- td->txbf_act, val[0], val[1], val[2], val[3], val[4], val[5]);
developer62b3f572023-06-07 17:39:27 +08001496+ dev_info(phy->dev->mt76.dev, "ibf cal process: act = %u, val = %u, %u, %u, %u, %u, %u, %u\n",
developer1346ce52022-12-15 21:36:14 +08001497+ td->txbf_act, val[0], val[1], val[2], val[3], val[4], val[5], val[6]);
1498
1499 switch (td->txbf_act) {
1500+ case MT76_TM_TXBF_ACT_GOLDEN_INIT:
1501 case MT76_TM_TXBF_ACT_INIT:
1502+ case MT76_TM_TX_EBF_ACT_GOLDEN_INIT:
1503+ case MT76_TM_TX_EBF_ACT_INIT:
1504+ td->ebf = !!u32_get_bits(td->txbf_act, TXBF_EBF_MASK);
1505+ td->is_txbf_dut = !!u32_get_bits(td->txbf_act, TXBF_IS_DUT_MASK);
1506 return mt7915_tm_txbf_init(phy, val);
1507 case MT76_TM_TXBF_ACT_UPDATE_CH:
1508 mt7915_tm_update_channel(phy);
developerb3cb52e2023-10-27 15:16:48 +08001509@@ -989,6 +1114,36 @@ mt7915_tm_set_txbf(struct mt7915_phy *phy)
developer1346ce52022-12-15 21:36:14 +08001510
1511 return mt7915_tm_txbf_apply_tx(phy, wlan_idx, ebf, ibf, phase_cal);
1512 }
1513+ case MT76_TM_TXBF_ACT_TRIGGER_SOUNDING:
1514+ return mt7915_tm_trigger_sounding(phy, val, true);
1515+ case MT76_TM_TXBF_ACT_STOP_SOUNDING:
1516+ memset(val, 0, sizeof(td->txbf_param));
1517+ return mt7915_tm_trigger_sounding(phy, val, false);
1518+ case MT76_TM_TXBF_ACT_PROFILE_TAG_READ:
1519+ case MT76_TM_TXBF_ACT_PROFILE_TAG_WRITE:
1520+ case MT76_TM_TXBF_ACT_PROFILE_TAG_INVALID: {
1521+ u8 pfmu_idx = val[0];
1522+ bool bfer = !!val[1];
1523+ struct mt7915_dev *dev = phy->dev;
1524+ struct mt7915_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
1525+
1526+ if (!tag) {
1527+ dev_err(dev->mt76.dev,
1528+ "pfmu tag is not initialized!\n");
1529+ return 0;
1530+ }
1531+
1532+ if (td->txbf_act == MT76_TM_TXBF_ACT_PROFILE_TAG_WRITE)
1533+ return mt7915_tm_txbf_profile_tag_write(phy, pfmu_idx, tag);
1534+ else if (td->txbf_act == MT76_TM_TXBF_ACT_PROFILE_TAG_READ)
1535+ return mt7915_mcu_txbf_profile_tag_read(phy, pfmu_idx, bfer);
1536+
1537+ tag->t1.invalid_prof = !!val[0];
1538+
1539+ return 0;
1540+ }
1541+ case MT76_TM_TXBF_ACT_STA_REC_READ:
1542+ return mt7915_mcu_txbf_sta_rec_read(phy->dev, val[0]);
1543 default:
1544 break;
1545 };
developerb3cb52e2023-10-27 15:16:48 +08001546@@ -1264,9 +1419,10 @@ mt7915_tm_set_ipi(struct mt7915_phy *phy)
developer1346ce52022-12-15 21:36:14 +08001547
1548 static int
1549 mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
1550- u16 cw_max, u16 txop, u8 tx_cmd)
1551+ u16 cw_max, u16 txop, u8 tx_cmd, bool bf_sounding)
1552 {
1553- struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv;
1554+ struct mt76_testmode_data *td = &phy->mt76->test;
1555+ struct mt7915_vif *mvif;
1556 struct mt7915_mcu_tx req = {
1557 .valid = true,
1558 .mode = tx_cmd,
developerb3cb52e2023-10-27 15:16:48 +08001559@@ -1274,6 +1430,9 @@ mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
developer1346ce52022-12-15 21:36:14 +08001560 };
1561 struct edca *e = &req.edca[0];
1562
1563+ mvif = bf_sounding ? (struct mt7915_vif *)td->second_vif->drv_priv :
1564+ (struct mt7915_vif *)phy->monitor_vif->drv_priv;
1565+
1566 e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS;
1567 e->set = WMM_PARAM_SET;
1568
developerb3cb52e2023-10-27 15:16:48 +08001569@@ -1286,17 +1445,19 @@ mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
developer1346ce52022-12-15 21:36:14 +08001570 }
1571
1572 static int
1573-mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode)
1574+mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode, bool bf_sounding)
1575 {
1576 #define TM_DEFAULT_SIFS 10
1577 #define TM_MAX_SIFS 127
1578 #define TM_MAX_AIFSN 0xf
1579 #define TM_MIN_AIFSN 0x1
1580 #define BBP_PROC_TIME 1500
1581+#define TM_DEFAULT_CW 1
1582 struct mt7915_dev *dev = phy->dev;
1583 u8 sig_ext = (mode == MT76_TM_TX_MODE_CCK) ? 0 : 6;
1584 u8 slot_time = 9, sifs = TM_DEFAULT_SIFS;
1585 u8 aifsn = TM_MIN_AIFSN;
1586+ bool tx_cmd;
1587 u8 band = phy->mt76->band_idx;
1588 u32 i2t_time, tr2t_time, txv_time;
1589 u16 cw = 0;
developerb3cb52e2023-10-27 15:16:48 +08001590@@ -1310,6 +1471,7 @@ mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode)
developer1346ce52022-12-15 21:36:14 +08001591 ipg -= sig_ext;
1592
1593 if (ipg <= (TM_MAX_SIFS + slot_time)) {
1594+ cw = TM_DEFAULT_CW;
1595 sifs = ipg - slot_time;
1596 } else {
1597 u32 val = (ipg + slot_time) / slot_time;
developerb3cb52e2023-10-27 15:16:48 +08001598@@ -1345,10 +1507,12 @@ done:
developer1346ce52022-12-15 21:36:14 +08001599
1600 mt7915_tm_set_slot_time(phy, slot_time, sifs);
1601
1602+ /* HE MU data and iBF/eBF sounding packet use TXCMD */
1603+ tx_cmd = (mode == MT76_TM_TX_MODE_HE_MU) || bf_sounding;
1604+
1605 return mt7915_tm_set_wmm_qid(phy,
1606 mt76_connac_lmac_mapping(IEEE80211_AC_BE),
1607- aifsn, cw, cw, 0,
1608- mode == MT76_TM_TX_MODE_HE_MU);
1609+ aifsn, cw, cw, 0, tx_cmd, bf_sounding);
1610 }
1611
1612 static int
developerb3cb52e2023-10-27 15:16:48 +08001613@@ -1547,7 +1711,7 @@ mt7915_tm_init(struct mt7915_phy *phy, bool en)
developer1346ce52022-12-15 21:36:14 +08001614
1615 phy->mt76->test.aid = 0;
1616 phy->mt76->test.tx_mpdu_len = 0;
1617- phy->test.bf_en = 0;
1618+ phy->mt76->test.bf_en = 0;
1619 mt7915_tm_set_entry(phy);
1620 } else {
1621 INIT_DELAYED_WORK(&phy->ipi_work, mt7915_tm_ipi_work);
developerb3cb52e2023-10-27 15:16:48 +08001622@@ -1732,7 +1896,7 @@ mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
developer1346ce52022-12-15 21:36:14 +08001623 u32 tx_time = td->tx_time, ipg = td->tx_ipg;
1624 u8 duty_cycle = td->tx_duty_cycle;
1625
1626- if (!phy->test.bf_en)
1627+ if (!td->bf_en)
1628 mt7915_tm_update_channel(phy);
1629
1630 if (td->tx_spe_idx)
developerb3cb52e2023-10-27 15:16:48 +08001631@@ -1747,7 +1911,7 @@ mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
developer1346ce52022-12-15 21:36:14 +08001632 if (duty_cycle < 100)
1633 tx_time = duty_cycle * ipg / (100 - duty_cycle);
1634 }
1635- mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
1636+ mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode, false);
1637 mt7915_tm_set_tx_len(phy, tx_time);
1638
1639 if (ipg)
developerb3cb52e2023-10-27 15:16:48 +08001640@@ -1766,6 +1930,9 @@ mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
developer1346ce52022-12-15 21:36:14 +08001641 mt7915_tm_tx_frames_mu(phy, en);
1642
1643 mt7915_tm_set_trx(phy, TM_MAC_TX, en);
1644+
1645+ if (td->bf_en)
1646+ mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1647 }
1648
1649 static int
developerb3cb52e2023-10-27 15:16:48 +08001650@@ -1857,7 +2024,7 @@ mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
developer1346ce52022-12-15 21:36:14 +08001651 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1652
1653 if (en) {
1654- if (!phy->test.bf_en)
1655+ if (!td->bf_en || !td->is_txbf_dut)
1656 mt7915_tm_update_channel(phy);
1657 if (td->aid)
1658 mt7915_tm_set_rx_user_idx(phy, td->aid);
developerb3cb52e2023-10-27 15:16:48 +08001659@@ -1874,6 +2041,9 @@ mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
developer1346ce52022-12-15 21:36:14 +08001660 mt7915_tm_set_muru_aid(phy, en ? td->aid : 0xf800);
1661
1662 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1663+
1664+ if (td->bf_en)
1665+ mt7915_tm_set_trx(phy, TM_MAC_TX, en);
1666 }
1667
1668 static int
developerb3cb52e2023-10-27 15:16:48 +08001669@@ -1933,34 +2103,7 @@ mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en)
developer1346ce52022-12-15 21:36:14 +08001670 rate_idx = sband->bitrates[idx].hw_value & 0xff;
1671 }
1672
1673- switch (td->tx_rate_mode) {
1674- case MT76_TM_TX_MODE_CCK:
1675- mode = MT_PHY_TYPE_CCK;
1676- break;
1677- case MT76_TM_TX_MODE_OFDM:
1678- mode = MT_PHY_TYPE_OFDM;
1679- break;
1680- case MT76_TM_TX_MODE_HT:
1681- mode = MT_PHY_TYPE_HT;
1682- break;
1683- case MT76_TM_TX_MODE_VHT:
1684- mode = MT_PHY_TYPE_VHT;
1685- break;
1686- case MT76_TM_TX_MODE_HE_SU:
1687- mode = MT_PHY_TYPE_HE_SU;
1688- break;
1689- case MT76_TM_TX_MODE_HE_EXT_SU:
1690- mode = MT_PHY_TYPE_HE_EXT_SU;
1691- break;
1692- case MT76_TM_TX_MODE_HE_TB:
1693- mode = MT_PHY_TYPE_HE_TB;
1694- break;
1695- case MT76_TM_TX_MODE_HE_MU:
1696- mode = MT_PHY_TYPE_HE_MU;
1697- break;
1698- default:
1699- return -EINVAL;
1700- }
1701+ mode = mt7915_tm_rate_to_phy(td->tx_rate_mode);
1702
1703 rateval = mode << 6 | rate_idx;
1704 tx_cont->rateval = cpu_to_le16(rateval);
1705diff --git a/mt7915/testmode.h b/mt7915/testmode.h
developere8045132023-08-04 14:40:12 +08001706index 7569826..5aba13c 100644
developer1346ce52022-12-15 21:36:14 +08001707--- a/mt7915/testmode.h
1708+++ b/mt7915/testmode.h
1709@@ -311,137 +311,7 @@ struct mt7915_tm_muru {
1710
1711 #define MAX_PHASE_GROUP_NUM 9
1712
1713-struct mt7915_tm_txbf_phase {
1714- u8 status;
1715- struct {
1716- u8 r0_uh;
1717- u8 r0_h;
1718- u8 r0_m;
1719- u8 r0_l;
1720- u8 r0_ul;
1721- u8 r1_uh;
1722- u8 r1_h;
1723- u8 r1_m;
1724- u8 r1_l;
1725- u8 r1_ul;
1726- u8 r2_uh;
1727- u8 r2_h;
1728- u8 r2_m;
1729- u8 r2_l;
1730- u8 r2_ul;
1731- u8 r3_uh;
1732- u8 r3_h;
1733- u8 r3_m;
1734- u8 r3_l;
1735- u8 r3_ul;
1736- u8 r2_uh_sx2;
1737- u8 r2_h_sx2;
1738- u8 r2_m_sx2;
1739- u8 r2_l_sx2;
1740- u8 r2_ul_sx2;
1741- u8 r3_uh_sx2;
1742- u8 r3_h_sx2;
1743- u8 r3_m_sx2;
1744- u8 r3_l_sx2;
1745- u8 r3_ul_sx2;
1746- u8 m_t0_h;
1747- u8 m_t1_h;
1748- u8 m_t2_h;
1749- u8 m_t2_h_sx2;
1750- u8 r0_reserved;
1751- u8 r1_reserved;
1752- u8 r2_reserved;
1753- u8 r3_reserved;
1754- u8 r2_sx2_reserved;
1755- u8 r3_sx2_reserved;
1756- } phase;
1757-};
1758-
1759-struct mt7915_tm_pfmu_tag1 {
1760- __le32 pfmu_idx:10;
1761- __le32 ebf:1;
1762- __le32 data_bw:2;
1763- __le32 lm:2;
1764- __le32 is_mu:1;
1765- __le32 nr:3, nc:3;
1766- __le32 codebook:2;
1767- __le32 ngroup:2;
1768- __le32 _rsv:2;
1769- __le32 invalid_prof:1;
1770- __le32 rmsd:3;
1771-
1772- __le32 col_id1:6, row_id1:10;
1773- __le32 col_id2:6, row_id2:10;
1774- __le32 col_id3:6, row_id3:10;
1775- __le32 col_id4:6, row_id4:10;
1776-
1777- __le32 ru_start_id:7;
1778- __le32 _rsv1:1;
1779- __le32 ru_end_id:7;
1780- __le32 _rsv2:1;
1781- __le32 mob_cal_en:1;
1782- __le32 _rsv3:15;
1783-
1784- __le32 snr_sts0:8, snr_sts1:8, snr_sts2:8, snr_sts3:8;
1785- __le32 snr_sts4:8, snr_sts5:8, snr_sts6:8, snr_sts7:8;
1786-
1787- __le32 _rsv4;
1788-} __packed;
1789-
1790-struct mt7915_tm_pfmu_tag2 {
1791- __le32 smart_ant:24;
1792- __le32 se_idx:5;
1793- __le32 _rsv:3;
1794-
1795- __le32 _rsv1:8;
1796- __le32 rmsd_thres:3;
1797- __le32 _rsv2:5;
1798- __le32 ibf_timeout:8;
1799- __le32 _rsv3:8;
1800-
1801- __le32 _rsv4:16;
1802- __le32 ibf_data_bw:2;
1803- __le32 ibf_nc:3;
1804- __le32 ibf_nr:3;
1805- __le32 ibf_ru:8;
1806-
1807- __le32 mob_delta_t:8;
1808- __le32 mob_lq_result:7;
1809- __le32 _rsv5:1;
1810- __le32 _rsv6:16;
1811-
1812- __le32 _rsv7;
1813-} __packed;
1814-
1815-struct mt7915_tm_pfmu_tag {
1816- struct mt7915_tm_pfmu_tag1 t1;
1817- struct mt7915_tm_pfmu_tag2 t2;
1818-};
1819-
1820-struct mt7915_tm_pfmu_data {
1821- __le16 subc_idx;
1822- __le16 phi11;
1823- __le16 phi21;
1824- __le16 phi31;
1825-};
1826-
1827-struct mt7915_tm_ibf_cal_info {
1828- u8 format_id;
1829- u8 group_l_m_n;
1830- u8 group;
1831- bool sx2;
1832- u8 status;
1833- u8 cal_type;
1834- u8 _rsv[2];
1835- u8 buf[1000];
1836-} __packed;
1837-
1838-enum {
1839- IBF_PHASE_CAL_UNSPEC,
1840- IBF_PHASE_CAL_NORMAL,
1841- IBF_PHASE_CAL_VERIFY,
1842- IBF_PHASE_CAL_NORMAL_INSTRUMENT,
1843- IBF_PHASE_CAL_VERIFY_INSTRUMENT,
1844-};
1845+#define TXBF_DUT_MAC_SUBADDR 0x22
1846+#define TXBF_GOLDEN_MAC_SUBADDR 0x11
1847
1848 #endif
1849diff --git a/testmode.c b/testmode.c
developerb3cb52e2023-10-27 15:16:48 +08001850index 4c22dfc..410c7ab 100644
developer1346ce52022-12-15 21:36:14 +08001851--- a/testmode.c
1852+++ b/testmode.c
developerb3cb52e2023-10-27 15:16:48 +08001853@@ -196,6 +196,7 @@ mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len,
developer1346ce52022-12-15 21:36:14 +08001854
1855 hdr = __skb_put_zero(head, sizeof(*hdr));
1856 hdr->frame_control = cpu_to_le16(fc);
1857+
1858 memcpy(hdr->addr1, addr[0], ETH_ALEN);
1859 memcpy(hdr->addr2, addr[1], ETH_ALEN);
1860 memcpy(hdr->addr3, addr[2], ETH_ALEN);
1861diff --git a/testmode.h b/testmode.h
developerb3cb52e2023-10-27 15:16:48 +08001862index b39cf51..20fab3e 100644
developer1346ce52022-12-15 21:36:14 +08001863--- a/testmode.h
1864+++ b/testmode.h
developerb3cb52e2023-10-27 15:16:48 +08001865@@ -303,7 +303,10 @@ enum mt76_testmode_cfg {
developer1346ce52022-12-15 21:36:14 +08001866 };
1867
1868 enum mt76_testmode_txbf_act {
1869+ MT76_TM_TXBF_ACT_GOLDEN_INIT,
1870 MT76_TM_TXBF_ACT_INIT,
1871+ MT76_TM_TX_EBF_ACT_GOLDEN_INIT,
1872+ MT76_TM_TX_EBF_ACT_INIT,
1873 MT76_TM_TXBF_ACT_UPDATE_CH,
1874 MT76_TM_TXBF_ACT_PHASE_COMP,
1875 MT76_TM_TXBF_ACT_TX_PREP,
developerb3cb52e2023-10-27 15:16:48 +08001876@@ -314,6 +317,12 @@ enum mt76_testmode_txbf_act {
developer1346ce52022-12-15 21:36:14 +08001877 MT76_TM_TXBF_ACT_PROF_UPDATE_ALL,
1878 MT76_TM_TXBF_ACT_PROF_UPDATE_ALL_CMD,
1879 MT76_TM_TXBF_ACT_E2P_UPDATE,
1880+ MT76_TM_TXBF_ACT_TRIGGER_SOUNDING,
1881+ MT76_TM_TXBF_ACT_STOP_SOUNDING,
1882+ MT76_TM_TXBF_ACT_PROFILE_TAG_READ,
1883+ MT76_TM_TXBF_ACT_PROFILE_TAG_WRITE,
1884+ MT76_TM_TXBF_ACT_PROFILE_TAG_INVALID,
1885+ MT76_TM_TXBF_ACT_STA_REC_READ,
1886
1887 /* keep last */
1888 NUM_MT76_TM_TXBF_ACT,
1889diff --git a/tools/fields.c b/tools/fields.c
developerb3cb52e2023-10-27 15:16:48 +08001890index e2cf4b9..027b8cd 100644
developer1346ce52022-12-15 21:36:14 +08001891--- a/tools/fields.c
1892+++ b/tools/fields.c
1893@@ -33,7 +33,10 @@ static const char * const testmode_tx_mode[] = {
1894 };
1895
1896 static const char * const testmode_txbf_act[] = {
1897+ [MT76_TM_TXBF_ACT_GOLDEN_INIT] = "golden_init",
1898 [MT76_TM_TXBF_ACT_INIT] = "init",
1899+ [MT76_TM_TX_EBF_ACT_GOLDEN_INIT] = "ebf_golden_init",
1900+ [MT76_TM_TX_EBF_ACT_INIT] = "ebf_init",
1901 [MT76_TM_TXBF_ACT_UPDATE_CH] = "update_ch",
1902 [MT76_TM_TXBF_ACT_PHASE_COMP] = "phase_comp",
1903 [MT76_TM_TXBF_ACT_TX_PREP] = "tx_prep",
1904@@ -44,6 +47,12 @@ static const char * const testmode_txbf_act[] = {
1905 [MT76_TM_TXBF_ACT_PROF_UPDATE_ALL] = "prof_update",
1906 [MT76_TM_TXBF_ACT_PROF_UPDATE_ALL_CMD] = "prof_update_all",
1907 [MT76_TM_TXBF_ACT_E2P_UPDATE] = "e2p_update",
1908+ [MT76_TM_TXBF_ACT_TRIGGER_SOUNDING] = "trigger_sounding",
1909+ [MT76_TM_TXBF_ACT_STOP_SOUNDING] = "stop_sounding",
1910+ [MT76_TM_TXBF_ACT_PROFILE_TAG_READ] = "pfmu_tag_read",
1911+ [MT76_TM_TXBF_ACT_PROFILE_TAG_WRITE] = "pfmu_tag_write",
1912+ [MT76_TM_TXBF_ACT_PROFILE_TAG_INVALID] = "set_invalid_prof",
1913+ [MT76_TM_TXBF_ACT_STA_REC_READ] = "sta_rec_read",
1914 };
1915
1916 static const char * const testmode_offchan_bw[] = {
1917--
developere8045132023-08-04 14:40:12 +080019182.18.0
developer1346ce52022-12-15 21:36:14 +08001919