developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988 GSW 10G SPIM-NAND 4PCIe RFB"; |
| 12 | compatible = "mediatek,mt7988a-gsw-10g-spim-snand-4pcie", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | pci=pcie_bus_perf"; |
| 20 | }; |
| 21 | |
| 22 | gsw: gsw@0 { |
| 23 | compatible = "mediatek,mt753x"; |
| 24 | mediatek,sysctrl = <ðwarp>; |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
| 27 | }; |
| 28 | |
| 29 | memory { |
| 30 | reg = <0 0x40000000 0 0x10000000>; |
| 31 | }; |
| 32 | |
| 33 | nmbm_spim_nand { |
| 34 | compatible = "generic,nmbm"; |
| 35 | |
| 36 | #address-cells = <1>; |
| 37 | #size-cells = <1>; |
| 38 | |
| 39 | lower-mtd-device = <&spi_nand>; |
| 40 | forced-create; |
| 41 | |
| 42 | partitions { |
| 43 | compatible = "fixed-partitions"; |
| 44 | #address-cells = <1>; |
| 45 | #size-cells = <1>; |
| 46 | |
| 47 | partition@0 { |
| 48 | label = "BL2"; |
| 49 | reg = <0x00000 0x0100000>; |
| 50 | read-only; |
| 51 | }; |
| 52 | |
| 53 | partition@100000 { |
| 54 | label = "u-boot-env"; |
| 55 | reg = <0x0100000 0x0080000>; |
| 56 | }; |
| 57 | |
| 58 | factory: partition@180000 { |
| 59 | label = "Factory"; |
| 60 | reg = <0x180000 0x0400000>; |
| 61 | }; |
| 62 | |
| 63 | partition@580000 { |
| 64 | label = "FIP"; |
| 65 | reg = <0x580000 0x0200000>; |
| 66 | }; |
| 67 | |
| 68 | partition@780000 { |
| 69 | label = "ubi"; |
developer | baa8f60 | 2022-12-07 17:07:51 +0800 | [diff] [blame] | 70 | reg = <0x780000 0x7080000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 71 | }; |
| 72 | }; |
| 73 | }; |
| 74 | |
| 75 | wsys_adie: wsys_adie@0 { |
| 76 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 77 | compatible = "mediatek,rebb-mt7988-adie"; |
| 78 | adie_id = <7976>; |
| 79 | sku_type = <3000>; |
| 80 | }; |
| 81 | }; |
| 82 | |
| 83 | &fan { |
| 84 | pwms = <&pwm 0 50000 0>; |
| 85 | status = "okay"; |
| 86 | }; |
| 87 | |
| 88 | &i2c0 { |
| 89 | pinctrl-names = "default"; |
| 90 | pinctrl-0 = <&i2c0_pins>; |
| 91 | status = "okay"; |
| 92 | |
| 93 | rt5190a_64: rt5190a@64 { |
| 94 | compatible = "richtek,rt5190a"; |
| 95 | reg = <0x64>; |
| 96 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 97 | vin2-supply = <&rt5190_buck1>; |
| 98 | vin3-supply = <&rt5190_buck1>; |
| 99 | vin4-supply = <&rt5190_buck1>; |
| 100 | |
| 101 | regulators { |
| 102 | rt5190_buck1: buck1 { |
| 103 | regulator-name = "rt5190a-buck1"; |
| 104 | regulator-min-microvolt = <5090000>; |
| 105 | regulator-max-microvolt = <5090000>; |
| 106 | regulator-allowed-modes = |
| 107 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 108 | regulator-boot-on; |
| 109 | }; |
| 110 | buck2 { |
| 111 | regulator-name = "vcore"; |
| 112 | regulator-min-microvolt = <600000>; |
| 113 | regulator-max-microvolt = <1400000>; |
| 114 | regulator-boot-on; |
| 115 | }; |
| 116 | buck3 { |
| 117 | regulator-name = "proc"; |
| 118 | regulator-min-microvolt = <600000>; |
| 119 | regulator-max-microvolt = <1400000>; |
| 120 | regulator-boot-on; |
| 121 | }; |
| 122 | buck4 { |
| 123 | regulator-name = "rt5190a-buck4"; |
| 124 | regulator-min-microvolt = <850000>; |
| 125 | regulator-max-microvolt = <850000>; |
| 126 | regulator-allowed-modes = |
| 127 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 128 | regulator-boot-on; |
| 129 | }; |
| 130 | ldo { |
| 131 | regulator-name = "rt5190a-ldo"; |
| 132 | regulator-min-microvolt = <1200000>; |
| 133 | regulator-max-microvolt = <1200000>; |
| 134 | regulator-boot-on; |
| 135 | }; |
| 136 | }; |
| 137 | }; |
| 138 | }; |
| 139 | |
| 140 | &i2c1 { |
| 141 | pinctrl-names = "default"; |
| 142 | pinctrl-0 = <&i2c1_pins>; |
| 143 | status = "okay"; |
| 144 | }; |
| 145 | |
| 146 | &pwm { |
| 147 | status = "okay"; |
| 148 | }; |
| 149 | |
| 150 | &uart0 { |
| 151 | status = "okay"; |
| 152 | }; |
| 153 | |
| 154 | &spi0 { |
| 155 | pinctrl-names = "default"; |
| 156 | pinctrl-0 = <&spi0_flash_pins>; |
| 157 | status = "okay"; |
| 158 | |
| 159 | spi_nand: spi_nand@0 { |
| 160 | #address-cells = <1>; |
| 161 | #size-cells = <1>; |
| 162 | compatible = "spi-nand"; |
| 163 | spi-cal-enable; |
| 164 | spi-cal-mode = "read-data"; |
| 165 | spi-cal-datalen = <7>; |
| 166 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 167 | spi-cal-addrlen = <5>; |
| 168 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 169 | reg = <0>; |
| 170 | spi-max-frequency = <52000000>; |
developer | 5fb8060 | 2023-05-02 18:54:53 +0800 | [diff] [blame] | 171 | spi-tx-bus-width = <4>; |
| 172 | spi-rx-bus-width = <4>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 173 | }; |
| 174 | }; |
| 175 | |
| 176 | &spi1 { |
| 177 | pinctrl-names = "default"; |
| 178 | /* pin shared with snfi */ |
| 179 | pinctrl-0 = <&spic_pins>; |
| 180 | status = "disabled"; |
| 181 | }; |
| 182 | |
| 183 | &pcie0 { |
| 184 | pinctrl-names = "default"; |
| 185 | pinctrl-0 = <&pcie0_pins>; |
| 186 | status = "okay"; |
| 187 | }; |
| 188 | |
| 189 | &pcie1 { |
| 190 | pinctrl-names = "default"; |
| 191 | pinctrl-0 = <&pcie1_pins>; |
| 192 | status = "okay"; |
| 193 | }; |
| 194 | |
| 195 | &pcie2 { |
| 196 | pinctrl-names = "default"; |
| 197 | pinctrl-0 = <&pcie2_pins>; |
| 198 | status = "okay"; |
| 199 | }; |
| 200 | |
| 201 | &pcie3 { |
| 202 | pinctrl-names = "default"; |
| 203 | pinctrl-0 = <&pcie3_pins>; |
| 204 | status = "okay"; |
| 205 | }; |
| 206 | |
| 207 | &pio { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 208 | mdio0_pins: mdio0-pins { |
| 209 | mux { |
| 210 | function = "mdio"; |
| 211 | groups = "mdc_mdio0"; |
| 212 | }; |
| 213 | |
| 214 | conf { |
| 215 | groups = "mdc_mdio0"; |
| 216 | drive-strength = <MTK_DRIVE_8mA>; |
| 217 | }; |
| 218 | }; |
| 219 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 220 | gbe0_led0_pins: gbe0-pins { |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 221 | mux { |
| 222 | function = "led"; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 223 | groups = "gbe0_led0"; |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 224 | }; |
| 225 | }; |
| 226 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 227 | gbe1_led0_pins: gbe1-pins { |
| 228 | mux { |
| 229 | function = "led"; |
| 230 | groups = "gbe1_led0"; |
| 231 | }; |
| 232 | }; |
| 233 | |
| 234 | gbe2_led0_pins: gbe2-pins { |
| 235 | mux { |
| 236 | function = "led"; |
| 237 | groups = "gbe2_led0"; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | gbe3_led0_pins: gbe3-pins { |
| 242 | mux { |
| 243 | function = "led"; |
| 244 | groups = "gbe3_led0"; |
| 245 | }; |
| 246 | }; |
| 247 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 248 | i2c0_pins: i2c0-pins-g0 { |
| 249 | mux { |
| 250 | function = "i2c"; |
| 251 | groups = "i2c0_1"; |
| 252 | }; |
| 253 | }; |
| 254 | |
| 255 | i2c1_pins: i2c1-pins-g0 { |
| 256 | mux { |
| 257 | function = "i2c"; |
| 258 | groups = "i2c1_0"; |
| 259 | }; |
| 260 | }; |
| 261 | |
| 262 | pcie0_pins: pcie0-pins { |
| 263 | mux { |
| 264 | function = "pcie"; |
| 265 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 266 | "pcie_wake_n0_0"; |
| 267 | }; |
| 268 | }; |
| 269 | |
| 270 | pcie1_pins: pcie1-pins { |
| 271 | mux { |
| 272 | function = "pcie"; |
| 273 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 274 | "pcie_wake_n1_0"; |
| 275 | }; |
| 276 | }; |
| 277 | |
| 278 | pcie2_pins: pcie2-pins { |
| 279 | mux { |
| 280 | function = "pcie"; |
| 281 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 282 | "pcie_wake_n2_0"; |
| 283 | }; |
| 284 | }; |
| 285 | |
| 286 | pcie3_pins: pcie3-pins { |
| 287 | mux { |
| 288 | function = "pcie"; |
| 289 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 290 | "pcie_wake_n3_0"; |
| 291 | }; |
| 292 | }; |
| 293 | |
| 294 | spi0_flash_pins: spi0-pins { |
| 295 | mux { |
| 296 | function = "spi"; |
| 297 | groups = "spi0", "spi0_wp_hold"; |
| 298 | }; |
| 299 | }; |
| 300 | |
| 301 | spic_pins: spi1-pins { |
| 302 | mux { |
| 303 | function = "spi"; |
developer | 1ceb26a | 2023-02-16 15:43:43 +0800 | [diff] [blame] | 304 | groups = "spi1"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 305 | }; |
| 306 | }; |
| 307 | }; |
| 308 | |
| 309 | &watchdog { |
| 310 | status = "disabled"; |
| 311 | }; |
| 312 | |
| 313 | &xhci0 { |
| 314 | status = "disabled"; |
| 315 | }; |
| 316 | |
| 317 | ð { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 318 | pinctrl-names = "default"; |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 319 | pinctrl-0 = <&mdio0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 320 | status = "okay"; |
| 321 | |
| 322 | gmac0: mac@0 { |
| 323 | compatible = "mediatek,eth-mac"; |
| 324 | reg = <0>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 325 | mac-type = "xgdm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 326 | phy-mode = "10gbase-kr"; |
| 327 | |
| 328 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 329 | speed = <10000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 330 | full-duplex; |
| 331 | pause; |
| 332 | }; |
| 333 | }; |
| 334 | |
| 335 | gmac1: mac@1 { |
| 336 | compatible = "mediatek,eth-mac"; |
| 337 | reg = <1>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 338 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 339 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 340 | phy-handle = <&phy0>; |
| 341 | }; |
| 342 | |
| 343 | gmac2: mac@2 { |
| 344 | compatible = "mediatek,eth-mac"; |
| 345 | reg = <2>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 346 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 347 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 348 | phy-handle = <&phy1>; |
| 349 | }; |
| 350 | |
| 351 | mdio: mdio-bus { |
| 352 | #address-cells = <1>; |
| 353 | #size-cells = <0>; |
developer | c4d8da7 | 2023-03-16 14:37:28 +0800 | [diff] [blame] | 354 | clock-frequency = <10500000>; |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 355 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 356 | phy0: ethernet-phy@0 { |
| 357 | reg = <0>; |
| 358 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 359 | reset-gpios = <&pio 72 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 360 | reset-assert-us = <100000>; |
| 361 | reset-deassert-us = <221000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 362 | }; |
| 363 | |
| 364 | phy1: ethernet-phy@8 { |
| 365 | reg = <8>; |
| 366 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 367 | reset-gpios = <&pio 71 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 368 | reset-assert-us = <100000>; |
| 369 | reset-deassert-us = <221000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 370 | }; |
| 371 | }; |
| 372 | }; |
| 373 | |
| 374 | &hnat { |
| 375 | mtketh-wan = "eth1"; |
| 376 | mtketh-lan = "eth0"; |
| 377 | mtketh-lan2 = "eth2"; |
| 378 | mtketh-max-gmac = <3>; |
| 379 | status = "okay"; |
| 380 | }; |
| 381 | |
| 382 | &gsw { |
| 383 | mediatek,mdio = <&mdio>; |
| 384 | mediatek,portmap = "llllw"; |
| 385 | mediatek,mdio_master_pinmux = <1>; |
| 386 | interrupt-parent = <&gic>; |
| 387 | interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
| 388 | status = "okay"; |
| 389 | |
| 390 | port6: port@6 { |
| 391 | compatible = "mediatek,mt753x-port"; |
| 392 | mediatek,ssc-on; |
| 393 | phy-mode = "10gbase-kr"; |
| 394 | reg = <6>; |
| 395 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 396 | speed = <10000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 397 | full-duplex; |
| 398 | }; |
| 399 | }; |
| 400 | |
| 401 | mdio1: mdio-bus { |
| 402 | #address-cells = <1>; |
| 403 | #size-cells = <0>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 404 | |
| 405 | gsw_phy0: ethernet-phy@0 { |
| 406 | compatible = "ethernet-phy-id03a2.9481"; |
| 407 | reg = <0>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 408 | pinctrl-names = "gbe-led"; |
| 409 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 410 | nvmem-cells = <&phy_calibration_p0>; |
| 411 | nvmem-cell-names = "phy-cal-data"; |
| 412 | }; |
| 413 | |
| 414 | gsw_phy1: ethernet-phy@1 { |
| 415 | compatible = "ethernet-phy-id03a2.9481"; |
| 416 | reg = <1>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 417 | pinctrl-names = "gbe-led"; |
| 418 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 419 | nvmem-cells = <&phy_calibration_p1>; |
| 420 | nvmem-cell-names = "phy-cal-data"; |
| 421 | }; |
| 422 | |
| 423 | gsw_phy2: ethernet-phy@2 { |
| 424 | compatible = "ethernet-phy-id03a2.9481"; |
| 425 | reg = <2>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 426 | pinctrl-names = "gbe-led"; |
| 427 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 428 | nvmem-cells = <&phy_calibration_p2>; |
| 429 | nvmem-cell-names = "phy-cal-data"; |
| 430 | }; |
| 431 | |
| 432 | gsw_phy3: ethernet-phy@3 { |
| 433 | compatible = "ethernet-phy-id03a2.9481"; |
| 434 | reg = <3>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 435 | pinctrl-names = "gbe-led"; |
| 436 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 437 | nvmem-cells = <&phy_calibration_p3>; |
| 438 | nvmem-cell-names = "phy-cal-data"; |
| 439 | }; |
| 440 | }; |
| 441 | }; |