[][kernel][mt7988][eth][mediatek-ge-soc: arm64: dts: Change GbE LED pin group to new separate ones]
[Description]
Change GbE pin groups to new separate ones, which are fixed by CL:7402754.
Without this patch, mediatek-ge-soc phy driver can't setup LED correctly.
[Release-log]
N/A
Change-Id: I4c2a14ed9e4fbc472d0d9d5ba6ba2a09c785a0d4
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7499794
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts
index b0e3d1b..5969966 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-gsw-10g-spim-nand-4pcie.dts
@@ -217,13 +217,34 @@
};
};
- gbe_led0_pins: gbe-pins {
+ gbe0_led0_pins: gbe0-pins {
mux {
function = "led";
- groups = "gbe_led0";
+ groups = "gbe0_led0";
};
};
+ gbe1_led0_pins: gbe1-pins {
+ mux {
+ function = "led";
+ groups = "gbe1_led0";
+ };
+ };
+
+ gbe2_led0_pins: gbe2-pins {
+ mux {
+ function = "led";
+ groups = "gbe2_led0";
+ };
+ };
+
+ gbe3_led0_pins: gbe3-pins {
+ mux {
+ function = "led";
+ groups = "gbe3_led0";
+ };
+ };
+
i2c0_pins: i2c0-pins-g0 {
mux {
function = "i2c";
@@ -380,15 +401,12 @@
mdio1: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&gbe_led0_pins>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9481";
reg = <0>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe0_led0_pins>;
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
};
@@ -396,9 +414,8 @@
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id03a2.9481";
reg = <1>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe1_led0_pins>;
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
};
@@ -406,9 +423,8 @@
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id03a2.9481";
reg = <2>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe2_led0_pins>;
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
};
@@ -416,9 +432,8 @@
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id03a2.9481";
reg = <3>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe3_led0_pins>;
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
};