blob: 1e231888f2e89ca8e46c5af213ff5bfe6c871b9b [file] [log] [blame]
developer691e73f2021-06-28 19:41:35 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-spim-nor-partition.dtsi"
developer691e73f2021-06-28 19:41:35 +08005/ {
6 model = "MediaTek MT7986b RFB";
7 compatible = "mediatek,mt7986b-nor-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
developer691e73f2021-06-28 19:41:35 +080016};
17
developer565bacb2021-09-28 21:26:32 +080018&uart0 {
developer691e73f2021-06-28 19:41:35 +080019 status = "okay";
developer5b91be72021-09-27 14:03:07 +080020};
21
developer565bacb2021-09-28 21:26:32 +080022/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
developer5b91be72021-09-27 14:03:07 +080026 status = "disabled";
27};
28
developer565bacb2021-09-28 21:26:32 +080029/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
developer5b91be72021-09-27 14:03:07 +080033 status = "disabled";
developer691e73f2021-06-28 19:41:35 +080034};
35
developer565bacb2021-09-28 21:26:32 +080036&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
developer283fc452022-08-18 19:50:33 +080053
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 link-gpio = <&pio 47 0>;
59 phy-handle = <&phy5>;
60 label = "lan5";
61 };
developer565bacb2021-09-28 21:26:32 +080062 };
63
64 gmac1: mac@1 {
65 compatible = "mediatek,eth-mac";
66 reg = <1>;
67 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080068 phy-handle = <&phy6>;
developer565bacb2021-09-28 21:26:32 +080069 };
70
71 mdio: mdio-bus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
developerf0a1e452022-08-15 12:06:11 +080075 reset-gpios = <&pio 6 1>;
76 reset-delay-us = <600>;
77
developer565bacb2021-09-28 21:26:32 +080078 phy5: phy@5 {
developer283fc452022-08-18 19:50:33 +080079 compatible = "ethernet-phy-id67c9.de0a";
developer565bacb2021-09-28 21:26:32 +080080 reg = <5>;
developer565bacb2021-09-28 21:26:32 +080081 };
82
83 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +080084 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +080085 reg = <6>;
developer565bacb2021-09-28 21:26:32 +080086 };
87
88 switch@0 {
89 compatible = "mediatek,mt7531";
90 reg = <31>;
91 reset-gpios = <&pio 5 0>;
92
93 ports {
94 #address-cells = <1>;
95 #size-cells = <0>;
developer691e73f2021-06-28 19:41:35 +080096
developer565bacb2021-09-28 21:26:32 +080097 port@0 {
98 reg = <0>;
99 label = "lan0";
100 };
101
102 port@1 {
103 reg = <1>;
104 label = "lan1";
105 };
106
107 port@2 {
108 reg = <2>;
109 label = "lan2";
110 };
111
112 port@3 {
113 reg = <3>;
114 label = "lan3";
115 };
116
117 port@4 {
118 reg = <4>;
119 label = "lan4";
120 };
developer691e73f2021-06-28 19:41:35 +0800121
developer565bacb2021-09-28 21:26:32 +0800122 port@5 {
123 reg = <5>;
124 label = "lan5";
125 phy-mode = "2500base-x";
126
127 fixed-link {
128 speed = <2500>;
129 full-duplex;
130 pause;
131 };
132 };
133
134 port@6 {
135 reg = <6>;
136 label = "cpu";
137 ethernet = <&gmac0>;
138 phy-mode = "2500base-x";
139
140 fixed-link {
141 speed = <2500>;
142 full-duplex;
143 pause;
144 };
developer691e73f2021-06-28 19:41:35 +0800145 };
146 };
147 };
developer565bacb2021-09-28 21:26:32 +0800148 };
149};
150
151&hnat {
152 mtketh-wan = "eth1";
153 mtketh-lan = "lan";
154 mtketh-max-gmac = <2>;
155 status = "okay";
156};
157
158&spi0 {
159 pinctrl-names = "default";
160 pinctrl-0 = <&spi_flash_pins>;
161 cs-gpios = <0>, <0>;
162 status = "okay";
163
164 spi_nor@0 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 compatible = "jedec,spi-nor";
168 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800169 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800170 spi-tx-buswidth = <4>;
171 spi-rx-buswidth = <4>;
172 };
173};
174
175/* Warning: pins shared with &uart2 */
176&spi1 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&spic_pins>;
179 status = "okay";
180};
181
182&wbsys {
183 mediatek,mtd-eeprom = <&factory 0x0000>;
184 status = "okay";
185};
186
187&pio {
188 spi_flash_pins: spi-flash-pins-33-to-38 {
189 mux {
190 function = "flash";
191 groups = "spi0", "spi0_wp_hold";
192 };
193 conf-pu {
194 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
195 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800196 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800197 };
198 conf-pd {
199 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
200 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800201 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800202 };
203
developer691e73f2021-06-28 19:41:35 +0800204 };
205};