blob: 3fc699c2a834f2c7f2c51d9497f9727a5b8be37d [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-snfi-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986a RFB";
7 compatible = "mediatek,mt7986a-snfi-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
developerbe797a32021-12-16 16:56:09 +080017 sound_wm8960 {
18 compatible = "mediatek,mt79xx-wm8960-machine";
developer565bacb2021-09-28 21:26:32 +080019 mediatek,platform = <&afe>;
20 audio-routing = "Headphone", "HP_L",
21 "Headphone", "HP_R",
22 "LINPUT1", "AMIC",
23 "RINPUT1", "AMIC";
24 mediatek,audio-codec = <&wm8960>;
25 status = "okay";
26 };
developerbe797a32021-12-16 16:56:09 +080027
28 sound_si3218x {
29 compatible = "mediatek,mt79xx-si3218x-machine";
30 mediatek,platform = <&afe>;
31 mediatek,ext-codec = <&proslic_spi>;
32 status = "okay";
33 };
developer565bacb2021-09-28 21:26:32 +080034};
35
36&pwm {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
39 status = "okay";
40};
41
42&uart0 {
43 status = "okay";
44};
45
46&uart1 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&uart1_pins>;
49 status = "okay";
50};
51
52&uart2 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&uart2_pins>;
55 status = "okay";
56};
57
58&i2c0 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c_pins>;
61 status = "okay";
62
63 wm8960: wm8960@1a {
64 compatible = "wlf,wm8960";
65 reg = <0x1a>;
66 };
67};
68
69&auxadc {
70 status = "okay";
71};
72
73&watchdog {
74 status = "okay";
75};
76
77&eth {
78 status = "okay";
79
80 gmac0: mac@0 {
81 compatible = "mediatek,eth-mac";
82 reg = <0>;
83 phy-mode = "2500base-x";
84
85 fixed-link {
86 speed = <2500>;
87 full-duplex;
88 pause;
89 };
90 };
91
92 gmac1: mac@1 {
93 compatible = "mediatek,eth-mac";
94 reg = <1>;
95 phy-mode = "2500base-x";
96
97 fixed-link {
98 speed = <2500>;
99 full-duplex;
100 pause;
101 };
102 };
103
104 mdio: mdio-bus {
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 phy5: phy@5 {
109 compatible = "ethernet-phy-id67c9.de0a";
110 reg = <5>;
111 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800112 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +0800113 reset-deassert-us = <20000>;
114 phy-mode = "2500base-x";
115 };
116
117 phy6: phy@6 {
118 compatible = "ethernet-phy-id67c9.de0a";
119 reg = <6>;
120 phy-mode = "2500base-x";
121 };
122
123 switch@0 {
124 compatible = "mediatek,mt7531";
125 reg = <31>;
126 reset-gpios = <&pio 5 0>;
127
128 ports {
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 port@0 {
133 reg = <0>;
134 label = "lan0";
135 };
136
137 port@1 {
138 reg = <1>;
139 label = "lan1";
140 };
141
142 port@2 {
143 reg = <2>;
144 label = "lan2";
145 };
146
147 port@3 {
148 reg = <3>;
149 label = "lan3";
150 };
151
152 port@6 {
153 reg = <6>;
154 label = "cpu";
155 ethernet = <&gmac0>;
156 phy-mode = "2500base-x";
157
158 fixed-link {
159 speed = <2500>;
160 full-duplex;
161 pause;
162 };
163 };
164 };
165 };
166 };
167};
168
169&hnat {
170 mtketh-wan = "eth1";
171 mtketh-lan = "lan";
172 mtketh-max-gmac = <2>;
173 status = "okay";
174};
175
176&snand {
177 pinctrl-names = "default";
178 pinctrl-0 = <&snfi_pins>;
179 mediatek,quad-spi;
180 status = "okay";
181
182 partitions {
183 compatible = "fixed-partitions";
184 #address-cells = <1>;
185 #size-cells = <1>;
186 };
187};
188
189&spi1 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&spic_pins_g2>;
192 status = "okay";
developerbe797a32021-12-16 16:56:09 +0800193
194 proslic_spi: proslic_spi@0 {
195 compatible = "silabs,proslic_spi";
196 reg = <0>;
197 spi-max-frequency = <10000000>;
198 spi-cpha = <1>;
199 spi-cpol = <1>;
200 channel_count = <1>;
201 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
202 reset_gpio = <&pio 7 0>;
203 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
204 };
developer565bacb2021-09-28 21:26:32 +0800205};
206
207&pcie0 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pcie0_pins>;
210 status = "okay";
211};
212
213&wbsys {
214 mediatek,mtd-eeprom = <&factory 0x0000>;
215 status = "okay";
216};
217
218&pio {
219 snfi_pins: snfi-pins-23-to-28 {
220 mux {
221 function = "flash";
222 groups = "snfi";
223 };
224 conf-clk {
225 pins = "SPI0_CLK";
226 drive-strength = <MTK_DRIVE_8mA>;
227 mediatek,pull-down-adv = <0>; /* bias-disable */
228 };
229 conf-pu {
230 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
231 drive-strength = <MTK_DRIVE_6mA>;
232 mediatek,pull-up-adv = <0>; /* bias-disable */
233 };
234 conf-pd {
235 pins = "SPI0_MOSI", "SPI0_MISO";
236 drive-strength = <MTK_DRIVE_6mA>;
237 mediatek,pull-down-adv = <0>; /* bias-disable */
238 };
239 };
240};