blob: 31640382b177a25f06860dea79f1783c3564bbd7 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-snfi-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986a RFB";
7 compatible = "mediatek,mt7986a-snfi-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
developerbe797a32021-12-16 16:56:09 +080017 sound_wm8960 {
18 compatible = "mediatek,mt79xx-wm8960-machine";
developer565bacb2021-09-28 21:26:32 +080019 mediatek,platform = <&afe>;
20 audio-routing = "Headphone", "HP_L",
21 "Headphone", "HP_R",
22 "LINPUT1", "AMIC",
23 "RINPUT1", "AMIC";
24 mediatek,audio-codec = <&wm8960>;
25 status = "okay";
26 };
developerbe797a32021-12-16 16:56:09 +080027
28 sound_si3218x {
29 compatible = "mediatek,mt79xx-si3218x-machine";
30 mediatek,platform = <&afe>;
31 mediatek,ext-codec = <&proslic_spi>;
32 status = "okay";
33 };
developer565bacb2021-09-28 21:26:32 +080034};
35
36&pwm {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
39 status = "okay";
40};
41
42&uart0 {
43 status = "okay";
44};
45
46&uart1 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&uart1_pins>;
49 status = "okay";
50};
51
52&uart2 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&uart2_pins>;
55 status = "okay";
56};
57
58&i2c0 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c_pins>;
61 status = "okay";
62
63 wm8960: wm8960@1a {
64 compatible = "wlf,wm8960";
65 reg = <0x1a>;
66 };
67};
68
69&auxadc {
70 status = "okay";
71};
72
73&watchdog {
74 status = "okay";
75};
76
77&eth {
78 status = "okay";
79
80 gmac0: mac@0 {
81 compatible = "mediatek,eth-mac";
82 reg = <0>;
83 phy-mode = "2500base-x";
84
85 fixed-link {
86 speed = <2500>;
87 full-duplex;
88 pause;
89 };
90 };
91
92 gmac1: mac@1 {
93 compatible = "mediatek,eth-mac";
94 reg = <1>;
95 phy-mode = "2500base-x";
96
97 fixed-link {
98 speed = <2500>;
99 full-duplex;
100 pause;
101 };
102 };
103
104 mdio: mdio-bus {
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 phy5: phy@5 {
109 compatible = "ethernet-phy-id67c9.de0a";
110 reg = <5>;
111 reset-gpios = <&pio 6 1>;
112 reset-deassert-us = <20000>;
113 phy-mode = "2500base-x";
114 };
115
116 phy6: phy@6 {
117 compatible = "ethernet-phy-id67c9.de0a";
118 reg = <6>;
119 phy-mode = "2500base-x";
120 };
121
122 switch@0 {
123 compatible = "mediatek,mt7531";
124 reg = <31>;
125 reset-gpios = <&pio 5 0>;
126
127 ports {
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 port@0 {
132 reg = <0>;
133 label = "lan0";
134 };
135
136 port@1 {
137 reg = <1>;
138 label = "lan1";
139 };
140
141 port@2 {
142 reg = <2>;
143 label = "lan2";
144 };
145
146 port@3 {
147 reg = <3>;
148 label = "lan3";
149 };
150
151 port@6 {
152 reg = <6>;
153 label = "cpu";
154 ethernet = <&gmac0>;
155 phy-mode = "2500base-x";
156
157 fixed-link {
158 speed = <2500>;
159 full-duplex;
160 pause;
161 };
162 };
163 };
164 };
165 };
166};
167
168&hnat {
169 mtketh-wan = "eth1";
170 mtketh-lan = "lan";
171 mtketh-max-gmac = <2>;
172 status = "okay";
173};
174
175&snand {
176 pinctrl-names = "default";
177 pinctrl-0 = <&snfi_pins>;
178 mediatek,quad-spi;
179 status = "okay";
180
181 partitions {
182 compatible = "fixed-partitions";
183 #address-cells = <1>;
184 #size-cells = <1>;
185 };
186};
187
188&spi1 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&spic_pins_g2>;
191 status = "okay";
developerbe797a32021-12-16 16:56:09 +0800192
193 proslic_spi: proslic_spi@0 {
194 compatible = "silabs,proslic_spi";
195 reg = <0>;
196 spi-max-frequency = <10000000>;
197 spi-cpha = <1>;
198 spi-cpol = <1>;
199 channel_count = <1>;
200 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
201 reset_gpio = <&pio 7 0>;
202 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
203 };
developer565bacb2021-09-28 21:26:32 +0800204};
205
206&pcie0 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pcie0_pins>;
209 status = "okay";
210};
211
212&wbsys {
213 mediatek,mtd-eeprom = <&factory 0x0000>;
214 status = "okay";
215};
216
217&pio {
218 snfi_pins: snfi-pins-23-to-28 {
219 mux {
220 function = "flash";
221 groups = "snfi";
222 };
223 conf-clk {
224 pins = "SPI0_CLK";
225 drive-strength = <MTK_DRIVE_8mA>;
226 mediatek,pull-down-adv = <0>; /* bias-disable */
227 };
228 conf-pu {
229 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
230 drive-strength = <MTK_DRIVE_6mA>;
231 mediatek,pull-up-adv = <0>; /* bias-disable */
232 };
233 conf-pd {
234 pins = "SPI0_MOSI", "SPI0_MISO";
235 drive-strength = <MTK_DRIVE_6mA>;
236 mediatek,pull-down-adv = <0>; /* bias-disable */
237 };
238 };
239};