blob: 713f76f3b02bf1f6330779e982d7d0f49980c1dc [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
5 compatible = "mediatek,mt7981-emmc-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000 \
9 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
10 };
11
12 memory {
13 // fpga ddr2: 128MB*2
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_3p3v: regulator-3p3v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-3.3V";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
25};
26
27&uart0 {
28 status = "okay";
29};
30
31&watchdog {
32 status = "okay";
33};
34
35&mmc0 {
36 pinctrl-names = "default", "state_uhs";
37 pinctrl-0 = <&mmc0_pins_default>;
38 pinctrl-1 = <&mmc0_pins_uhs>;
39 bus-width = <4>;
40 max-frequency = <52000000>;
41 cap-sd-highspeed;
42 vmmc-supply = <&reg_3p3v>;
43 vqmmc-supply = <&reg_3p3v>;
44 status = "okay";
45};
46
47&eth {
48 status = "okay";
49
50 gmac0: mac@0 {
51 compatible = "mediatek,eth-mac";
52 reg = <0>;
53 phy-mode = "2500base-x";
54
55 fixed-link {
56 speed = <2500>;
57 full-duplex;
58 pause;
59 };
60 };
61
62 gmac1: mac@1 {
63 compatible = "mediatek,eth-mac";
64 reg = <1>;
65 phy-mode = "gmii";
66 phy-handle = <&phy0>;
67 };
68
69 mdio: mdio-bus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 phy0: ethernet-phy@0 {
developera7de8be2021-11-15 21:14:31 +080074 compatible = "ethernet-phy-id03a2.9461";
developer24455dd2021-10-28 10:55:41 +080075 reg = <0>;
developera7de8be2021-11-15 21:14:31 +080076 phy-mode = "gmii";
77 rext = "sw";
78 tx_r50 = "sw";
79 tx_vcm = "sw";
80 nvmem-cells = <&phy_calibration>;
81 nvmem-cell-names = "phy-cal-data";
developer24455dd2021-10-28 10:55:41 +080082 };
83
84 switch@0 {
85 compatible = "mediatek,mt7531";
86 reg = <31>;
87 reset-gpios = <&pio 39 0>;
88
89 ports {
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 port@0 {
94 reg = <0>;
95 label = "lan1";
96 };
97
98 port@1 {
99 reg = <1>;
100 label = "lan2";
101 };
102
103 port@2 {
104 reg = <2>;
105 label = "lan3";
106 };
107
108 port@3 {
109 reg = <3>;
110 label = "lan4";
111 };
112
113 port@6 {
114 reg = <6>;
115 label = "cpu";
116 ethernet = <&gmac0>;
117 phy-mode = "2500base-x";
118
119 fixed-link {
120 speed = <2500>;
121 full-duplex;
122 pause;
123 };
124 };
125 };
126 };
127 };
128};
129
130&hnat {
131 mtketh-wan = "eth1";
132 mtketh-lan = "lan";
133 mtketh-max-gmac = <2>;
134 status = "okay";
135};
136
137&spi1 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&spic_pins>;
140 status = "disabled";
141};
142
143&pio {
144
145 spic_pins: spi1-pins {
146 mux {
147 function = "spi";
148 groups = "spi1_1";
149 };
150 };
151
152 mmc0_pins_default: mmc0-pins-default {
153 mux {
154 function = "flash";
155 groups = "emmc_45";
156 };
157 };
158
159 mmc0_pins_uhs: mmc0-pins-uhs {
160 mux {
161 function = "flash";
162 groups = "emmc_45";
163 };
164 };
165};
166
167&xhci {
168 mediatek,u3p-dis-msk = <0x0>;
169 phys = <&u2port0 PHY_TYPE_USB2>,
170 <&u3port0 PHY_TYPE_USB3>;
171 status = "okay";
172};