| developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame^] | 1 | /dts-v1/; |
| 2 | #include "mt7981.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7981 RFB"; |
| 5 | compatible = "mediatek,mt7981-emmc-rfb"; |
| 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000 \ |
| 9 | root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs"; |
| 10 | }; |
| 11 | |
| 12 | memory { |
| 13 | // fpga ddr2: 128MB*2 |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | reg_3p3v: regulator-3p3v { |
| 18 | compatible = "regulator-fixed"; |
| 19 | regulator-name = "fixed-3.3V"; |
| 20 | regulator-min-microvolt = <3300000>; |
| 21 | regulator-max-microvolt = <3300000>; |
| 22 | regulator-boot-on; |
| 23 | regulator-always-on; |
| 24 | }; |
| 25 | }; |
| 26 | |
| 27 | &uart0 { |
| 28 | status = "okay"; |
| 29 | }; |
| 30 | |
| 31 | &watchdog { |
| 32 | status = "okay"; |
| 33 | }; |
| 34 | |
| 35 | &mmc0 { |
| 36 | pinctrl-names = "default", "state_uhs"; |
| 37 | pinctrl-0 = <&mmc0_pins_default>; |
| 38 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 39 | bus-width = <4>; |
| 40 | max-frequency = <52000000>; |
| 41 | cap-sd-highspeed; |
| 42 | vmmc-supply = <®_3p3v>; |
| 43 | vqmmc-supply = <®_3p3v>; |
| 44 | status = "okay"; |
| 45 | }; |
| 46 | |
| 47 | ð { |
| 48 | status = "okay"; |
| 49 | |
| 50 | gmac0: mac@0 { |
| 51 | compatible = "mediatek,eth-mac"; |
| 52 | reg = <0>; |
| 53 | phy-mode = "2500base-x"; |
| 54 | |
| 55 | fixed-link { |
| 56 | speed = <2500>; |
| 57 | full-duplex; |
| 58 | pause; |
| 59 | }; |
| 60 | }; |
| 61 | |
| 62 | gmac1: mac@1 { |
| 63 | compatible = "mediatek,eth-mac"; |
| 64 | reg = <1>; |
| 65 | phy-mode = "gmii"; |
| 66 | phy-handle = <&phy0>; |
| 67 | }; |
| 68 | |
| 69 | mdio: mdio-bus { |
| 70 | #address-cells = <1>; |
| 71 | #size-cells = <0>; |
| 72 | |
| 73 | phy0: ethernet-phy@0 { |
| 74 | reg = <0>; |
| 75 | }; |
| 76 | |
| 77 | switch@0 { |
| 78 | compatible = "mediatek,mt7531"; |
| 79 | reg = <31>; |
| 80 | reset-gpios = <&pio 39 0>; |
| 81 | |
| 82 | ports { |
| 83 | #address-cells = <1>; |
| 84 | #size-cells = <0>; |
| 85 | |
| 86 | port@0 { |
| 87 | reg = <0>; |
| 88 | label = "lan1"; |
| 89 | }; |
| 90 | |
| 91 | port@1 { |
| 92 | reg = <1>; |
| 93 | label = "lan2"; |
| 94 | }; |
| 95 | |
| 96 | port@2 { |
| 97 | reg = <2>; |
| 98 | label = "lan3"; |
| 99 | }; |
| 100 | |
| 101 | port@3 { |
| 102 | reg = <3>; |
| 103 | label = "lan4"; |
| 104 | }; |
| 105 | |
| 106 | port@6 { |
| 107 | reg = <6>; |
| 108 | label = "cpu"; |
| 109 | ethernet = <&gmac0>; |
| 110 | phy-mode = "2500base-x"; |
| 111 | |
| 112 | fixed-link { |
| 113 | speed = <2500>; |
| 114 | full-duplex; |
| 115 | pause; |
| 116 | }; |
| 117 | }; |
| 118 | }; |
| 119 | }; |
| 120 | }; |
| 121 | }; |
| 122 | |
| 123 | &hnat { |
| 124 | mtketh-wan = "eth1"; |
| 125 | mtketh-lan = "lan"; |
| 126 | mtketh-max-gmac = <2>; |
| 127 | status = "okay"; |
| 128 | }; |
| 129 | |
| 130 | &spi1 { |
| 131 | pinctrl-names = "default"; |
| 132 | pinctrl-0 = <&spic_pins>; |
| 133 | status = "disabled"; |
| 134 | }; |
| 135 | |
| 136 | &pio { |
| 137 | |
| 138 | spic_pins: spi1-pins { |
| 139 | mux { |
| 140 | function = "spi"; |
| 141 | groups = "spi1_1"; |
| 142 | }; |
| 143 | }; |
| 144 | |
| 145 | mmc0_pins_default: mmc0-pins-default { |
| 146 | mux { |
| 147 | function = "flash"; |
| 148 | groups = "emmc_45"; |
| 149 | }; |
| 150 | }; |
| 151 | |
| 152 | mmc0_pins_uhs: mmc0-pins-uhs { |
| 153 | mux { |
| 154 | function = "flash"; |
| 155 | groups = "emmc_45"; |
| 156 | }; |
| 157 | }; |
| 158 | }; |
| 159 | |
| 160 | &xhci { |
| 161 | mediatek,u3p-dis-msk = <0x0>; |
| 162 | phys = <&u2port0 PHY_TYPE_USB2>, |
| 163 | <&u3port0 PHY_TYPE_USB3>; |
| 164 | status = "okay"; |
| 165 | }; |