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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 9b3248d63a838479a94e271da76173d49c2e2ba5 / . / autobuild_mac80211_release / mt7986_besra_mac80211 / package / kernel / mt76 / src / mt76_connac_mcu.h
blob: 207569d2e510a9533987dd23c8f83c25dd4ba2c4 [file] [log] [blame]
developerb11a5392022-03-31 00:34:47 +0800[diff] [blame]1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT76_CONNAC_MCU_H
5#define __MT76_CONNAC_MCU_H
6
7#include "mt76_connac.h"
8
9#define FW_FEATURE_SET_ENCRYPT BIT(0)
10#define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
11#define FW_FEATURE_ENCRY_MODE BIT(4)
12#define FW_FEATURE_OVERRIDE_ADDR BIT(5)
13
14#define DL_MODE_ENCRYPT BIT(0)
15#define DL_MODE_KEY_IDX GENMASK(2, 1)
16#define DL_MODE_RESET_SEC_IV BIT(3)
17#define DL_MODE_WORKING_PDA_CR4 BIT(4)
18#define DL_MODE_VALID_RAM_ENTRY BIT(5)
19#define DL_CONFIG_ENCRY_MODE_SEL BIT(6)
20#define DL_MODE_NEED_RSP BIT(31)
21
22#define FW_START_OVERRIDE BIT(0)
23#define FW_START_WORKING_PDA_CR4 BIT(2)
24
25#define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)
26#define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
27#define PATCH_SEC_TYPE_INFO 0x2
28
29struct tlv {
30 __le16 tag;
31 __le16 len;
32} __packed;
33
34struct bss_info_omac {
35 __le16 tag;
36 __le16 len;
37 u8 hw_bss_idx;
38 u8 omac_idx;
39 u8 band_idx;
40 u8 rsv0;
41 __le32 conn_type;
42 u32 rsv1;
43} __packed;
44
45struct bss_info_basic {
46 __le16 tag;
47 __le16 len;
48 __le32 network_type;
49 u8 active;
50 u8 rsv0;
51 __le16 bcn_interval;
52 u8 bssid[ETH_ALEN];
53 u8 wmm_idx;
54 u8 dtim_period;
55 u8 bmc_wcid_lo;
56 u8 cipher;
57 u8 phy_mode;
58 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
59 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
60 u8 bmc_wcid_hi; /* high Byte and version */
61 u8 rsv[2];
62} __packed;
63
64struct bss_info_rf_ch {
65 __le16 tag;
66 __le16 len;
67 u8 pri_ch;
68 u8 center_ch0;
69 u8 center_ch1;
70 u8 bw;
71 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
72 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
73 u8 rsv[2];
74} __packed;
75
76struct bss_info_ext_bss {
77 __le16 tag;
78 __le16 len;
79 __le32 mbss_tsf_offset; /* in unit of us */
80 u8 rsv[8];
81} __packed;
82
83enum {
84 BSS_INFO_OMAC,
85 BSS_INFO_BASIC,
86 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
87 BSS_INFO_PM, /* sta only */
88 BSS_INFO_UAPSD, /* sta only */
89 BSS_INFO_ROAM_DETECT, /* obsoleted */
90 BSS_INFO_LQ_RM, /* obsoleted */
91 BSS_INFO_EXT_BSS,
92 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
93 BSS_INFO_SYNC_MODE, /* obsoleted */
94 BSS_INFO_RA,
95 BSS_INFO_HW_AMSDU,
96 BSS_INFO_BSS_COLOR,
97 BSS_INFO_HE_BASIC,
98 BSS_INFO_PROTECT_INFO,
99 BSS_INFO_OFFLOAD,
100 BSS_INFO_11V_MBSSID,
101 BSS_INFO_MAX_NUM
102};
103
104/* sta_rec */
105
106struct sta_ntlv_hdr {
107 u8 rsv[2];
108 __le16 tlv_num;
109} __packed;
110
111struct sta_req_hdr {
112 u8 bss_idx;
113 u8 wlan_idx_lo;
114 __le16 tlv_num;
115 u8 is_tlv_append;
116 u8 muar_idx;
117 u8 wlan_idx_hi;
118 u8 rsv;
119} __packed;
120
121struct sta_rec_basic {
122 __le16 tag;
123 __le16 len;
124 __le32 conn_type;
125 u8 conn_state;
126 u8 qos;
127 __le16 aid;
128 u8 peer_addr[ETH_ALEN];
129#define EXTRA_INFO_VER BIT(0)
130#define EXTRA_INFO_NEW BIT(1)
131 __le16 extra_info;
132} __packed;
133
134struct sta_rec_ht {
135 __le16 tag;
136 __le16 len;
137 __le16 ht_cap;
138 __le16 ext_ht_cap;
139} __packed;
140
141struct sta_rec_vht {
142 __le16 tag;
143 __le16 len;
144 __le32 vht_cap;
145 __le16 vht_rx_mcs_map;
146 __le16 vht_tx_mcs_map;
147 /* mt7915 - mt7921 */
148 u8 rts_bw_sig;
149 u8 rsv[3];
150} __packed;
151
152struct sta_rec_uapsd {
153 __le16 tag;
154 __le16 len;
155 u8 dac_map;
156 u8 tac_map;
157 u8 max_sp;
158 u8 rsv0;
159 __le16 listen_interval;
160 u8 rsv1[2];
161} __packed;
162
163struct sta_rec_ba {
164 __le16 tag;
165 __le16 len;
166 u8 tid;
167 u8 ba_type;
168 u8 amsdu;
169 u8 ba_en;
170 __le16 ssn;
171 __le16 winsize;
172} __packed;
173
174struct uni_sta_rec_ba {
175 __le16 tag;
176 __le16 len;
177 u8 tid;
178 u8 ba_type;
179 u8 amsdu;
180 u8 ba_en;
181 __le16 ssn;
182 __le16 winsize;
183 u8 ba_rdd_rro;
184 u8 __rsv[3];
185} __packed;
186
187struct sta_rec_he {
188 __le16 tag;
189 __le16 len;
190
191 __le32 he_cap;
192
193 u8 t_frame_dur;
194 u8 max_ampdu_exp;
195 u8 bw_set;
196 u8 device_class;
197 u8 dcm_tx_mode;
198 u8 dcm_tx_max_nss;
199 u8 dcm_rx_mode;
200 u8 dcm_rx_max_nss;
201 u8 dcm_max_ru;
202 u8 punc_pream_rx;
203 u8 pkt_ext;
204 u8 rsv1;
205
206 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
207
208 u8 rsv2[2];
209} __packed;
210
211struct sta_rec_he_v2 {
212 __le16 tag;
213 __le16 len;
214
215 u8 he_mac_cap[6];
216 u8 he_phy_cap[11];
217 u8 pkt_ext;
218 /*0: BW80, 1: BW160, 2: BW8080*/
219 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
220} __packed;
221
222struct sta_rec_amsdu {
223 __le16 tag;
224 __le16 len;
225 u8 max_amsdu_num;
226 u8 max_mpdu_size;
227 u8 amsdu_en;
228 u8 rsv;
229} __packed;
230
231struct sta_rec_state {
232 __le16 tag;
233 __le16 len;
234 __le32 flags;
235 u8 state;
236 u8 vht_opmode;
237 u8 action;
238 u8 rsv[1];
239} __packed;
240
241#define RA_LEGACY_OFDM GENMASK(13, 6)
242#define RA_LEGACY_CCK GENMASK(3, 0)
243#define HT_MCS_MASK_NUM 10
244struct sta_rec_ra_info {
245 __le16 tag;
246 __le16 len;
247 __le16 legacy;
248 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
249} __packed;
250
251struct sta_rec_phy {
252 __le16 tag;
253 __le16 len;
254 __le16 basic_rate;
255 u8 phy_type;
256 u8 ampdu;
257 u8 rts_policy;
258 u8 rcpi;
259 u8 rsv[2];
260} __packed;
261
262struct sta_rec_he_6g_capa {
263 __le16 tag;
264 __le16 len;
265 __le16 capa;
266 u8 rsv[2];
267} __packed;
268
269struct sec_key {
270 u8 cipher_id;
271 u8 cipher_len;
272 u8 key_id;
273 u8 key_len;
274 u8 key[32];
275} __packed;
276
277struct sta_rec_sec {
278 __le16 tag;
279 __le16 len;
280 u8 add;
281 u8 n_cipher;
282 u8 rsv[2];
283
284 struct sec_key key[2];
285} __packed;
286
287struct uni_sec_key {
288 __le16 wlan_idx;
289 u8 mgmt_prot;
290 u8 cipher_id;
291 u8 cipher_len;
292 u8 key_id;
293 u8 key_len;
294 u8 need_resp;
295 u8 key[32];
296} __packed;
297
298struct uni_sta_rec_sec {
299 __le16 tag;
300 __le16 len;
301 u8 add;
302 u8 n_cipher;
303 u8 rsv[2];
304
305 struct uni_sec_key key[2];
306} __packed;
307
308struct sta_rec_bf {
309 __le16 tag;
310 __le16 len;
311
312 __le16 pfmu; /* 0xffff: no access right for PFMU */
313 bool su_mu; /* 0: SU, 1: MU */
314 u8 bf_cap; /* 0: iBF, 1: eBF */
315 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
316 u8 ndpa_rate;
317 u8 ndp_rate;
318 u8 rept_poll_rate;
319 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
320 u8 ncol;
321 u8 nrow;
322 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
323
324 u8 mem_total;
325 u8 mem_20m;
326 struct {
327 u8 row;
328 u8 col: 6, row_msb: 2;
329 } mem[4];
330
331 __le16 smart_ant;
332 u8 se_idx;
333 u8 auto_sounding; /* b7: low traffic indicator
334 * b6: Stop sounding for this entry
335 * b5 ~ b0: postpone sounding
336 */
337 u8 ibf_timeout;
338 u8 ibf_dbw;
339 u8 ibf_ncol;
340 u8 ibf_nrow;
341 u8 nrow_bw160;
342 u8 ncol_bw160;
343 u8 ru_start_idx;
344 u8 ru_end_idx;
345
346 bool trigger_su;
347 bool trigger_mu;
348 bool ng16_su;
349 bool ng16_mu;
350 bool codebook42_su;
351 bool codebook75_mu;
352
353 u8 he_ltf;
354 u8 rsv[3];
355} __packed;
356
357struct sta_rec_bfee {
358 __le16 tag;
359 __le16 len;
360 bool fb_identity_matrix; /* 1: feedback identity matrix */
361 bool ignore_feedback; /* 1: ignore */
362 u8 rsv[2];
363} __packed;
364
365struct sta_rec_muru {
366 __le16 tag;
367 __le16 len;
368
369 struct {
370 bool ofdma_dl_en;
371 bool ofdma_ul_en;
372 bool mimo_dl_en;
373 bool mimo_ul_en;
374 u8 rsv[4];
375 } cfg;
376
377 struct {
378 u8 punc_pream_rx;
379 bool he_20m_in_40m_2g;
380 bool he_20m_in_160m;
381 bool he_80m_in_160m;
382 bool lt16_sigb;
383 bool rx_su_comp_sigb;
384 bool rx_su_non_comp_sigb;
385 u8 rsv;
386 } ofdma_dl;
387
388 struct {
389 u8 t_frame_dur;
390 u8 mu_cascading;
391 u8 uo_ra;
392 u8 he_2x996_tone;
393 u8 rx_t_frame_11ac;
394 u8 rx_ctrl_to_mbss;
395 u8 rsv[2];
396 } ofdma_ul;
397
398 struct {
399 bool vht_mu_bfee;
400 bool partial_bw_dl_mimo;
401 u8 rsv[2];
402 } mimo_dl;
403
404 struct {
405 bool full_ul_mimo;
406 bool partial_ul_mimo;
407 u8 rsv[2];
408 } mimo_ul;
409} __packed;
410
411struct sta_phy {
412 u8 type;
413 u8 flag;
414 u8 stbc;
415 u8 sgi;
416 u8 bw;
417 u8 ldpc;
418 u8 mcs;
419 u8 nss;
420 u8 he_ltf;
421};
422
423struct sta_rec_ra {
424 __le16 tag;
425 __le16 len;
426
427 u8 valid;
428 u8 auto_rate;
429 u8 phy_mode;
430 u8 channel;
431 u8 bw;
432 u8 disable_cck;
433 u8 ht_mcs32;
434 u8 ht_gf;
435 u8 ht_mcs[4];
436 u8 mmps_mode;
437 u8 gband_256;
438 u8 af;
439 u8 auth_wapi_mode;
440 u8 rate_len;
441
442 u8 supp_mode;
443 u8 supp_cck_rate;
444 u8 supp_ofdm_rate;
445 __le32 supp_ht_mcs;
446 __le16 supp_vht_mcs[4];
447
448 u8 op_mode;
449 u8 op_vht_chan_width;
450 u8 op_vht_rx_nss;
451 u8 op_vht_rx_nss_type;
452
453 __le32 sta_cap;
454
455 struct sta_phy phy;
456} __packed;
457
458struct sta_rec_ra_fixed {
459 __le16 tag;
460 __le16 len;
461
462 __le32 field;
463 u8 op_mode;
464 u8 op_vht_chan_width;
465 u8 op_vht_rx_nss;
466 u8 op_vht_rx_nss_type;
467
468 struct sta_phy phy;
469
470 u8 spe_en;
471 u8 short_preamble;
472 u8 is_5g;
473 u8 mmps_mode;
474} __packed;
475
developer66cd2092022-05-10 15:43:01 +0800[diff] [blame]476struct sta_rec_hdr_trans {
477 __le16 tag;
478 __le16 len;
479 u8 from_ds;
480 u8 to_ds;
481 u8 dis_rx_hdr_tran;
482 u8 rsv;
483} __packed;
484
developerb11a5392022-03-31 00:34:47 +0800[diff] [blame]485/* wtbl_rec */
486
487struct wtbl_req_hdr {
488 u8 wlan_idx_lo;
489 u8 operation;
490 __le16 tlv_num;
491 u8 wlan_idx_hi;
492 u8 rsv[3];
493} __packed;
494
495struct wtbl_generic {
496 __le16 tag;
497 __le16 len;
498 u8 peer_addr[ETH_ALEN];
499 u8 muar_idx;
500 u8 skip_tx;
501 u8 cf_ack;
502 u8 qos;
503 u8 mesh;
504 u8 adm;
505 __le16 partial_aid;
506 u8 baf_en;
507 u8 aad_om;
508} __packed;
509
510struct wtbl_rx {
511 __le16 tag;
512 __le16 len;
513 u8 rcid;
514 u8 rca1;
515 u8 rca2;
516 u8 rv;
517 u8 rsv[4];
518} __packed;
519
520struct wtbl_ht {
521 __le16 tag;
522 __le16 len;
523 u8 ht;
524 u8 ldpc;
525 u8 af;
526 u8 mm;
527 u8 rsv[4];
528} __packed;
529
530struct wtbl_vht {
531 __le16 tag;
532 __le16 len;
533 u8 ldpc;
534 u8 dyn_bw;
535 u8 vht;
536 u8 txop_ps;
537 u8 rsv[4];
538} __packed;
539
540struct wtbl_tx_ps {
541 __le16 tag;
542 __le16 len;
543 u8 txps;
544 u8 rsv[3];
545} __packed;
546
547struct wtbl_hdr_trans {
548 __le16 tag;
549 __le16 len;
550 u8 to_ds;
551 u8 from_ds;
552 u8 no_rx_trans;
553 u8 rsv;
554} __packed;
555
556struct wtbl_ba {
557 __le16 tag;
558 __le16 len;
559 /* common */
560 u8 tid;
561 u8 ba_type;
562 u8 rsv0[2];
563 /* originator only */
564 __le16 sn;
565 u8 ba_en;
566 u8 ba_winsize_idx;
567 /* originator & recipient */
568 __le16 ba_winsize;
569 /* recipient only */
570 u8 peer_addr[ETH_ALEN];
571 u8 rst_ba_tid;
572 u8 rst_ba_sel;
573 u8 rst_ba_sb;
574 u8 band_idx;
575 u8 rsv1[4];
576} __packed;
577
578struct wtbl_smps {
579 __le16 tag;
580 __le16 len;
581 u8 smps;
582 u8 rsv[3];
583} __packed;
584
585/* mt7615 only */
586
587struct wtbl_bf {
588 __le16 tag;
589 __le16 len;
590 u8 ibf;
591 u8 ebf;
592 u8 ibf_vht;
593 u8 ebf_vht;
594 u8 gid;
595 u8 pfmu_idx;
596 u8 rsv[2];
597} __packed;
598
599struct wtbl_pn {
600 __le16 tag;
601 __le16 len;
602 u8 pn[6];
603 u8 rsv[2];
604} __packed;
605
606struct wtbl_spe {
607 __le16 tag;
608 __le16 len;
609 u8 spe_idx;
610 u8 rsv[3];
611} __packed;
612
613struct wtbl_raw {
614 __le16 tag;
615 __le16 len;
616 u8 wtbl_idx;
617 u8 dw;
618 u8 rsv[2];
619 __le32 msk;
620 __le32 val;
621} __packed;
622
623#define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
624 sizeof(struct wtbl_generic) + \
625 sizeof(struct wtbl_rx) + \
626 sizeof(struct wtbl_ht) + \
627 sizeof(struct wtbl_vht) + \
628 sizeof(struct wtbl_tx_ps) + \
629 sizeof(struct wtbl_hdr_trans) +\
630 sizeof(struct wtbl_ba) + \
631 sizeof(struct wtbl_bf) + \
632 sizeof(struct wtbl_smps) + \
633 sizeof(struct wtbl_pn) + \
634 sizeof(struct wtbl_spe))
635
636#define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
637 sizeof(struct sta_rec_basic) + \
638 sizeof(struct sta_rec_bf) + \
639 sizeof(struct sta_rec_ht) + \
640 sizeof(struct sta_rec_he_v2) + \
641 sizeof(struct uni_sta_rec_ba) + \
642 sizeof(struct sta_rec_vht) + \
643 sizeof(struct sta_rec_uapsd) + \
644 sizeof(struct sta_rec_amsdu) + \
645 sizeof(struct sta_rec_muru) + \
646 sizeof(struct sta_rec_bfee) + \
647 sizeof(struct sta_rec_phy) + \
648 sizeof(struct sta_rec_ra) + \
649 sizeof(struct sta_rec_sec) + \
650 sizeof(struct sta_rec_ra_fixed) + \
651 sizeof(struct sta_rec_he_6g_capa) + \
developer66cd2092022-05-10 15:43:01 +0800[diff] [blame]652 sizeof(struct sta_rec_hdr_trans) + \
developerb11a5392022-03-31 00:34:47 +0800[diff] [blame]653 sizeof(struct tlv) + \
654 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
655
656enum {
657 STA_REC_BASIC,
658 STA_REC_RA,
659 STA_REC_RA_CMM_INFO,
660 STA_REC_RA_UPDATE,
661 STA_REC_BF,
662 STA_REC_AMSDU,
663 STA_REC_BA,
664 STA_REC_STATE,
665 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
666 STA_REC_HT,
667 STA_REC_VHT,
668 STA_REC_APPS,
669 STA_REC_KEY,
670 STA_REC_WTBL,
671 STA_REC_HE,
672 STA_REC_HW_AMSDU,
673 STA_REC_WTBL_AADOM,
674 STA_REC_KEY_V2,
675 STA_REC_MURU,
676 STA_REC_MUEDCA,
677 STA_REC_BFEE,
678 STA_REC_PHY = 0x15,
679 STA_REC_HE_6G = 0x17,
680 STA_REC_HE_V2 = 0x19,
developer66cd2092022-05-10 15:43:01 +0800[diff] [blame]681 STA_REC_HDR_TRANS = 0x2B,
developerb11a5392022-03-31 00:34:47 +0800[diff] [blame]682 STA_REC_MAX_NUM
683};
684
685enum {
686 WTBL_GENERIC,
687 WTBL_RX,
688 WTBL_HT,
689 WTBL_VHT,
690 WTBL_PEER_PS, /* not used */
691 WTBL_TX_PS,
692 WTBL_HDR_TRANS,
693 WTBL_SEC_KEY,
694 WTBL_BA,
695 WTBL_RDG, /* obsoleted */
696 WTBL_PROTECT, /* not used */
697 WTBL_CLEAR, /* not used */
698 WTBL_BF,
699 WTBL_SMPS,
700 WTBL_RAW_DATA, /* debug only */
701 WTBL_PN,
702 WTBL_SPE,
703 WTBL_MAX_NUM
704};
705
706#define STA_TYPE_STA BIT(0)
707#define STA_TYPE_AP BIT(1)
708#define STA_TYPE_ADHOC BIT(2)
709#define STA_TYPE_WDS BIT(4)
710#define STA_TYPE_BC BIT(5)
711
712#define NETWORK_INFRA BIT(16)
713#define NETWORK_P2P BIT(17)
714#define NETWORK_IBSS BIT(18)
715#define NETWORK_WDS BIT(21)
716
717#define SCAN_FUNC_RANDOM_MAC BIT(0)
718#define SCAN_FUNC_SPLIT_SCAN BIT(5)
719
720#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
721#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
722#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
723#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
724#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
725#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
726#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
727
728#define CONN_STATE_DISCONNECT 0
729#define CONN_STATE_CONNECT 1
730#define CONN_STATE_PORT_SECURE 2
731
732/* HE MAC */
733#define STA_REC_HE_CAP_HTC BIT(0)
734#define STA_REC_HE_CAP_BQR BIT(1)
735#define STA_REC_HE_CAP_BSR BIT(2)
736#define STA_REC_HE_CAP_OM BIT(3)
737#define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
738/* HE PHY */
739#define STA_REC_HE_CAP_DUAL_BAND BIT(5)
740#define STA_REC_HE_CAP_LDPC BIT(6)
741#define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
742#define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
743/* STBC */
744#define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
745#define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
746#define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
747#define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
748/* GI */
749#define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
750#define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
751#define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
752#define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
753#define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
754/* 242 TONE */
755#define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
756#define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
757#define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
758
759#define PHY_MODE_A BIT(0)
760#define PHY_MODE_B BIT(1)
761#define PHY_MODE_G BIT(2)
762#define PHY_MODE_GN BIT(3)
763#define PHY_MODE_AN BIT(4)
764#define PHY_MODE_AC BIT(5)
765#define PHY_MODE_AX_24G BIT(6)
766#define PHY_MODE_AX_5G BIT(7)
767
768#define PHY_MODE_AX_6G BIT(0) /* phymode_ext */
769
770#define MODE_CCK BIT(0)
771#define MODE_OFDM BIT(1)
772#define MODE_HT BIT(2)
773#define MODE_VHT BIT(3)
774#define MODE_HE BIT(4)
775
776#define STA_CAP_WMM BIT(0)
777#define STA_CAP_SGI_20 BIT(4)
778#define STA_CAP_SGI_40 BIT(5)
779#define STA_CAP_TX_STBC BIT(6)
780#define STA_CAP_RX_STBC BIT(7)
781#define STA_CAP_VHT_SGI_80 BIT(16)
782#define STA_CAP_VHT_SGI_160 BIT(17)
783#define STA_CAP_VHT_TX_STBC BIT(18)
784#define STA_CAP_VHT_RX_STBC BIT(19)
785#define STA_CAP_VHT_LDPC BIT(23)
786#define STA_CAP_LDPC BIT(24)
787#define STA_CAP_HT BIT(26)
788#define STA_CAP_VHT BIT(27)
789#define STA_CAP_HE BIT(28)
790
791enum {
792 PHY_TYPE_HR_DSSS_INDEX = 0,
793 PHY_TYPE_ERP_INDEX,
794 PHY_TYPE_ERP_P2P_INDEX,
795 PHY_TYPE_OFDM_INDEX,
796 PHY_TYPE_HT_INDEX,
797 PHY_TYPE_VHT_INDEX,
798 PHY_TYPE_HE_INDEX,
799 PHY_TYPE_INDEX_NUM
800};
801
802#define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
803#define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
804#define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
805#define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
806#define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
807#define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
808
809#define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
810#define MT_WTBL_RATE_MCS GENMASK(5, 0)
811#define MT_WTBL_RATE_NSS GENMASK(12, 10)
812#define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
813#define MT_WTBL_RATE_GI GENMASK(3, 0)
814
815#define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
816#define MT_WTBL_W5_SHORT_GI_20 BIT(8)
817#define MT_WTBL_W5_SHORT_GI_40 BIT(9)
818#define MT_WTBL_W5_SHORT_GI_80 BIT(10)
819#define MT_WTBL_W5_SHORT_GI_160 BIT(11)
820#define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
821#define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
822#define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
823#define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
824
825enum {
826 WTBL_RESET_AND_SET = 1,
827 WTBL_SET,
828 WTBL_QUERY,
829 WTBL_RESET_ALL
830};
831
832enum {
833 MT_BA_TYPE_INVALID,
834 MT_BA_TYPE_ORIGINATOR,
835 MT_BA_TYPE_RECIPIENT
836};
837
838enum {
839 RST_BA_MAC_TID_MATCH,
840 RST_BA_MAC_MATCH,
841 RST_BA_NO_MATCH
842};
843
844enum {
845 DEV_INFO_ACTIVE,
846 DEV_INFO_MAX_NUM
847};
848
849#define MCU_UNI_CMD_EVENT BIT(1)
850#define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2)
851
852/* unified event table */
853enum {
854 MCU_UNI_EVENT_RESULT = 0x01,
855 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04,
856 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09,
857};
858
859/* event table */
860enum {
861 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
862 MCU_EVENT_FW_START = 0x01,
863 MCU_EVENT_GENERIC = 0x01,
864 MCU_EVENT_ACCESS_REG = 0x02,
865 MCU_EVENT_MT_PATCH_SEM = 0x04,
866 MCU_EVENT_REG_ACCESS = 0x05,
867 MCU_EVENT_LP_INFO = 0x07,
868 MCU_EVENT_SCAN_DONE = 0x0d,
869 MCU_EVENT_TX_DONE = 0x0f,
870 MCU_EVENT_ROC = 0x10,
871 MCU_EVENT_BSS_ABSENCE = 0x11,
872 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
873 MCU_EVENT_CH_PRIVILEGE = 0x18,
874 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
875 MCU_EVENT_DBG_MSG = 0x27,
876 MCU_EVENT_TXPWR = 0xd0,
877 MCU_EVENT_EXT = 0xed,
878 MCU_EVENT_RESTART_DL = 0xef,
879 MCU_EVENT_COREDUMP = 0xf0,
880};
881
882/* ext event table */
883enum {
884 MCU_EXT_EVENT_PS_SYNC = 0x5,
885 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
886 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
887 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
888 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
889 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
890 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
891 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
892};
893
894enum {
895 MCU_Q_QUERY,
896 MCU_Q_SET,
897 MCU_Q_RESERVED,
898 MCU_Q_NA
899};
900
901enum {
902 MCU_S2D_H2N,
903 MCU_S2D_C2N,
904 MCU_S2D_H2C,
905 MCU_S2D_H2CN,
906 MCU_S2D_H2WO
907};
908
909enum {
910 PATCH_NOT_DL_SEM_FAIL,
911 PATCH_IS_DL,
912 PATCH_NOT_DL_SEM_SUCCESS,
913 PATCH_REL_SEM_SUCCESS
914};
915
916enum {
917 FW_STATE_INITIAL,
918 FW_STATE_FW_DOWNLOAD,
919 FW_STATE_NORMAL_OPERATION,
920 FW_STATE_NORMAL_TRX,
921 FW_STATE_RDY = 7
922};
923
924enum {
925 CH_SWITCH_NORMAL = 0,
926 CH_SWITCH_SCAN = 3,
927 CH_SWITCH_MCC = 4,
928 CH_SWITCH_DFS = 5,
929 CH_SWITCH_BACKGROUND_SCAN_START = 6,
930 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
931 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
932 CH_SWITCH_SCAN_BYPASS_DPD = 9
933};
934
935enum {
936 THERMAL_SENSOR_TEMP_QUERY,
937 THERMAL_SENSOR_MANUAL_CTRL,
938 THERMAL_SENSOR_INFO_QUERY,
939 THERMAL_SENSOR_TASK_CTRL,
940};
941
942enum mcu_cipher_type {
943 MCU_CIPHER_NONE = 0,
944 MCU_CIPHER_WEP40,
945 MCU_CIPHER_WEP104,
946 MCU_CIPHER_WEP128,
947 MCU_CIPHER_TKIP,
948 MCU_CIPHER_AES_CCMP,
949 MCU_CIPHER_CCMP_256,
950 MCU_CIPHER_GCMP,
951 MCU_CIPHER_GCMP_256,
952 MCU_CIPHER_WAPI,
953 MCU_CIPHER_BIP_CMAC_128,
954};
955
956enum {
957 EE_MODE_EFUSE,
958 EE_MODE_BUFFER,
959};
960
961enum {
962 EE_FORMAT_BIN,
963 EE_FORMAT_WHOLE,
964 EE_FORMAT_MULTIPLE,
965};
966
967enum {
968 MCU_PHY_STATE_TX_RATE,
969 MCU_PHY_STATE_RX_RATE,
970 MCU_PHY_STATE_RSSI,
971 MCU_PHY_STATE_CONTENTION_RX_RATE,
972 MCU_PHY_STATE_OFDMLQ_CNINFO,
973};
974
975#define MCU_CMD_ACK BIT(0)
976#define MCU_CMD_UNI BIT(1)
977#define MCU_CMD_QUERY BIT(2)
978
979#define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
980 MCU_CMD_QUERY)
981#define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI)
982
983#define __MCU_CMD_FIELD_ID GENMASK(7, 0)
984#define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
985#define __MCU_CMD_FIELD_QUERY BIT(16)
986#define __MCU_CMD_FIELD_UNI BIT(17)
987#define __MCU_CMD_FIELD_CE BIT(18)
988#define __MCU_CMD_FIELD_WA BIT(19)
989#define __MCU_CMD_FIELD_WM BIT(20)
990
991#define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \
992 MCU_CMD_##_t)
993#define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
994 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
995 MCU_EXT_CMD_##_t))
996#define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
997#define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \
998 FIELD_PREP(__MCU_CMD_FIELD_ID, \
999 MCU_UNI_CMD_##_t))
1000#define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \
1001 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1002 MCU_CE_CMD_##_t))
1003#define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1004
1005#define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1006#define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1007#define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
1008 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1009 MCU_WA_PARAM_CMD_##_t))
1010
1011#define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1012 __MCU_CMD_FIELD_WM)
1013#define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1014 __MCU_CMD_FIELD_WA)
1015#define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \
1016 __MCU_CMD_FIELD_WA)
1017
1018enum {
1019 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1020 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1021 MCU_EXT_CMD_RF_TEST = 0x04,
1022 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1023 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1024 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1025 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1026 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1027 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1028 MCU_EXT_CMD_THERMAL_PROT = 0x23,
1029 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1030 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1031 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1032 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1033 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1034 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1035 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1036 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1037 MCU_EXT_CMD_ATE_CTRL = 0x3d,
1038 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1039 MCU_EXT_CMD_DBDC_CTRL = 0x45,
1040 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1041 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1042 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1043 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1044 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1045 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1046 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1047 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1048 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1049 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1050 MCU_EXT_CMD_TXDPD_CAL = 0x60,
1051 MCU_EXT_CMD_CAL_CACHE = 0x67,
1052 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1053 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1054 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1055 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
developerb11a5392022-03-31 00:34:47 +0800[diff] [blame]1056 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1057 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1058 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1059 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1060 MCU_EXT_CMD_MURU_CTRL = 0x9f,
1061 MCU_EXT_CMD_SET_SPR = 0xa8,
1062 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1063 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1064 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1065};
1066
1067enum {
1068 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1069 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1070 MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1071 MCU_UNI_CMD_EDCA = 0x04,
1072 MCU_UNI_CMD_SUSPEND = 0x05,
1073 MCU_UNI_CMD_OFFLOAD = 0x06,
1074 MCU_UNI_CMD_HIF_CTRL = 0x07,
1075 MCU_UNI_CMD_BAND_CONFIG = 0x08,
1076 MCU_UNI_CMD_WSYS_CONFIG = 0x0b,
1077 MCU_UNI_CMD_RX_HDR_TRANS = 0x12,
1078 MCU_UNI_CMD_RDD_CTRL = 0x19,
1079 MCU_UNI_CMD_GET_MIB_INFO = 0x22,
1080 MCU_UNI_CMD_SNIFFER = 0x24,
1081 MCU_UNI_CMD_TXPOWER = 0x2b,
1082 MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
1083 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
1084 MCU_UNI_CMD_VOW = 0x37,
1085};
1086
1087enum {
1088 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1089 MCU_CMD_FW_START_REQ = 0x02,
1090 MCU_CMD_INIT_ACCESS_REG = 0x3,
1091 MCU_CMD_NIC_POWER_CTRL = 0x4,
1092 MCU_CMD_PATCH_START_REQ = 0x05,
1093 MCU_CMD_PATCH_FINISH_REQ = 0x07,
1094 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1095 MCU_CMD_WA_PARAM = 0xc4,
1096 MCU_CMD_EXT_CID = 0xed,
1097 MCU_CMD_FW_SCATTER = 0xee,
1098 MCU_CMD_RESTART_DL_REQ = 0xef,
1099};
1100
1101/* offload mcu commands */
1102enum {
1103 MCU_CE_CMD_TEST_CTRL = 0x01,
1104 MCU_CE_CMD_START_HW_SCAN = 0x03,
1105 MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1106 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1107 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1108 MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1109 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1110 MCU_CE_CMD_SET_ROC = 0x1c,
1111 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1112 MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1113 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1114 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1115 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1116 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1117 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1118 MCU_CE_CMD_REG_WRITE = 0xc0,
1119 MCU_CE_CMD_REG_READ = 0xc0,
1120 MCU_CE_CMD_CHIP_CONFIG = 0xca,
1121 MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1122 MCU_CE_CMD_GET_WTBL = 0xcd,
1123 MCU_CE_CMD_GET_TXPWR = 0xd0,
1124};
1125
1126enum {
1127 PATCH_SEM_RELEASE,
1128 PATCH_SEM_GET
1129};
1130
1131enum {
1132 UNI_BSS_INFO_BASIC = 0,
1133 UNI_BSS_INFO_RA = 1,
1134 UNI_BSS_INFO_RLM = 2,
1135 UNI_BSS_INFO_BSS_COLOR = 4,
1136 UNI_BSS_INFO_HE_BASIC = 5,
1137 UNI_BSS_INFO_BCN_CONTENT = 7,
1138 UNI_BSS_INFO_BCN_CSA = 8,
1139 UNI_BSS_INFO_BCN_BCC = 9,
1140 UNI_BSS_INFO_BCN_MBSSID = 10,
1141 UNI_BSS_INFO_RATE = 11,
1142 UNI_BSS_INFO_QBSS = 15,
1143 UNI_BSS_INFO_SEC = 16,
1144 UNI_BSS_INFO_TXCMD = 18,
1145 UNI_BSS_INFO_UAPSD = 19,
1146 UNI_BSS_INFO_PS = 21,
1147 UNI_BSS_INFO_BCNFT = 22,
1148 UNI_BSS_INFO_MLD = 26,
1149};
1150
1151enum {
1152 MCU_EDCA_AC_PARAM = 0,
1153};
1154
1155enum {
1156 UNI_OFFLOAD_OFFLOAD_ARP,
1157 UNI_OFFLOAD_OFFLOAD_ND,
1158 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1159 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1160};
1161
1162enum {
1163 MT_NIC_CAP_TX_RESOURCE,
1164 MT_NIC_CAP_TX_EFUSE_ADDR,
1165 MT_NIC_CAP_COEX,
1166 MT_NIC_CAP_SINGLE_SKU,
1167 MT_NIC_CAP_CSUM_OFFLOAD,
1168 MT_NIC_CAP_HW_VER,
1169 MT_NIC_CAP_SW_VER,
1170 MT_NIC_CAP_MAC_ADDR,
1171 MT_NIC_CAP_PHY,
1172 MT_NIC_CAP_MAC,
1173 MT_NIC_CAP_FRAME_BUF,
1174 MT_NIC_CAP_BEAM_FORM,
1175 MT_NIC_CAP_LOCATION,
1176 MT_NIC_CAP_MUMIMO,
1177 MT_NIC_CAP_BUFFER_MODE_INFO,
1178 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1179 MT_NIC_CAP_ANTSWP = 0x16,
1180 MT_NIC_CAP_WFDMA_REALLOC,
1181 MT_NIC_CAP_6G,
1182};
1183
1184#define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
1185#define UNI_WOW_DETECT_TYPE_ANY BIT(1)
1186#define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
1187#define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
1188#define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
1189#define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
1190#define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
1191
1192enum {
1193 UNI_SUSPEND_MODE_SETTING,
1194 UNI_SUSPEND_WOW_CTRL,
1195 UNI_SUSPEND_WOW_GPIO_PARAM,
1196 UNI_SUSPEND_WOW_WAKEUP_PORT,
1197 UNI_SUSPEND_WOW_PATTERN,
1198};
1199
1200enum {
1201 WOW_USB = 1,
1202 WOW_PCIE = 2,
1203 WOW_GPIO = 3,
1204};
1205
1206struct mt76_connac_bss_basic_tlv {
1207 __le16 tag;
1208 __le16 len;
1209 u8 active;
1210 u8 omac_idx;
1211 u8 hw_bss_idx;
1212 u8 band_idx;
1213 __le32 conn_type;
1214 u8 conn_state;
1215 u8 wmm_idx;
1216 u8 bssid[ETH_ALEN];
1217 __le16 bmc_tx_wlan_idx;
1218 __le16 bcn_interval;
1219 u8 dtim_period;
1220 u8 phymode; /* bit(0): A
1221 * bit(1): B
1222 * bit(2): G
1223 * bit(3): GN
1224 * bit(4): AN
1225 * bit(5): AC
1226 * bit(6): AX2
1227 * bit(7): AX5
1228 * bit(8): AX6
1229 */
1230 __le16 sta_idx;
1231 __le16 nonht_basic_phy;
1232 u8 phymode_ext; /* bit(0) AX_6G */
1233 u8 mlo_link_idx;
1234} __packed;
1235
1236struct mt76_connac_bss_qos_tlv {
1237 __le16 tag;
1238 __le16 len;
1239 u8 qos;
1240 u8 pad[3];
1241} __packed;
1242
1243struct mt76_connac_beacon_loss_event {
1244 u8 bss_idx;
1245 u8 reason;
1246 u8 pad[2];
1247} __packed;
1248
1249struct mt76_connac_mcu_bss_event {
1250 u8 bss_idx;
1251 u8 is_absent;
1252 u8 free_quota;
1253 u8 pad;
1254} __packed;
1255
1256struct mt76_connac_mcu_scan_ssid {
1257 __le32 ssid_len;
1258 u8 ssid[IEEE80211_MAX_SSID_LEN];
1259} __packed;
1260
1261struct mt76_connac_mcu_scan_channel {
1262 u8 band; /* 1: 2.4GHz
1263 * 2: 5.0GHz
1264 * Others: Reserved
1265 */
1266 u8 channel_num;
1267} __packed;
1268
1269struct mt76_connac_mcu_scan_match {
1270 __le32 rssi_th;
1271 u8 ssid[IEEE80211_MAX_SSID_LEN];
1272 u8 ssid_len;
1273 u8 rsv[3];
1274} __packed;
1275
1276struct mt76_connac_hw_scan_req {
1277 u8 seq_num;
1278 u8 bss_idx;
1279 u8 scan_type; /* 0: PASSIVE SCAN
1280 * 1: ACTIVE SCAN
1281 */
1282 u8 ssid_type; /* BIT(0) wildcard SSID
1283 * BIT(1) P2P wildcard SSID
1284 * BIT(2) specified SSID + wildcard SSID
1285 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1286 */
1287 u8 ssids_num;
1288 u8 probe_req_num; /* Number of probe request for each SSID */
1289 u8 scan_func; /* BIT(0) Enable random MAC scan
1290 * BIT(1) Disable DBDC scan type 1~3.
1291 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1292 */
1293 u8 version; /* 0: Not support fields after ies.
1294 * 1: Support fields after ies.
1295 */
1296 struct mt76_connac_mcu_scan_ssid ssids[4];
1297 __le16 probe_delay_time;
1298 __le16 channel_dwell_time; /* channel Dwell interval */
1299 __le16 timeout_value;
1300 u8 channel_type; /* 0: Full channels
1301 * 1: Only 2.4GHz channels
1302 * 2: Only 5GHz channels
1303 * 3: P2P social channel only (channel #1, #6 and #11)
1304 * 4: Specified channels
1305 * Others: Reserved
1306 */
1307 u8 channels_num; /* valid when channel_type is 4 */
1308 /* valid when channels_num is set */
1309 struct mt76_connac_mcu_scan_channel channels[32];
1310 __le16 ies_len;
1311 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1312 /* following fields are valid if version > 0 */
1313 u8 ext_channels_num;
1314 u8 ext_ssids_num;
1315 __le16 channel_min_dwell_time;
1316 struct mt76_connac_mcu_scan_channel ext_channels[32];
1317 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1318 u8 bssid[ETH_ALEN];
1319 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1320 u8 pad[63];
1321 u8 ssid_type_ext;
1322} __packed;
1323
1324#define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
1325
1326struct mt76_connac_hw_scan_done {
1327 u8 seq_num;
1328 u8 sparse_channel_num;
1329 struct mt76_connac_mcu_scan_channel sparse_channel;
1330 u8 complete_channel_num;
1331 u8 current_state;
1332 u8 version;
1333 u8 pad;
1334 __le32 beacon_scan_num;
1335 u8 pno_enabled;
1336 u8 pad2[3];
1337 u8 sparse_channel_valid_num;
1338 u8 pad3[3];
1339 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1340 /* idle format for channel_idle_time
1341 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1342 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1343 * 2: dwell time (16us)
1344 */
1345 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1346 /* beacon and probe response count */
1347 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1348 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1349 __le32 beacon_2g_num;
1350 __le32 beacon_5g_num;
1351} __packed;
1352
1353struct mt76_connac_sched_scan_req {
1354 u8 version;
1355 u8 seq_num;
1356 u8 stop_on_match;
1357 u8 ssids_num;
1358 u8 match_num;
1359 u8 pad;
1360 __le16 ie_len;
1361 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1362 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1363 u8 channel_type;
1364 u8 channels_num;
1365 u8 intervals_num;
1366 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1367 struct mt76_connac_mcu_scan_channel channels[64];
1368 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1369 union {
1370 struct {
1371 u8 random_mac[ETH_ALEN];
1372 u8 pad2[58];
1373 } mt7663;
1374 struct {
1375 u8 bss_idx;
1376 u8 pad1[3];
1377 __le32 delay;
1378 u8 pad2[12];
1379 u8 random_mac[ETH_ALEN];
1380 u8 pad3[38];
1381 } mt7921;
1382 };
1383} __packed;
1384
1385struct mt76_connac_sched_scan_done {
1386 u8 seq_num;
1387 u8 status; /* 0: ssid found */
1388 __le16 pad;
1389} __packed;
1390
1391struct bss_info_uni_bss_color {
1392 __le16 tag;
1393 __le16 len;
1394 u8 enable;
1395 u8 bss_color;
1396 u8 rsv[2];
1397} __packed;
1398
1399struct bss_info_uni_he {
1400 __le16 tag;
1401 __le16 len;
1402 __le16 he_rts_thres;
1403 u8 he_pe_duration;
1404 u8 su_disable;
1405 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1406 u8 rsv[2];
1407} __packed;
1408
1409struct mt76_connac_gtk_rekey_tlv {
1410 __le16 tag;
1411 __le16 len;
1412 u8 kek[NL80211_KEK_LEN];
1413 u8 kck[NL80211_KCK_LEN];
1414 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1415 u8 rekey_mode; /* 0: rekey offload enable
1416 * 1: rekey offload disable
1417 * 2: rekey update
1418 */
1419 u8 keyid;
1420 u8 option; /* 1: rekey data update without enabling offload */
1421 u8 pad[1];
1422 __le32 proto; /* WPA-RSN-WAPI-OPSN */
1423 __le32 pairwise_cipher;
1424 __le32 group_cipher;
1425 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1426 __le32 mgmt_group_cipher;
1427 u8 reserverd[4];
1428} __packed;
1429
1430#define MT76_CONNAC_WOW_MASK_MAX_LEN 16
1431#define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
1432
1433struct mt76_connac_wow_pattern_tlv {
1434 __le16 tag;
1435 __le16 len;
1436 u8 index; /* pattern index */
1437 u8 enable; /* 0: disable
1438 * 1: enable
1439 */
1440 u8 data_len; /* pattern length */
1441 u8 pad;
1442 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1443 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1444 u8 rsv[4];
1445} __packed;
1446
1447struct mt76_connac_wow_ctrl_tlv {
1448 __le16 tag;
1449 __le16 len;
1450 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1451 * 0x2: PM_WOWLAN_REQ_STOP
1452 * 0x3: PM_WOWLAN_PARAM_CLEAR
1453 */
1454 u8 trigger; /* 0: NONE
1455 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1456 * BIT(1): NL80211_WOWLAN_TRIG_ANY
1457 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1458 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1459 * BIT(4): BEACON_LOST
1460 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1461 */
1462 u8 wakeup_hif; /* 0x0: HIF_SDIO
1463 * 0x1: HIF_USB
1464 * 0x2: HIF_PCIE
1465 * 0x3: HIF_GPIO
1466 */
1467 u8 pad;
1468 u8 rsv[4];
1469} __packed;
1470
1471struct mt76_connac_wow_gpio_param_tlv {
1472 __le16 tag;
1473 __le16 len;
1474 u8 gpio_pin;
1475 u8 trigger_lvl;
1476 u8 pad[2];
1477 __le32 gpio_interval;
1478 u8 rsv[4];
1479} __packed;
1480
1481struct mt76_connac_arpns_tlv {
1482 __le16 tag;
1483 __le16 len;
1484 u8 mode;
1485 u8 ips_num;
1486 u8 option;
1487 u8 pad[1];
1488} __packed;
1489
1490struct mt76_connac_suspend_tlv {
1491 __le16 tag;
1492 __le16 len;
1493 u8 enable; /* 0: suspend mode disabled
1494 * 1: suspend mode enabled
1495 */
1496 u8 mdtim; /* LP parameter */
1497 u8 wow_suspend; /* 0: update by origin policy
1498 * 1: update by wow dtim
1499 */
1500 u8 pad[5];
1501} __packed;
1502
1503enum mt76_sta_info_state {
1504 MT76_STA_INFO_STATE_NONE,
1505 MT76_STA_INFO_STATE_AUTH,
1506 MT76_STA_INFO_STATE_ASSOC
1507};
1508
1509struct mt76_sta_cmd_info {
1510 struct ieee80211_sta *sta;
1511 struct mt76_wcid *wcid;
1512
1513 struct ieee80211_vif *vif;
1514
1515 bool offload_fw;
1516 bool enable;
1517 bool newly;
1518 int cmd;
1519 u8 rcpi;
1520 u8 state;
1521};
1522
1523#define MT_SKU_POWER_LIMIT 161
1524
1525struct mt76_connac_sku_tlv {
1526 u8 channel;
1527 s8 pwr_limit[MT_SKU_POWER_LIMIT];
1528} __packed;
1529
1530struct mt76_connac_tx_power_limit_tlv {
1531 /* DW0 - common info*/
1532 u8 ver;
1533 u8 pad0;
1534 __le16 len;
1535 /* DW1 - cmd hint */
1536 u8 n_chan; /* # channel */
1537 u8 band; /* 2.4GHz - 5GHz - 6GHz */
1538 u8 last_msg;
1539 u8 pad1;
1540 /* DW3 */
1541 u8 alpha2[4]; /* regulatory_request.alpha2 */
1542 u8 pad2[32];
1543} __packed;
1544
1545struct mt76_connac_config {
1546 __le16 id;
1547 u8 type;
1548 u8 resp_type;
1549 __le16 data_size;
1550 __le16 resv;
1551 u8 data[320];
1552} __packed;
1553
1554static inline enum mcu_cipher_type
1555mt76_connac_mcu_get_cipher(int cipher)
1556{
1557 switch (cipher) {
1558 case WLAN_CIPHER_SUITE_WEP40:
1559 return MCU_CIPHER_WEP40;
1560 case WLAN_CIPHER_SUITE_WEP104:
1561 return MCU_CIPHER_WEP104;
1562 case WLAN_CIPHER_SUITE_TKIP:
1563 return MCU_CIPHER_TKIP;
1564 case WLAN_CIPHER_SUITE_AES_CMAC:
1565 return MCU_CIPHER_BIP_CMAC_128;
1566 case WLAN_CIPHER_SUITE_CCMP:
1567 return MCU_CIPHER_AES_CCMP;
1568 case WLAN_CIPHER_SUITE_CCMP_256:
1569 return MCU_CIPHER_CCMP_256;
1570 case WLAN_CIPHER_SUITE_GCMP:
1571 return MCU_CIPHER_GCMP;
1572 case WLAN_CIPHER_SUITE_GCMP_256:
1573 return MCU_CIPHER_GCMP_256;
1574 case WLAN_CIPHER_SUITE_SMS4:
1575 return MCU_CIPHER_WAPI;
1576 default:
1577 return MCU_CIPHER_NONE;
1578 }
1579}
1580
1581static inline u32
1582mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1583{
1584 u32 ret = 0;
1585
1586 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1587 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1588 if (is_mt7921(dev))
1589 ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1590 DL_CONFIG_ENCRY_MODE_SEL : 0;
1591 ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1592 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1593 ret |= DL_MODE_NEED_RSP;
1594 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1595
1596 return ret;
1597}
1598
1599#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1600#define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1601
1602static inline void
1603mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1604 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1605{
1606 *wlan_idx_hi = 0;
1607
1608 if (!is_connac_v1(dev)) {
1609 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1610 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1611 } else {
1612 *wlan_idx_lo = wcid ? wcid->idx : 0;
1613 }
1614}
1615
1616struct sk_buff *
1617__mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1618 struct mt76_wcid *wcid, int len);
1619static inline struct sk_buff *
1620mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1621 struct mt76_wcid *wcid)
1622{
1623 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1624 MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1625}
1626
1627struct wtbl_req_hdr *
1628mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1629 int cmd, void *sta_wtbl, struct sk_buff **skb);
1630struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1631 int len, void *sta_ntlv,
1632 void *sta_wtbl);
1633static inline struct tlv *
1634mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1635{
1636 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1637}
1638
1639int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1640int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1641void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
1642 struct ieee80211_vif *vif,
1643 struct ieee80211_sta *sta, bool enable,
1644 bool newly);
1645void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1646 struct ieee80211_vif *vif,
1647 struct ieee80211_sta *sta, void *sta_wtbl,
1648 void *wtbl_tlv);
1649void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1650 struct ieee80211_vif *vif,
1651 struct mt76_wcid *wcid,
1652 void *sta_wtbl, void *wtbl_tlv);
1653int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1654 struct ieee80211_vif *vif,
1655 struct mt76_wcid *wcid, int cmd);
1656int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1657 struct ieee80211_vif *vif,
1658 struct ieee80211_sta *sta);
1659u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif,
1660 enum nl80211_band band, struct ieee80211_sta *sta);
1661void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1662 struct ieee80211_sta *sta,
1663 struct ieee80211_vif *vif,
1664 u8 rcpi, u8 state);
1665void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1666 struct ieee80211_sta *sta, void *sta_wtbl,
1667 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1668void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1669 struct ieee80211_ampdu_params *params,
1670 bool enable, bool tx, void *sta_wtbl,
1671 void *wtbl_tlv);
1672void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1673 struct ieee80211_ampdu_params *params,
1674 bool enable, bool tx);
1675int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1676 struct ieee80211_vif *vif,
1677 struct mt76_wcid *wcid,
1678 bool enable);
1679int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1680 struct ieee80211_ampdu_params *params,
1681 int cmd, bool enable, bool tx);
1682int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1683 struct ieee80211_vif *vif,
1684 struct mt76_wcid *wcid,
1685 bool enable);
1686int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1687 struct mt76_sta_cmd_info *info);
1688void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1689 struct ieee80211_vif *vif);
1690int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1691int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1692 bool hdr_trans);
1693int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1694 u32 mode);
1695int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1696int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1697int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1698int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1699
1700int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1701 struct ieee80211_scan_request *scan_req);
1702int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1703 struct ieee80211_vif *vif);
1704int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1705 struct ieee80211_vif *vif,
1706 struct cfg80211_sched_scan_request *sreq);
1707int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1708 struct ieee80211_vif *vif,
1709 bool enable);
1710int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1711 struct mt76_vif *vif,
1712 struct ieee80211_bss_conf *info);
1713int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1714 struct ieee80211_vif *vif,
1715 struct cfg80211_gtk_rekey_data *key);
1716int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1717void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1718 struct ieee80211_vif *vif);
1719int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1720 enum ieee80211_sta_state old_state,
1721 enum ieee80211_sta_state new_state);
1722int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1723int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1724void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1725 struct mt76_connac_coredump *coredump);
1726int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1727int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1728 struct ieee80211_vif *vif);
1729u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1730void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1731
1732const struct ieee80211_sta_he_cap *
1733mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1734u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1735 enum nl80211_band band, struct ieee80211_sta *sta);
1736
1737int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
1738 struct mt76_connac_sta_key_conf *sta_key_conf,
1739 struct ieee80211_key_conf *key, int mcu_cmd,
1740 struct mt76_wcid *wcid, enum set_key_cmd cmd);
1741
1742void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
1743void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
1744 struct ieee80211_vif *vif);
1745int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
1746 struct ieee80211_vif *vif,
1747 struct ieee80211_sta *sta,
1748 struct mt76_phy *phy, u16 wlan_idx,
1749 bool enable);
1750void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
1751 struct ieee80211_sta *sta);
1752void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
1753 struct ieee80211_sta *sta,
1754 void *sta_wtbl, void *wtbl_tlv);
1755int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
1756int mt76_connac_mcu_restart(struct mt76_dev *dev);
1757int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
1758 u8 rx_sel, u8 val);
1759#endif /* __MT76_CONNAC_MCU_H */