developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988C GSW 10G SFP SPIM-NAND RFB"; |
| 12 | compatible = "mediatek,mt7988c-gsw-10g-sfp-spim-snand", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000"; |
| 19 | }; |
| 20 | |
| 21 | gsw: gsw@0 { |
| 22 | compatible = "mediatek,mt753x"; |
| 23 | mediatek,sysctrl = <ðwarp>; |
| 24 | #address-cells = <1>; |
| 25 | #size-cells = <0>; |
| 26 | }; |
| 27 | |
| 28 | memory { |
| 29 | reg = <0 0x40000000 0 0x10000000>; |
| 30 | }; |
| 31 | |
| 32 | nmbm_spim_nand { |
| 33 | compatible = "generic,nmbm"; |
| 34 | |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <1>; |
| 37 | |
| 38 | lower-mtd-device = <&spi_nand>; |
| 39 | forced-create; |
| 40 | |
| 41 | partitions { |
| 42 | compatible = "fixed-partitions"; |
| 43 | #address-cells = <1>; |
| 44 | #size-cells = <1>; |
| 45 | |
| 46 | partition@0 { |
| 47 | label = "BL2"; |
| 48 | reg = <0x00000 0x0100000>; |
| 49 | read-only; |
| 50 | }; |
| 51 | |
| 52 | partition@100000 { |
| 53 | label = "u-boot-env"; |
| 54 | reg = <0x0100000 0x0080000>; |
| 55 | }; |
| 56 | |
| 57 | factory: partition@180000 { |
| 58 | label = "Factory"; |
| 59 | reg = <0x180000 0x0400000>; |
| 60 | }; |
| 61 | |
| 62 | partition@580000 { |
| 63 | label = "FIP"; |
| 64 | reg = <0x580000 0x0200000>; |
| 65 | }; |
| 66 | |
| 67 | partition@780000 { |
| 68 | label = "ubi"; |
| 69 | reg = <0x780000 0x7080000>; |
| 70 | }; |
| 71 | }; |
| 72 | }; |
| 73 | |
| 74 | wsys_adie: wsys_adie@0 { |
| 75 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 76 | compatible = "mediatek,rebb-mt7988-adie"; |
| 77 | adie_id = <7976>; |
| 78 | sku_type = <3000>; |
| 79 | }; |
| 80 | |
| 81 | sfp_esp0: sfp@0 { |
| 82 | compatible = "sff,sfp"; |
| 83 | i2c-bus = <&i2c1>; |
| 84 | mod-def0-gpios = <&pio 0 1>; |
developer | 85e9390 | 2023-02-10 13:41:42 +0800 | [diff] [blame] | 85 | los-gpios = <&pio 30 0>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 86 | tx-disable-gpios = <&pio 29 0>; |
| 87 | }; |
| 88 | }; |
| 89 | |
| 90 | &fan { |
| 91 | pwms = <&pwm 0 50000 0>; |
| 92 | status = "okay"; |
| 93 | }; |
| 94 | |
| 95 | &i2c0 { |
| 96 | pinctrl-names = "default"; |
| 97 | pinctrl-0 = <&i2c0_pins>; |
| 98 | status = "okay"; |
| 99 | |
| 100 | rt5190a_64: rt5190a@64 { |
| 101 | compatible = "richtek,rt5190a"; |
| 102 | reg = <0x64>; |
| 103 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 104 | vin2-supply = <&rt5190_buck1>; |
| 105 | vin3-supply = <&rt5190_buck1>; |
| 106 | vin4-supply = <&rt5190_buck1>; |
| 107 | |
| 108 | regulators { |
| 109 | rt5190_buck1: buck1 { |
| 110 | regulator-name = "rt5190a-buck1"; |
| 111 | regulator-min-microvolt = <5090000>; |
| 112 | regulator-max-microvolt = <5090000>; |
| 113 | regulator-allowed-modes = |
| 114 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 115 | regulator-boot-on; |
| 116 | }; |
| 117 | buck2 { |
| 118 | regulator-name = "vcore"; |
| 119 | regulator-min-microvolt = <600000>; |
| 120 | regulator-max-microvolt = <1400000>; |
| 121 | regulator-boot-on; |
| 122 | }; |
| 123 | buck3 { |
| 124 | regulator-name = "proc"; |
| 125 | regulator-min-microvolt = <600000>; |
| 126 | regulator-max-microvolt = <1400000>; |
| 127 | regulator-boot-on; |
| 128 | }; |
| 129 | buck4 { |
| 130 | regulator-name = "rt5190a-buck4"; |
| 131 | regulator-min-microvolt = <850000>; |
| 132 | regulator-max-microvolt = <850000>; |
| 133 | regulator-allowed-modes = |
| 134 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 135 | regulator-boot-on; |
| 136 | }; |
| 137 | ldo { |
| 138 | regulator-name = "rt5190a-ldo"; |
| 139 | regulator-min-microvolt = <1200000>; |
| 140 | regulator-max-microvolt = <1200000>; |
| 141 | regulator-boot-on; |
| 142 | }; |
| 143 | }; |
| 144 | }; |
| 145 | }; |
| 146 | |
| 147 | &i2c1 { |
| 148 | pinctrl-names = "default"; |
| 149 | pinctrl-0 = <&i2c1_pins>; |
| 150 | status = "okay"; |
| 151 | }; |
| 152 | |
| 153 | &pwm { |
| 154 | status = "okay"; |
| 155 | }; |
| 156 | |
| 157 | &uart0 { |
| 158 | status = "okay"; |
| 159 | }; |
| 160 | |
| 161 | &spi0 { |
| 162 | pinctrl-names = "default"; |
| 163 | pinctrl-0 = <&spi0_flash_pins>; |
| 164 | status = "okay"; |
| 165 | |
| 166 | spi_nand: spi_nand@0 { |
| 167 | #address-cells = <1>; |
| 168 | #size-cells = <1>; |
| 169 | compatible = "spi-nand"; |
| 170 | spi-cal-enable; |
| 171 | spi-cal-mode = "read-data"; |
| 172 | spi-cal-datalen = <7>; |
| 173 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 174 | spi-cal-addrlen = <5>; |
| 175 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 176 | reg = <0>; |
| 177 | spi-max-frequency = <52000000>; |
developer | 5fb8060 | 2023-05-02 18:54:53 +0800 | [diff] [blame] | 178 | spi-tx-bus-width = <4>; |
| 179 | spi-rx-bus-width = <4>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 180 | }; |
| 181 | }; |
| 182 | |
| 183 | &spi1 { |
| 184 | pinctrl-names = "default"; |
| 185 | /* pin shared with snfi */ |
| 186 | pinctrl-0 = <&spic_pins>; |
| 187 | status = "disabled"; |
| 188 | }; |
| 189 | |
| 190 | &pcie0 { |
| 191 | pinctrl-names = "default"; |
| 192 | pinctrl-0 = <&pcie0_pins>; |
| 193 | status = "okay"; |
| 194 | }; |
| 195 | |
| 196 | &pcie1 { |
| 197 | pinctrl-names = "default"; |
| 198 | pinctrl-0 = <&pcie1_pins>; |
| 199 | status = "disabled"; |
| 200 | }; |
| 201 | |
| 202 | &pcie2 { |
| 203 | pinctrl-names = "default"; |
| 204 | pinctrl-0 = <&pcie2_pins>; |
| 205 | status = "disabled"; |
| 206 | }; |
| 207 | |
| 208 | &pcie3 { |
| 209 | pinctrl-names = "default"; |
| 210 | pinctrl-0 = <&pcie3_pins>; |
| 211 | status = "okay"; |
| 212 | }; |
| 213 | |
| 214 | &pio { |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 215 | gbe0_led0_pins: gbe0-pins { |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 216 | mux { |
| 217 | function = "led"; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 218 | groups = "gbe0_led0"; |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 219 | }; |
| 220 | }; |
| 221 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 222 | gbe1_led0_pins: gbe1-pins { |
| 223 | mux { |
| 224 | function = "led"; |
| 225 | groups = "gbe1_led0"; |
| 226 | }; |
| 227 | }; |
| 228 | |
| 229 | gbe2_led0_pins: gbe2-pins { |
| 230 | mux { |
| 231 | function = "led"; |
| 232 | groups = "gbe2_led0"; |
| 233 | }; |
| 234 | }; |
| 235 | |
| 236 | gbe3_led0_pins: gbe3-pins { |
| 237 | mux { |
| 238 | function = "led"; |
| 239 | groups = "gbe3_led0"; |
| 240 | }; |
| 241 | }; |
| 242 | |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 243 | i2p5gbe_led0_pins: 2p5gbe-pins { |
| 244 | mux { |
| 245 | function = "led"; |
| 246 | groups = "2p5gbe_led0"; |
| 247 | }; |
| 248 | }; |
| 249 | |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 250 | i2c0_pins: i2c0-pins-g0 { |
| 251 | mux { |
| 252 | function = "i2c"; |
| 253 | groups = "i2c0_1"; |
| 254 | }; |
| 255 | }; |
| 256 | |
| 257 | i2c1_pins: i2c1-pins-g0 { |
| 258 | mux { |
| 259 | function = "i2c"; |
| 260 | groups = "i2c1_sfp"; |
| 261 | }; |
| 262 | }; |
| 263 | |
| 264 | pcie0_pins: pcie0-pins { |
| 265 | mux { |
| 266 | function = "pcie"; |
| 267 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 268 | "pcie_wake_n0_0"; |
| 269 | }; |
| 270 | }; |
| 271 | |
| 272 | pcie1_pins: pcie1-pins { |
| 273 | mux { |
| 274 | function = "pcie"; |
| 275 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 276 | "pcie_wake_n1_0"; |
| 277 | }; |
| 278 | }; |
| 279 | |
| 280 | pcie2_pins: pcie2-pins { |
| 281 | mux { |
| 282 | function = "pcie"; |
| 283 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 284 | "pcie_wake_n2_0"; |
| 285 | }; |
| 286 | }; |
| 287 | |
| 288 | pcie3_pins: pcie3-pins { |
| 289 | mux { |
| 290 | function = "pcie"; |
| 291 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 292 | "pcie_wake_n3_0"; |
| 293 | }; |
| 294 | }; |
| 295 | |
| 296 | spi0_flash_pins: spi0-pins { |
| 297 | mux { |
| 298 | function = "spi"; |
| 299 | groups = "spi0", "spi0_wp_hold"; |
| 300 | }; |
| 301 | }; |
| 302 | |
| 303 | spic_pins: spi1-pins { |
| 304 | mux { |
| 305 | function = "spi"; |
developer | 1ceb26a | 2023-02-16 15:43:43 +0800 | [diff] [blame] | 306 | groups = "spi1"; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 307 | }; |
| 308 | }; |
| 309 | }; |
| 310 | |
| 311 | &watchdog { |
| 312 | status = "disabled"; |
| 313 | }; |
| 314 | |
| 315 | ð { |
| 316 | status = "okay"; |
| 317 | |
| 318 | gmac0: mac@0 { |
| 319 | compatible = "mediatek,eth-mac"; |
| 320 | reg = <0>; |
| 321 | mac-type = "xgdm"; |
| 322 | phy-mode = "10gbase-kr"; |
| 323 | |
| 324 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 325 | speed = <10000>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 326 | full-duplex; |
| 327 | pause; |
| 328 | }; |
| 329 | }; |
| 330 | |
| 331 | gmac1: mac@1 { |
| 332 | compatible = "mediatek,eth-mac"; |
| 333 | reg = <1>; |
| 334 | mac-type = "xgdm"; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 335 | phy-mode = "xgmii"; |
| 336 | phy-handle = <&phy0>; |
| 337 | }; |
| 338 | |
| 339 | gmac2: mac@2 { |
| 340 | compatible = "mediatek,eth-mac"; |
| 341 | reg = <2>; |
| 342 | mac-type = "xgdm"; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 343 | phy-mode = "10gbase-kr"; |
| 344 | managed = "in-band-status"; |
| 345 | sfp = <&sfp_esp0>; |
| 346 | }; |
| 347 | |
| 348 | mdio: mdio-bus { |
| 349 | #address-cells = <1>; |
| 350 | #size-cells = <0>; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 351 | |
| 352 | phy0: ethernet-phy@0 { |
developer | 813ffc4 | 2023-05-17 13:39:48 +0800 | [diff] [blame^] | 353 | pinctrl-names = "i2p5gbe-led"; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 354 | pinctrl-0 = <&i2p5gbe_led0_pins>; |
| 355 | reg = <15>; |
| 356 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 357 | phy-mode = "xgmii"; |
| 358 | }; |
| 359 | |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 360 | }; |
| 361 | }; |
| 362 | |
| 363 | &hnat { |
| 364 | mtketh-wan = "eth1"; |
| 365 | mtketh-lan = "eth0"; |
| 366 | mtketh-lan2 = "eth2"; |
| 367 | mtketh-max-gmac = <3>; |
| 368 | status = "okay"; |
| 369 | }; |
| 370 | |
| 371 | &gsw { |
| 372 | mediatek,mdio = <&mdio>; |
| 373 | mediatek,portmap = "llllw"; |
| 374 | mediatek,mdio_master_pinmux = <1>; |
| 375 | interrupt-parent = <&gic>; |
| 376 | interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
| 377 | status = "okay"; |
| 378 | |
| 379 | port6: port@6 { |
| 380 | compatible = "mediatek,mt753x-port"; |
| 381 | mediatek,ssc-on; |
| 382 | phy-mode = "10gbase-kr"; |
| 383 | reg = <6>; |
| 384 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 385 | speed = <10000>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 386 | full-duplex; |
| 387 | }; |
| 388 | }; |
| 389 | |
| 390 | mdio1: mdio-bus { |
| 391 | #address-cells = <1>; |
| 392 | #size-cells = <0>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 393 | |
| 394 | gsw_phy0: ethernet-phy@0 { |
| 395 | compatible = "ethernet-phy-id03a2.9481"; |
| 396 | reg = <0>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 397 | pinctrl-names = "gbe-led"; |
| 398 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 399 | nvmem-cells = <&phy_calibration_p0>; |
| 400 | nvmem-cell-names = "phy-cal-data"; |
| 401 | }; |
| 402 | |
| 403 | gsw_phy1: ethernet-phy@1 { |
| 404 | compatible = "ethernet-phy-id03a2.9481"; |
| 405 | reg = <1>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 406 | pinctrl-names = "gbe-led"; |
| 407 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 408 | nvmem-cells = <&phy_calibration_p1>; |
| 409 | nvmem-cell-names = "phy-cal-data"; |
| 410 | }; |
| 411 | |
| 412 | gsw_phy2: ethernet-phy@2 { |
| 413 | compatible = "ethernet-phy-id03a2.9481"; |
| 414 | reg = <2>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 415 | pinctrl-names = "gbe-led"; |
| 416 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 417 | nvmem-cells = <&phy_calibration_p2>; |
| 418 | nvmem-cell-names = "phy-cal-data"; |
| 419 | }; |
| 420 | |
| 421 | gsw_phy3: ethernet-phy@3 { |
| 422 | compatible = "ethernet-phy-id03a2.9481"; |
| 423 | reg = <3>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 424 | pinctrl-names = "gbe-led"; |
| 425 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 426 | nvmem-cells = <&phy_calibration_p3>; |
| 427 | nvmem-cell-names = "phy-cal-data"; |
| 428 | }; |
| 429 | }; |
| 430 | }; |