| commit | 5fb806042aea68ef740a06269022c27bd9ad081c | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue May 02 18:54:53 2023 +0800 |
| committer | developer <developer@mediatek.com> | Wed May 17 13:36:30 2023 +0800 |
| tree | a62fbeb9b2d8ae132d2c6d2a1b52c1e8d88ad3d2 | |
| parent | 329c5c73eb4a0c08ba90caabf1c524fcf7f59077 [diff] [blame] |
[][kernel][common][spi][spi-mt65xx: Fix dual/quad mode for IPM design] [Description] Fix the issue of dts buswidth cannot be applied properly in spi-mt65xx. (1) Fix the name of buswidth to bus-width in dts in order to fit the format in linux spi kernel so that spi-tx-bus-width & spi-rx-bus-width can be parsed properly. (2) Add quad and dual ability of transfer mode in spim controller. We have known that spi->mode is determined by dts & spi controller mode->bits. However, the SPI TX/RX DUAL/QUAD bits haven't been set now in spim controller and this leads to the fact that dts buswidth cannot be applied properly. [Release-log] N/A Change-Id: I6cf32362bf825a8d1871b3d64c653740df04c7ff Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7397940
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts index 2185239..fe0ca1e 100644 --- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts
@@ -175,8 +175,8 @@ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; reg = <0>; spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; };