blob: a11a809d3f49a68f0caa2dc0226bd5c64e12fe77 [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
developera1c200a2022-03-04 20:10:00 +08005 compatible = "mediatek,mt7981-spim-snand-2500wan-gmac2-rfb";
developer24455dd2021-10-28 10:55:41 +08006 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
developer63866c92021-11-15 12:05:13 +080016 nmbm_spim_nand {
developer24455dd2021-10-28 10:55:41 +080017 compatible = "generic,nmbm";
18
19 #address-cells = <1>;
20 #size-cells = <1>;
21
developer63866c92021-11-15 12:05:13 +080022 lower-mtd-device = <&spi_nand>;
developer24455dd2021-10-28 10:55:41 +080023 forced-create;
developer24455dd2021-10-28 10:55:41 +080024
25 partitions {
26 compatible = "fixed-partitions";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 partition@0 {
31 label = "BL2";
32 reg = <0x00000 0x0100000>;
33 read-only;
34 };
35
36 partition@100000 {
37 label = "u-boot-env";
38 reg = <0x0100000 0x0080000>;
39 };
40
developer63866c92021-11-15 12:05:13 +080041 partition@180000 {
developer24455dd2021-10-28 10:55:41 +080042 label = "Factory";
43 reg = <0x180000 0x0200000>;
44 };
45
46 partition@380000 {
47 label = "FIP";
48 reg = <0x380000 0x0200000>;
49 };
50
51 partition@580000 {
52 label = "ubi";
53 reg = <0x580000 0x4000000>;
54 };
55 };
56 };
57};
58
59&uart0 {
60 status = "okay";
61};
62
63&watchdog {
64 status = "okay";
65};
66
67&eth {
68 status = "okay";
69
70 gmac0: mac@0 {
71 compatible = "mediatek,eth-mac";
72 reg = <0>;
73 phy-mode = "2500base-x";
74
75 fixed-link {
76 speed = <2500>;
77 full-duplex;
78 pause;
79 };
80 };
81
82 gmac1: mac@1 {
83 compatible = "mediatek,eth-mac";
84 reg = <1>;
85 phy-mode = "2500base-x";
86
87 fixed-link {
88 speed = <2500>;
89 full-duplex;
90 pause;
91 };
92 };
93
94 mdio: mdio-bus {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
developer32805cd2022-01-06 17:08:06 +080098 phy5: phy@5 {
99 compatible = "ethernet-phy-id67c9.de0a";
100 reg = <5>;
101 reset-gpios = <&pio 14 1>;
developer8c5a08b2022-05-06 09:10:38 +0800102 reset-assert-us = <600>;
developer32805cd2022-01-06 17:08:06 +0800103 reset-deassert-us = <20000>;
104 phy-mode = "2500base-x";
105 };
developer24455dd2021-10-28 10:55:41 +0800106
107 switch@0 {
108 compatible = "mediatek,mt7531";
109 reg = <31>;
110 reset-gpios = <&pio 39 0>;
developer24455dd2021-10-28 10:55:41 +0800111 ports {
112 #address-cells = <1>;
113 #size-cells = <0>;
114
115 port@0 {
116 reg = <0>;
117 label = "lan1";
118 };
119
120 port@1 {
121 reg = <1>;
122 label = "lan2";
123 };
124
125 port@2 {
126 reg = <2>;
127 label = "lan3";
128 };
129
130 port@3 {
131 reg = <3>;
132 label = "lan4";
133 };
134
135 port@6 {
136 reg = <6>;
137 label = "cpu";
138 ethernet = <&gmac0>;
139 phy-mode = "2500base-x";
140
141 fixed-link {
142 speed = <2500>;
143 full-duplex;
144 pause;
145 };
146 };
147 };
148 };
149 };
150};
151
152&hnat {
153 mtketh-wan = "eth1";
154 mtketh-lan = "lan";
155 mtketh-max-gmac = <2>;
156 status = "okay";
157};
158
developer63866c92021-11-15 12:05:13 +0800159&spi0 {
developer24455dd2021-10-28 10:55:41 +0800160 pinctrl-names = "default";
developer63866c92021-11-15 12:05:13 +0800161 pinctrl-0 = <&spi0_flash_pins>;
developer24455dd2021-10-28 10:55:41 +0800162 status = "okay";
developer63866c92021-11-15 12:05:13 +0800163 spi_nand: spi_nand@0 {
developer24455dd2021-10-28 10:55:41 +0800164 #address-cells = <1>;
165 #size-cells = <1>;
developer63866c92021-11-15 12:05:13 +0800166 compatible = "spi-nand";
167 reg = <0>;
168 spi-max-frequency = <52000000>;
169 spi-tx-buswidth = <4>;
170 spi-rx-buswidth = <4>;
developer24455dd2021-10-28 10:55:41 +0800171 };
172};
173
174&spi1 {
175 pinctrl-names = "default";
176 pinctrl-0 = <&spic_pins>;
177 status = "disabled";
178};
179
180&pio {
181
developer63866c92021-11-15 12:05:13 +0800182 i2c_pins: i2c-pins-g0 {
183 mux {
184 function = "i2c";
185 groups = "i2c0_0";
186 };
187 };
188
189 pcm_pins: pcm-pins-g0 {
190 mux {
191 function = "pcm";
192 groups = "pcm";
193 };
194 };
195
196 pwm0_pin: pwm0-pin-g0 {
197 mux {
198 function = "pwm";
199 groups = "pwm0_0";
200 };
201 };
202
203 pwm1_pin: pwm1-pin-g0 {
204 mux {
205 function = "pwm";
206 groups = "pwm1_0";
207 };
208 };
209
210 pwm2_pin: pwm2-pin {
211 mux {
212 function = "pwm";
213 groups = "pwm2";
214 };
215 };
216
217 spi0_flash_pins: spi0-pins {
developer24455dd2021-10-28 10:55:41 +0800218 mux {
developer63866c92021-11-15 12:05:13 +0800219 function = "spi";
220 groups = "spi0", "spi0_wp_hold";
developer24455dd2021-10-28 10:55:41 +0800221 };
developer66b31fc2021-12-27 17:12:45 +0800222
223 conf-pu {
224 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
225 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800226 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800227 };
228
229 conf-pd {
230 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
231 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800232 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800233 };
developer24455dd2021-10-28 10:55:41 +0800234 };
235
236 spic_pins: spi1-pins {
237 mux {
238 function = "spi";
239 groups = "spi1_1";
240 };
241 };
developer63866c92021-11-15 12:05:13 +0800242
243 uart1_pins: uart1-pins-g1 {
244 mux {
245 function = "uart";
246 groups = "uart1_1";
247 };
248 };
249
250 uart2_pins: uart2-pins-g1 {
251 mux {
252 function = "uart";
253 groups = "uart2_1";
254 };
255 };
developer24455dd2021-10-28 10:55:41 +0800256};
257
258&xhci {
developer24455dd2021-10-28 10:55:41 +0800259 status = "okay";
260};