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developerba28e032021-12-07 10:40:00 +08001/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * xhci-mtk-unusuallib.h -- xhci toolkit header file
4 *
5 * Copyright (C) 2021 Mediatek Inc - http://www.mediatek.com
6 *
7 * Author: Zhanyong Wang <zhanyong.wang@mediatek.com>
8 */
9
10#ifndef __XHCI_MTK_UNUSUAL_H
11#define __XHCI_MTK_UNUSUAL_H
12
developerabd06d72022-03-03 16:13:41 +080013#include <dt-bindings/phy/phy.h>
14
developerba28e032021-12-07 10:40:00 +080015#define HQA_PREFIX_SIZE 4*1024
16
17#define BIT_WIDTH_1 1
18#define MSK_WIDTH_1 0x1
19#define VAL_MAX_WDITH_1 0x1
20
21#define STRNG_0_WIDTH_1 "0"
22#define STRNG_1_WIDTH_1 "1"
23
24#define BIT_WIDTH_2 2
25#define MSK_WIDTH_2 0x3
26#define VAL_MAX_WDITH_2 0x3
27#define STRNG_0_WIDTH_2 "00"
28#define STRNG_1_WIDTH_2 "01"
29#define STRNG_2_WIDTH_2 "10"
30#define STRNG_3_WIDTH_2 "11"
31
32
33#define BIT_WIDTH_3 3
34#define MSK_WIDTH_3 0x7
35#define VAL_MAX_WDITH_3 0x7
36#define STRNG_0_WIDTH_3 "000"
37#define STRNG_1_WIDTH_3 "001"
38#define STRNG_2_WIDTH_3 "010"
39#define STRNG_3_WIDTH_3 "011"
40#define STRNG_4_WIDTH_3 "100"
41#define STRNG_5_WIDTH_3 "101"
42#define STRNG_6_WIDTH_3 "110"
43#define STRNG_7_WIDTH_3 "111"
44
45#define BIT_WIDTH_4 4
46#define MSK_WIDTH_4 0xf
47#define VAL_MAX_WDITH_4 0xf
48#define STRNG_0_WIDTH_4 "0000"
49#define STRNG_1_WIDTH_4 "0001"
50#define STRNG_2_WIDTH_4 "0010"
51#define STRNG_3_WIDTH_4 "0011"
52#define STRNG_4_WIDTH_4 "0100"
53#define STRNG_5_WIDTH_4 "0101"
54#define STRNG_6_WIDTH_4 "0110"
55#define STRNG_7_WIDTH_4 "0111"
56#define STRNG_8_WIDTH_4 "1000"
57#define STRNG_9_WIDTH_4 "1001"
58#define STRNG_A_WIDTH_4 "1010"
59#define STRNG_B_WIDTH_4 "1011"
60#define STRNG_C_WIDTH_4 "1100"
61#define STRNG_D_WIDTH_4 "1101"
62#define STRNG_E_WIDTH_4 "1110"
63#define STRNG_F_WIDTH_4 "1111"
64
65/* specific */
66#define NAME_RG_USB20_INTR_EN "RG_USB20_INTR_EN"
67#define USB20_PHY_USBPHYACR0 0x00
68#define SHFT_RG_USB20_INTR_EN 5
69#define BV_RG_USB20_INTR_EN BIT(5)
70
71#define NAME_RG_USB20_VRT_VREF_SEL "RG_USB20_VRT_VREF_SEL"
72#define USB20_PHY_USBPHYACR1 0x04
73#define SHFT_RG_USB20_VRT_VREF_SEL 12
74#define BV_RG_USB20_VRT_VREF_SEL GENMASK(14, 12)
75
76#define NAME_RG_USB20_TERM_VREF_SEL "RG_USB20_TERM_VREF_SEL"
77#define SHFT_RG_USB20_TERM_VREF_SEL 8
78#define BV_RG_USB20_TERM_VREF_SEL GENMASK(10, 8)
79
80#define NAME_RG_USB20_HSTX_SRCTRL "RG_USB20_HSTX_SRCTRL"
81#define USB20_PHY_USBPHYACR5 0x14
82#define SHFT_RG_USB20_HSTX_SRCTRL 12
83#define BV_RG_USB20_HSTX_SRCTRL GENMASK(14, 12)
84
85#define NAME_RG_USB20_DISCTH "RG_USB20_DISCTH"
86#define USB20_PHY_USBPHYACR6 0x18
87#define SHFT_RG_USB20_DISCTH 4
88#define BV_RG_USB20_DISCTH GENMASK(8, 4)
89
90#define NAME_RG_CHGDT_EN "RG_CHGDT_EN"
91#define USB20_PHY_U2PHYBC12C 0x80
92#define SHFT_RG_CHGDT_EN 0
93#define BV_RG_CHGDT_EN BIT(0)
94
95#define ECHO_HQA(reg, _bd, _bw) do {\
96 val = usb20hqa_read(addr + (reg), \
97 SHFT_##_bd, \
98 BV_##_bd); \
99 val = bin2str(val, BIT_WIDTH_##_bw, str); \
100 cnt += sprintf(buf + cnt, " %-22s = %ib%s\n", \
101 NAME_##_bd, _bw, str); } while(0)
102
103
104#ifdef CONFIG_USB_XHCI_MTK_DEBUGFS
105static inline u32 usb20hqa_write(u32 __iomem *addr,
106 u32 shift, u32 mask, u32 value)
107{
108 u32 val;
109
110 val = readl(addr);
111 val &= ~((mask) << shift);
112 val |= (((value) & (mask)) << shift);
113 writel(val, addr);
114
115 return val;
116}
117static inline u32 usb20hqa_read(u32 __iomem *addr, u32 shift, u32 mask)
118{
119 u32 val;
120
121 val = readl(addr);
122 val &= mask;
123 val >>= shift;
124
125 return val;
126}
127
128u32 binary_write_width1(u32 __iomem *addr,
129 u32 shift, const char *buf);
130u32 binary_write_width3(u32 __iomem *addr,
131 u32 shift, const char *buf);
132u32 binary_write_width4(u32 __iomem *addr,
133 u32 shift, const char *buf);
134u32 bin2str(u32 value, u32 width, char *buffer);
135int query_phy_addr(struct device_node *np, int *start,
developerabd06d72022-03-03 16:13:41 +0800136 u32 *addr, u32 *length, int type);
137int query_reg_addr(struct platform_device *pdev, u32 *addr,
138 u32 *length, const char* name);
139
developerba28e032021-12-07 10:40:00 +0800140static inline int remaining(struct xhci_hcd_mtk *mtk)
141{
142 u32 surplus = 0;
143 if (mtk && mtk->hqa_pos < mtk->hqa_size)
144 surplus = mtk->hqa_size - mtk->hqa_pos;
145
146 return surplus;
147}
148
149#define hqa_info(mtk, fmt, args...) \
150 (mtk)->hqa_pos += snprintf((mtk)->hqa_buf + (mtk)->hqa_pos, \
151 remaining(mtk), fmt, ## args)
152
153#define DEVICE_ATTR_DECLARED(_name) \
154 extern struct device_attribute dev_attr_##_name;
155#define UNUSUAL_DEVICE_ATTR(_name) &dev_attr_##_name
156#else
157static inline u32 usb20hqa_write(u32 __iomem *addr,
158 u32 shift, u32 mask, u32 value)
159{
160 return 0;
161}
162static inline u32 usb20hqa_read(u32 __iomem *addr, u32 shift, u32 mask)
163{
164 return 0;
165}
166static inline u32 binary_write_width1(u32 __iomem *addr,
167 u32 shift, const char *buf)
168{
169 return 0;
170};
171static inline u32 binary_write_width3(u32 __iomem *addr,
172 u32 shift, const char *buf)
173{
174 return 0;
175};
176static inline u32 binary_write_width4(u32 __iomem *addr,
177 u32 shift, const char *buf)
178{
179 return 0;
180};
181static inline u32 bin2str(u32 value, u32 width, char *buffer)
182{
183 return 0;
184};
185static inline int query_phy_addr(struct device_node *np, int *start,
developerabd06d72022-03-03 16:13:41 +0800186 u32 *addr, u32 *length, int type)
187{
188 return -EPERM;
189}
190static inline int query_reg_addr(struct platform_device *pdev, u32 *addr,
191 u32 *length, const char* name)
developerba28e032021-12-07 10:40:00 +0800192{
193 return -EPERM;
194}
195static inline int remaining(int wrote)
196{
197 return 0;
198}
199#define hqa_info(mtk, fmt, args...)
200#define DEVICE_ATTR_DECLARED(...)
201#endif
202
203#include "unusual-declaration.h"
204
205#endif /* __XHCI_MTK_UNUSUAL_H */