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developerba28e032021-12-07 10:40:00 +08001/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * xhci-mtk-unusuallib.h -- xhci toolkit header file
4 *
5 * Copyright (C) 2021 Mediatek Inc - http://www.mediatek.com
6 *
7 * Author: Zhanyong Wang <zhanyong.wang@mediatek.com>
8 */
9
10#ifndef __XHCI_MTK_UNUSUAL_H
11#define __XHCI_MTK_UNUSUAL_H
12
13#define HQA_PREFIX_SIZE 4*1024
14
15#define BIT_WIDTH_1 1
16#define MSK_WIDTH_1 0x1
17#define VAL_MAX_WDITH_1 0x1
18
19#define STRNG_0_WIDTH_1 "0"
20#define STRNG_1_WIDTH_1 "1"
21
22#define BIT_WIDTH_2 2
23#define MSK_WIDTH_2 0x3
24#define VAL_MAX_WDITH_2 0x3
25#define STRNG_0_WIDTH_2 "00"
26#define STRNG_1_WIDTH_2 "01"
27#define STRNG_2_WIDTH_2 "10"
28#define STRNG_3_WIDTH_2 "11"
29
30
31#define BIT_WIDTH_3 3
32#define MSK_WIDTH_3 0x7
33#define VAL_MAX_WDITH_3 0x7
34#define STRNG_0_WIDTH_3 "000"
35#define STRNG_1_WIDTH_3 "001"
36#define STRNG_2_WIDTH_3 "010"
37#define STRNG_3_WIDTH_3 "011"
38#define STRNG_4_WIDTH_3 "100"
39#define STRNG_5_WIDTH_3 "101"
40#define STRNG_6_WIDTH_3 "110"
41#define STRNG_7_WIDTH_3 "111"
42
43#define BIT_WIDTH_4 4
44#define MSK_WIDTH_4 0xf
45#define VAL_MAX_WDITH_4 0xf
46#define STRNG_0_WIDTH_4 "0000"
47#define STRNG_1_WIDTH_4 "0001"
48#define STRNG_2_WIDTH_4 "0010"
49#define STRNG_3_WIDTH_4 "0011"
50#define STRNG_4_WIDTH_4 "0100"
51#define STRNG_5_WIDTH_4 "0101"
52#define STRNG_6_WIDTH_4 "0110"
53#define STRNG_7_WIDTH_4 "0111"
54#define STRNG_8_WIDTH_4 "1000"
55#define STRNG_9_WIDTH_4 "1001"
56#define STRNG_A_WIDTH_4 "1010"
57#define STRNG_B_WIDTH_4 "1011"
58#define STRNG_C_WIDTH_4 "1100"
59#define STRNG_D_WIDTH_4 "1101"
60#define STRNG_E_WIDTH_4 "1110"
61#define STRNG_F_WIDTH_4 "1111"
62
63/* specific */
64#define NAME_RG_USB20_INTR_EN "RG_USB20_INTR_EN"
65#define USB20_PHY_USBPHYACR0 0x00
66#define SHFT_RG_USB20_INTR_EN 5
67#define BV_RG_USB20_INTR_EN BIT(5)
68
69#define NAME_RG_USB20_VRT_VREF_SEL "RG_USB20_VRT_VREF_SEL"
70#define USB20_PHY_USBPHYACR1 0x04
71#define SHFT_RG_USB20_VRT_VREF_SEL 12
72#define BV_RG_USB20_VRT_VREF_SEL GENMASK(14, 12)
73
74#define NAME_RG_USB20_TERM_VREF_SEL "RG_USB20_TERM_VREF_SEL"
75#define SHFT_RG_USB20_TERM_VREF_SEL 8
76#define BV_RG_USB20_TERM_VREF_SEL GENMASK(10, 8)
77
78#define NAME_RG_USB20_HSTX_SRCTRL "RG_USB20_HSTX_SRCTRL"
79#define USB20_PHY_USBPHYACR5 0x14
80#define SHFT_RG_USB20_HSTX_SRCTRL 12
81#define BV_RG_USB20_HSTX_SRCTRL GENMASK(14, 12)
82
83#define NAME_RG_USB20_DISCTH "RG_USB20_DISCTH"
84#define USB20_PHY_USBPHYACR6 0x18
85#define SHFT_RG_USB20_DISCTH 4
86#define BV_RG_USB20_DISCTH GENMASK(8, 4)
87
88#define NAME_RG_CHGDT_EN "RG_CHGDT_EN"
89#define USB20_PHY_U2PHYBC12C 0x80
90#define SHFT_RG_CHGDT_EN 0
91#define BV_RG_CHGDT_EN BIT(0)
92
93#define ECHO_HQA(reg, _bd, _bw) do {\
94 val = usb20hqa_read(addr + (reg), \
95 SHFT_##_bd, \
96 BV_##_bd); \
97 val = bin2str(val, BIT_WIDTH_##_bw, str); \
98 cnt += sprintf(buf + cnt, " %-22s = %ib%s\n", \
99 NAME_##_bd, _bw, str); } while(0)
100
101
102#ifdef CONFIG_USB_XHCI_MTK_DEBUGFS
103static inline u32 usb20hqa_write(u32 __iomem *addr,
104 u32 shift, u32 mask, u32 value)
105{
106 u32 val;
107
108 val = readl(addr);
109 val &= ~((mask) << shift);
110 val |= (((value) & (mask)) << shift);
111 writel(val, addr);
112
113 return val;
114}
115static inline u32 usb20hqa_read(u32 __iomem *addr, u32 shift, u32 mask)
116{
117 u32 val;
118
119 val = readl(addr);
120 val &= mask;
121 val >>= shift;
122
123 return val;
124}
125
126u32 binary_write_width1(u32 __iomem *addr,
127 u32 shift, const char *buf);
128u32 binary_write_width3(u32 __iomem *addr,
129 u32 shift, const char *buf);
130u32 binary_write_width4(u32 __iomem *addr,
131 u32 shift, const char *buf);
132u32 bin2str(u32 value, u32 width, char *buffer);
133int query_phy_addr(struct device_node *np, int *start,
134 u32 *addr, u32 *length);
135static inline int remaining(struct xhci_hcd_mtk *mtk)
136{
137 u32 surplus = 0;
138 if (mtk && mtk->hqa_pos < mtk->hqa_size)
139 surplus = mtk->hqa_size - mtk->hqa_pos;
140
141 return surplus;
142}
143
144#define hqa_info(mtk, fmt, args...) \
145 (mtk)->hqa_pos += snprintf((mtk)->hqa_buf + (mtk)->hqa_pos, \
146 remaining(mtk), fmt, ## args)
147
148#define DEVICE_ATTR_DECLARED(_name) \
149 extern struct device_attribute dev_attr_##_name;
150#define UNUSUAL_DEVICE_ATTR(_name) &dev_attr_##_name
151#else
152static inline u32 usb20hqa_write(u32 __iomem *addr,
153 u32 shift, u32 mask, u32 value)
154{
155 return 0;
156}
157static inline u32 usb20hqa_read(u32 __iomem *addr, u32 shift, u32 mask)
158{
159 return 0;
160}
161static inline u32 binary_write_width1(u32 __iomem *addr,
162 u32 shift, const char *buf)
163{
164 return 0;
165};
166static inline u32 binary_write_width3(u32 __iomem *addr,
167 u32 shift, const char *buf)
168{
169 return 0;
170};
171static inline u32 binary_write_width4(u32 __iomem *addr,
172 u32 shift, const char *buf)
173{
174 return 0;
175};
176static inline u32 bin2str(u32 value, u32 width, char *buffer)
177{
178 return 0;
179};
180static inline int query_phy_addr(struct device_node *np, int *start,
181 u32 *addr, u32 *length)
182{
183 return -EPERM;
184}
185static inline int remaining(int wrote)
186{
187 return 0;
188}
189#define hqa_info(mtk, fmt, args...)
190#define DEVICE_ATTR_DECLARED(...)
191#endif
192
193#include "unusual-declaration.h"
194
195#endif /* __XHCI_MTK_UNUSUAL_H */