| developer | c66d4ac | 2021-09-17 16:27:09 +0800 | [diff] [blame] | 1 | From cea0f76a483d1270ac6f6513964e3e75193dda48 Mon Sep 17 00:00:00 2001 |
| 2 | From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> |
| 3 | Date: Mon, 29 Jun 2020 15:00:52 +0300 |
| 4 | Subject: [PATCH 3/5] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR |
| 5 | PHY |
| 6 | |
| 7 | Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed |
| 8 | Processing System Gigabit Transceiver which provides PHY capabilities to |
| 9 | USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. |
| 10 | |
| 11 | Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> |
| 12 | Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 13 | Reviewed-by: Rob Herring <robh@kernel.org> |
| 14 | Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com |
| 15 | Signed-off-by: Vinod Koul <vkoul@kernel.org> |
| 16 | --- |
| 17 | include/dt-bindings/phy/phy.h | 1 + |
| 18 | 1 file changed, 1 insertion(+) |
| 19 | |
| 20 | diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h |
| 21 | index 3727ef72138b..36e8c241cf48 100644 |
| 22 | --- a/include/dt-bindings/phy/phy.h |
| 23 | +++ b/include/dt-bindings/phy/phy.h |
| 24 | @@ -18,5 +18,6 @@ |
| 25 | #define PHY_TYPE_UFS 5 |
| 26 | #define PHY_TYPE_DP 6 |
| 27 | #define PHY_TYPE_XPCS 7 |
| 28 | +#define PHY_TYPE_SGMII 8 |
| 29 | |
| 30 | #endif /* _DT_BINDINGS_PHY */ |
| 31 | -- |
| 32 | 2.18.0 |
| 33 | |