| From cea0f76a483d1270ac6f6513964e3e75193dda48 Mon Sep 17 00:00:00 2001 |
| From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> |
| Date: Mon, 29 Jun 2020 15:00:52 +0300 |
| Subject: [PATCH 3/5] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR |
| PHY |
| |
| Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed |
| Processing System Gigabit Transceiver which provides PHY capabilities to |
| USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. |
| |
| Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> |
| Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| Reviewed-by: Rob Herring <robh@kernel.org> |
| Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com |
| Signed-off-by: Vinod Koul <vkoul@kernel.org> |
| --- |
| include/dt-bindings/phy/phy.h | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h |
| index 3727ef72138b..36e8c241cf48 100644 |
| --- a/include/dt-bindings/phy/phy.h |
| +++ b/include/dt-bindings/phy/phy.h |
| @@ -18,5 +18,6 @@ |
| #define PHY_TYPE_UFS 5 |
| #define PHY_TYPE_DP 6 |
| #define PHY_TYPE_XPCS 7 |
| +#define PHY_TYPE_SGMII 8 |
| |
| #endif /* _DT_BINDINGS_PHY */ |
| -- |
| 2.18.0 |
| |