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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 772156434670e0105a94dd9a7dbede093537f36e / . / target / linux / mediatek / patches-5.4 / 752-net-dsa-phy-coverity-scan.patch
blob: 17921e8bc17e764421684431e9be5efdf1125fe4 [file] [log] [blame]
developer91044d52022-11-28 10:01:04 +0800[diff] [blame]1diff -Naur a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
2--- a/drivers/net/dsa/mt7530.c 2022-11-25 14:10:39.452491570 +0800
3+++ b/drivers/net/dsa/mt7530.c 2022-11-28 09:47:11.157096408 +0800
4@@ -2476,7 +2476,7 @@
5 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
6 {
7 struct mt7530_priv *priv = ds->priv;
8- phy_interface_t interface;
9+ phy_interface_t interface = PHY_INTERFACE_MODE_NA;
10 int speed;
11
12 switch (port) {
13@@ -2496,6 +2496,8 @@
14 priv->p6_interface = interface;
15 break;
16 };
17+ if (interface == PHY_INTERFACE_MODE_NA)
18+ dev_err(priv->dev, "invalid interface\n");
19
20 if (interface == PHY_INTERFACE_MODE_2500BASEX)
21 speed = SPEED_2500;
22diff -Naur a/drivers/net/dsa/mt7531_phy.c b/drivers/net/dsa/mt7531_phy.c
23--- a/drivers/net/dsa/mt7531_phy.c 2022-11-25 14:10:47.032465430 +0800
24+++ b/drivers/net/dsa/mt7531_phy.c 2022-11-29 09:56:05.024665073 +0800
25@@ -252,7 +252,7 @@
26 u16 dev1e_17a_tmp, dev1e_e0_tmp;
27
28 /* *** Iext/Rext Cal start ************ */
29- all_ana_cal_status = ANACAL_INIT;
30+ //all_ana_cal_status = ANACAL_INIT;
31 /* analog calibration enable, Rext calibration enable */
32 /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
33 /* 1e_dc[0]:rg_txvos_calen */
34@@ -296,7 +296,7 @@
35 all_ana_cal_status = ANACAL_FINISH;
36 //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
37 } else {
38- dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
39+ //dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
40 dev1e_e0_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0xe0);
41 if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
42 all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
43@@ -718,32 +718,34 @@
44 } else if (phyaddr == 1) {
45 if (calibration_pair == ANACAL_PAIR_A)
46 tx_amp_temp = tx_amp_temp - 1;
47- else if(calibration_pair == ANACAL_PAIR_B)
48- tx_amp_temp = tx_amp_temp ;
49+ //else if(calibration_pair == ANACAL_PAIR_B)
50+ // tx_amp_temp = tx_amp_temp;
51 else if(calibration_pair == ANACAL_PAIR_C)
52 tx_amp_temp = tx_amp_temp - 1;
53 else if(calibration_pair == ANACAL_PAIR_D)
54 tx_amp_temp = tx_amp_temp - 1;
55 } else if (phyaddr == 2) {
56- if (calibration_pair == ANACAL_PAIR_A)
57- tx_amp_temp = tx_amp_temp;
58- else if(calibration_pair == ANACAL_PAIR_B)
59+ //if (calibration_pair == ANACAL_PAIR_A)
60+ // tx_amp_temp = tx_amp_temp;
61+ //else if(calibration_pair == ANACAL_PAIR_B)
62+ if(calibration_pair == ANACAL_PAIR_B)
63 tx_amp_temp = tx_amp_temp - 1;
64- else if(calibration_pair == ANACAL_PAIR_C)
65- tx_amp_temp = tx_amp_temp;
66+ //else if(calibration_pair == ANACAL_PAIR_C)
67+ // tx_amp_temp = tx_amp_temp;
68 else if(calibration_pair == ANACAL_PAIR_D)
69 tx_amp_temp = tx_amp_temp - 1;
70- } else if (phyaddr == 3) {
71- tx_amp_temp = tx_amp_temp;
72+ //} else if (phyaddr == 3) {
73+ // tx_amp_temp = tx_amp_temp;
74 } else if (phyaddr == 4) {
75- if (calibration_pair == ANACAL_PAIR_A)
76- tx_amp_temp = tx_amp_temp;
77- else if(calibration_pair == ANACAL_PAIR_B)
78+ //if (calibration_pair == ANACAL_PAIR_A)
79+ // tx_amp_temp = tx_amp_temp;
80+ //else if(calibration_pair == ANACAL_PAIR_B)
81+ if(calibration_pair == ANACAL_PAIR_B)
82 tx_amp_temp = tx_amp_temp - 1;
83- else if(calibration_pair == ANACAL_PAIR_C)
84- tx_amp_temp = tx_amp_temp;
85- else if(calibration_pair == ANACAL_PAIR_D)
86- tx_amp_temp = tx_amp_temp;
87+ //else if(calibration_pair == ANACAL_PAIR_C)
88+ // tx_amp_temp = tx_amp_temp;
89+ //else if(calibration_pair == ANACAL_PAIR_D)
90+ // tx_amp_temp = tx_amp_temp;
91 }
92 reg_temp = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
93 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
94@@ -858,7 +860,7 @@
95 reg_backup = 0x0000;
96 reg_backup |= ((tx_amp_temp << 10) | (tx_amp_temp << 0));
97 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x12, reg_backup);
98- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
99+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
100 //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
101 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
102 reg_tmp = ((reg_backup & 0x3f) >> 0);
103@@ -866,7 +868,7 @@
104 reg_backup = (reg_backup & (~0x3f));
105 reg_backup |= (tx_amp_temp << 0);
106 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x16, reg_backup);
107- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
108+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
109 //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
110 }
111 else if(calibration_pair == ANACAL_PAIR_B){
112@@ -876,7 +878,7 @@
113 reg_backup = 0x0000;
114 reg_backup |= ((tx_amp_temp << 8) | (tx_amp_temp << 0));
115 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x17, reg_backup);
116- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
117+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
118 //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
119 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
120 reg_tmp = ((reg_backup & 0x3f) >> 0);
121@@ -884,7 +886,7 @@
122 reg_backup = (reg_backup & (~0x3f));
123 reg_backup |= (tx_amp_temp << 0);
124 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x18, reg_backup);
125- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
126+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
127 //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
128 }
129 else if(calibration_pair == ANACAL_PAIR_C){
130@@ -894,7 +896,7 @@
131 reg_backup = (reg_backup & (~0x3f00));
132 reg_backup |= (tx_amp_temp << 8);
133 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x19, reg_backup);
134- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
135+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
136 //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
137 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
138 reg_tmp = ((reg_backup & 0x3f) >> 0);
139@@ -902,7 +904,7 @@
140 reg_backup = (reg_backup & (~0x3f));
141 reg_backup |= (tx_amp_temp << 0);
142 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x20, reg_backup);
143- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
144+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
145 //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
146 }
147 else if(calibration_pair == ANACAL_PAIR_D){
148@@ -912,7 +914,7 @@
149 reg_backup = (reg_backup & (~0x3f00));
150 reg_backup |= (tx_amp_temp << 8);
151 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x21, reg_backup);
152- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
153+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
154 //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
155 reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
156 reg_tmp = ((reg_backup & 0x3f) >> 0);
157@@ -920,7 +922,7 @@
158 reg_backup = (reg_backup & (~0x3f));
159 reg_backup |= (tx_amp_temp << 0);
160 tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x22, reg_backup);
161- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
162+ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
163 //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
164 }
165
166@@ -1352,7 +1354,7 @@
167
168 int mt7531_phy_setup(struct dsa_switch *ds)
169 {
170- int ret;
171+ int ret = 0;
172 int i;
173
developer0b16f962022-12-22 12:25:34 +0800[diff] [blame]174 mt7531_phy_setting(ds);
175