| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * switch_ioctl.h: switch(ioctl) set API |
| 3 | */ |
| 4 | |
| 5 | #ifndef SWITCH_IOCTL_H |
| 6 | #define SWITCH_IOCTL_H |
| 7 | |
| 8 | #define ETH_DEVNAME "eth0" |
| 9 | #define BR_DEVNAME "br-lan" |
| 10 | |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 11 | #define RAETH_MII_READ 0x89F3 |
| 12 | #define RAETH_MII_WRITE 0x89F4 |
| 13 | #define RAETH_ESW_PHY_DUMP 0x89F7 |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 14 | |
| 15 | struct esw_reg { |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 16 | unsigned int off; |
| 17 | unsigned int val; |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 18 | }; |
| 19 | |
| 20 | struct ra_mii_ioctl_data { |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 21 | __u16 phy_id; |
| 22 | __u16 reg_num; |
| 23 | __u32 val_in; |
| 24 | __u32 val_out; |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 25 | }; |
| 26 | |
| 27 | struct ra_switch_ioctl_data { |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 28 | unsigned int cmd; |
| 29 | unsigned int on_off; |
| 30 | unsigned int port; |
| 31 | unsigned int bw; |
| 32 | unsigned int vid; |
| 33 | unsigned int fid; |
| 34 | unsigned int port_map; |
| 35 | unsigned int rx_port_map; |
| 36 | unsigned int tx_port_map; |
| 37 | unsigned int igmp_query_interval; |
| 38 | unsigned int reg_addr; |
| 39 | unsigned int reg_val; |
| 40 | unsigned int mode; |
| 41 | unsigned int qos_queue_num; |
| 42 | unsigned int qos_type; |
| 43 | unsigned int qos_pri; |
| 44 | unsigned int qos_dscp; |
| 45 | unsigned int qos_table_idx; |
| 46 | unsigned int qos_weight; |
| 47 | unsigned char mac[6]; |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | extern int chip_name; |
| 51 | |
| developer | 0c1ae57 | 2021-05-27 15:32:01 +0800 | [diff] [blame] | 52 | int switch_ioctl_init(void); |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 53 | void switch_ioctl_fini(void); |
| 54 | int reg_read_ioctl(unsigned int offset, unsigned int *value); |
| 55 | int reg_write_ioctl(unsigned int offset, unsigned int value); |
| 56 | int phy_dump_ioctl(unsigned int phy_addr); |
| 57 | int mii_mgr_cl22_read_ioctl(unsigned int port_num, unsigned int reg, |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 58 | unsigned int *value); |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 59 | int mii_mgr_cl22_write_ioctl(unsigned int port_num, unsigned int reg, |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 60 | unsigned int value); |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 61 | int mii_mgr_cl45_read_ioctl(unsigned int port_num, unsigned int dev, |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 62 | unsigned int reg, unsigned int *value); |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 63 | int mii_mgr_cl45_write_ioctl(unsigned int port_num, unsigned int dev, |
| developer | cd707d2 | 2024-08-06 10:44:11 +0800 | [diff] [blame] | 64 | unsigned int reg, unsigned int value); |
| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 65 | #endif |